CN103095158B - Constant-current control circuit in AC-DC converter and voltage generator - Google Patents
Constant-current control circuit in AC-DC converter and voltage generator Download PDFInfo
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Abstract
The present invention relates to the constant-current control circuit in AC-DC converter and voltage generator.Constant-current control circuit of the present invention comprises switching tube, resistance, the first comparator, voltage generator, the second comparator, and this first comparator first input voltage is reference voltage.Described switching tube and described resistant series, so that the electric current flowing through this switching tube produces pressure drop on this resistance.Described first comparator compares described resistance both end voltage and described reference voltage.Described voltage generator receives the comparative result of described first comparator, and increases according to this comparative result or reduce its output voltage values.Described second comparator first input end receives the output voltage of described voltage generator, and when this voltage is equal with described resistance both end voltage, this second comparator turns off described switching tube.Constant-current control circuit of the present invention eliminates the adverse effect that time delay brings constant-current circuit, can be applied in integrated circuit (IC) design.
Description
Technical field
The present invention relates to integrated circuit, particularly relate to the constant-current control circuit in AC-DC converter.
Background technology
Fig. 1 is the constant-current control circuit in a kind of AC-DC converter of the prior art.In Fig. 1, Ton signal is the start signal of PWM (pulse width modulation) signal, and it is provided by other circuit in chip.When pwm signal is high level, power switch pipe M1 opens, and now primary inductance voltage is busbar voltage VIN after bridge, and primary inductance electric current linearly increases with slope VIN/Lp; Wherein Lp is primary inductance value.After power switch pipe M1 opens, primary inductance electric current is flow on resistance Rcs by power switch pipe M1.When resistance Rcs both end voltage Vcs reaches internal reference voltage Vref, comparator U1 exports high level with triggered RS flip-flop U2; Rest-set flip-flop U2 exports cut-off signals to buffer U3, makes it turn off by buffer U3 driving power switching tube M1.After power switch pipe M1 is turned off, primary inductance current conversion is to secondary inductance, and the voltage of resistance Rcs is down to 0 volt.Concrete Vref signal, Vcs signal, pwm signal waveform relationship are Vref signal in Fig. 1, Vcs signal, pwm signal waveform relationship schematic diagram see Fig. 2, Fig. 2.
But, in the constant-current control circuit of reality, comparator U1 has delay, and buffer U3 driving force is limited, and power switch pipe M1 exists parasitic capacitance, these factors make switching tube M1 reception cut-off signals there is certain delay td (as shown in Figure 3); That is, buffer, can not on-off switching tube M1 immediately after receiving pwm signal (i.e. cut-off signals), but needs to turn off after one section of time delay td.Meanwhile, because the slope flowing through the electric current of resistance Rcs is VIN/Lp, therefore when busbar voltage VIN after bridge increases, the slope flowing through the electric current of resistance Rcs also can increase, but time delay td is constant, therefore makes the overshoot of Vcs constantly increase, directly affect output current precision, see Fig. 3.The relation schematic diagram that during Tu3Shi city Electrical change, Vcs overshoot changes thereupon.Except above-mentioned delay, also there is certain difference in the threshold voltage of the NMOS tube that different manufacturers is produced and parasitic capacitance, often the NMOS tube of different model can cause the speed of service of different constant-current control circuits.
In sum, existing constant-current control circuit is due to the existence of the limited driving force of internal buffer and its external power switching tube parasitic parameter driven, and the delay that prototype part has itself, the cut-off signals causing switching tube to receive has delay, resistance both end voltage produces overshoot relative to reference voltage, reduce power switch pipe turn-off speed, directly affect the precision of output current.
Summary of the invention
The invention provides the constant-current control circuit in a kind of AC-DC converter that can overcome the above problems and voltage generator.
In first aspect, the invention provides a kind of constant-current control circuit.This constant-current control circuit comprises switching tube, resistance, the first comparator, voltage generator, the second comparator, and this first comparator first input voltage is reference voltage.This switching tube and this resistant series, so that the electric current flowing through this switching tube produces pressure drop on this resistance.This first comparator compares this resistance both end voltage and reference voltage.This voltage generator receives the comparative result of described first comparator, and increases according to this comparative result or reduce its output voltage values.This second comparator first input end receives the output voltage of described voltage generator, and when this voltage is equal with described resistance both end voltage, this second comparator turns off described switching tube.
In second aspect, the invention provides a kind of voltage generator.This voltage generator comprises the first d type flip flop, full adder, the second d type flip flop, decoder.This first d type flip flop input is connected to supply voltage, and described first d type flip flop output is connected with this full adder control end.This full adder input is connected with this second d type flip flop output, and this full adder output is connected with this second d type flip flop input.This second d type flip flop output is connected to described decoder.
The present invention by increasing by a comparator and increasing by a voltage generator of the present invention on existing constant-current control circuit, to solve in existing constant-current control circuit resistance both end voltage relative to reference voltage overshooting problem, reduce the delay that cut-off signals arrives switching tube, make constant-current control accuracy and NMOS tube parameter have nothing to do simultaneously, improve output current precision.
Accompanying drawing explanation
Fig. 1 is the constant-current control circuit in a kind of AC-DC converter of the prior art;
Fig. 2 is Vref signal in Fig. 1, Vcs signal, pwm signal waveform relationship schematic diagram;
The relation schematic diagram that during Tu3Shi city Electrical change, Vcs overshoot changes thereupon;
Fig. 4 is the constant-current control circuit schematic diagram of one embodiment of the invention;
Fig. 5 is each module output signal waveform relationship schematic diagram in Fig. 4 circuit;
Fig. 6 is the specific implementation circuit diagram of the voltage generator of one embodiment of the invention;
Fig. 7 is a specific implementation circuit diagram of Fig. 4 constant-current control circuit.
Embodiment
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Fig. 4 is the constant-current control circuit schematic diagram of one embodiment of the invention, and this constant-current control circuit comprises voltage generator U5, comparator U4 and existing constant-current control circuit; Wherein, existing constant-current control circuit comprises bridge rectifier, electric capacity C1, transformer T1, diode D1, electric capacity C2, power switch pipe M1, buffer U3, rest-set flip-flop U2, comparator U1, reference voltage Vref, resistance Rcs.
In Fig. 4, comparator U4 positive input is connected to the tie point between resistance Rcs and power switch pipe M1, and namely comparator U4 forward input voltage is resistance Rcs both end voltage Vcs; Comparator U4 negative input is connected with chip internal reference voltage source, and namely comparator U4 negative sense input voltage is reference voltage Vref; Comparator U4 output is connected to the input Ctrl of voltage generator U5.
Voltage generator U5 output VOCP is connected to the negative input of comparator U1; Comparator U1 positive input is connected to the tie point between resistance Rcs and power switch pipe M1, and namely comparator U1 positive input is connected with comparator U4 positive input, then comparator U1 forward input voltage is resistance Rcs both end voltage Vcs; Comparator U1 output is connected to R end (reset terminal) of rest-set flip-flop U2.
S end (set end) of rest-set flip-flop U2 receives Ton signal, and this Ton signal is provided by other circuit of chip internal, this rest-set flip-flop U2 is for generation of PWM (pulse width modulation) signal, concrete signal waveform is each module output signal waveform relationship schematic diagram in Fig. 4 circuit see Fig. 5, Fig. 5.Q end (output) of rest-set flip-flop U2 is connected with the input of buffer U3.The output of buffer U3 is connected to the grid of power switch pipe M1 (NMOS tube), to drive unlatching and the shutoff of this power switch pipe M1.
Power switch pipe M1 drain electrode is connected to the primary inductance Lp of transformer T1.Transformer T1 primary inductance Lp voltage is busbar voltage VIN after bridge.When power switch pipe M1 opens, primary inductance electric current transfers to resistance Rcs through power switch pipe M1, thus forms pressure drop Vcs at resistance Rcs two ends.When power switch pipe M1 turns off, transformer T1 secondary inductance Ls by diode D1, electric capacity C2 for outside LDE lamp provides electric energy.
Set forth Fig. 4 circuit specific works principle below.
In Fig. 4, mains input voltage is delivered to transformer T1 after bridge rectifier, electric capacity C1, then transformer T1 primary inductance Lp voltage is busbar voltage VIN after bridge.Primary inductance Lp connects with power switch pipe M1, resistance Rcs, then the electric current flowing through resistance Rcs is primary inductance electric current
therefore, resistance Rcs both end voltage Vcs meets
wherein, VIN is the primary inductance voltage of transformer T1, and LP is primary inductance value, and t is the time, and the concrete waveform of this Vcs is see Fig. 5.
Comparator U1 is used for the magnitude relationship between comparison resistance Rcs both end voltage Vcs and voltage generator U5 output voltage VO CP, and when this voltage Vcs is more than VOCP, comparator U1 output high level is held to the R of rest-set flip-flop U2.Now, rest-set flip-flop U2 output is reset to 0.That is, the pwm signal that rest-set flip-flop U2 exports becomes low level.Because buffer U3, power switch pipe M1 can cause time delay td, when the pwm signal that therefore rest-set flip-flop U2 exports becomes low level, power switch pipe M1 can not be turned off immediately.
In this timing period, the reference voltage Vref that its forward input voltage Vcs and its negative sense input compares by comparator U4; If voltage Vcs is greater than reference voltage Vref, then comparator U4 exports high level to voltage generator U5; Otherwise if voltage Vcs is less than reference voltage Vref, then comparator U4 output low level is to voltage generator U5.
Voltage generator U5 is for generation of so a kind of voltage VOCP, and the size of this voltage is adjustable, and this adjustment step-length is discrete, and concrete step sizes can be determined according to precision needed for constant-current control circuit; Such as Vstep=Vref × 1%; Wherein, Vstep is step sizes, and Vref is reference voltage.
When the input (Ctrl end) of voltage generator U5 receives high level (when being greater than reference voltage Vref as voltage Vcs), the voltage that this voltage generator U5 exports reduces a step-length.Otherwise when the input (Ctrl end) of voltage generator U5 receives low level (when not exceeding reference voltage Vref all the time when Vcs voltage in current period), the voltage that this voltage generator U5 exports increases a step-length.Concrete principle is see Fig. 5.Finally, voltage generator U5 can switch on the magnitude of voltage that two differences are a step-length, thus the balance under reaching long-range.Therefore, the adverse effect that causes of Fig. 4 circuit for eliminating time delay td.
Fig. 6 is the specific implementation circuit diagram of the voltage generator of one embodiment of the invention.
This voltage generator comprises two input node Ctrl (Controlling vertex) and CLK (clock node), and comprises an output node Vocp; Wherein, node CLK is connected with the output of rest-set flip-flop U2, and node Ctrl is connected with the output of comparator U4, and node Vocp is connected with the negative input of comparator U1.
In Fig. 6, this voltage generator comprises inverter, d type flip flop U51, full adder U52, many bits d type flip flop U53, decoder.In an example, this decoder is 8421 decoders, this 8421 decoder comprises multiple interrupteur SW 0, SWx......SWn-1, and comprise respectively with resistance R0, R1......Rx......RWn-1 of the plurality of switch in parallel, this 8421 decoder also comprises and the current source Iref of the plurality of resistant series and resistance Rref.
In Fig. 6, D end (input) of d type flip flop U51 is connected with VDD (supply voltage); Reset end (reset terminal) of d type flip flop U51 is connected to the Ctrl node (Controlling vertex) of this voltage generator; CLK end (clock end) of d type flip flop U51 is connected to the CLK node of this voltage generator by an inverter; Q end (output) of d type flip flop U51 holds (control end) to be connected with the A of full adder U52.B end (data terminal) of full adder U52 is connected to the output of many bits d type flip flop U53; S end (output) of full adder U52 is connected to D end (input) of many bits d type flip flop U53.CLK end (clock end) of many bits d type flip flop U53 is connected to the CLK node of this voltage generator, and the output of many bits d type flip flop U53 is connected to decoder, and provides many bit informations for this decoder.The output of decoder is the output VOCP of this voltage generator.
In Fig. 6, when the CLK node of this voltage generator produces trailing edge and the Ctrl node of this voltage generator is low level, d type flip flop U51 output high level is held to the A of full adder U52.From full adder characteristic, when full adder A holds (control end) for high level, the output of full adder is that full adder B holds (input) data to add 1.Because the B end of full adder U52 is connected with the output of many bits d type flip flop U53, then the B end data of full adder comes from the output of many bits d type flip flop U53, and therefore, the now output of full adder is that the output data of many bits d type flip flop add 1.
When the CLK node of this voltage generator produces trailing edge and the Ctrl node of this voltage generator is high level, d type flip flop U51 is reset to 0, and namely d type flip flop U51 output low level is held to the A of full adder U52.From full adder characteristic, when full adder A holds (control end) for low level, the output of full adder is that full adder B holds (input) data to subtract 1.Because the B end of full adder U52 is connected with the output of many bits d type flip flop U53, then the B end data of full adder comes from the output of many bits d type flip flop U53, and therefore, the now output of full adder is that the output data of many bits d type flip flop add 1.
Therefore, when the CLK node of voltage generator produces trailing edge, if Ctrl node is low level, then d type flip flop U51 exports high level, and many bits full adder U52 performs B<0:n-1>+1 operation to fan-in according to B<0:n-1>; If Ctrl node is high level, d type flip flop U51 is reset to 0, and many bits full adder U52 is to input data B<0:n-1> executable operations B<0:n-1>-1 operation.
When the CLK node of voltage generator produces rising edge, many bits d type flip flop U53 obtains data from full adder U52 output, and these data are sent to the B end of full adder U52, so that this many bits d type flip flop U53 obtains the data increasing/reduce a step-length when next cycle.In addition, this many bits d type flip flop U53 exported data be sent to full adder U52 B end while, this many bits d type flip flop U53 is also exported data and is sent to decoder, so that this decoder controls unlatching and the shutoff of multi-position switch SW<0:n-1> by the output of this many bits d type flip flop U53.This multi-position switch SW<0:n-1> changes the resistance sizes of decoder by various combination, because the electric current (it is provided by continuous current source Iref) flowing through each resistance is fixing, therefore by the size of the output voltage VO CP of the incompatible regulation voltage generator of different switches set.As can be seen here, this voltage generator can produce the adjustable voltage of magnitude of voltage, concrete adjustment step-length obtains by the resistance value arranged in decoder, and this voltage generator increases or reduces magnitude of voltage to be determined according to Ctrl node (i.e. the output of comparator U4 is also Vref, Vcs magnitude relationship).
Fig. 7 is a specific implementation circuit diagram of Fig. 4 constant-current control circuit.In Fig. 7, voltage generator Ctrl node is connected with comparator U4 output, and voltage generator CLK node is connected to rest-set flip-flop output, and voltage generator output VOCP is connected to comparator U1 negative input.Other modules in this circuit and annexation thereof are see Fig. 4 and declaratives thereof.
In Fig. 7, when Vcs is greater than Vref, comparator U4 output high level is held to the Ctrl of voltage generator U5, then voltage generator is sent to comparator U1 negative input after Vcs value is deducted a step-length.When Vcs is less than Vref, comparator U4 output low level is held to the Ctrl of voltage generator U5, then voltage generator is sent to comparator U1 negative input after Vcs value is added a step-length.Finally make voltage generator be that the voltage of a step-length switches two differences, reach the balance under long-range.
It should be noted last that, above embodiment is only in order to illustrate technical scheme of the present invention and unrestricted, although with reference to preferred embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that, can modify to technical scheme of the present invention or equivalent replacement, and not depart from the spirit and scope of technical solution of the present invention.
Claims (9)
1. a constant-current control circuit, comprises switching tube (M1), resistance (Rcs), the first comparator, voltage generator, the second comparator, and this first comparator first input voltage is reference voltage;
Described switching tube (M1) is connected with described resistance (Rcs), so that the electric current flowing through this switching tube (M1) produces pressure drop on this resistance (Rcs);
Described first comparator compares described resistance both end voltage and described reference voltage;
Described voltage generator receives the comparative result of described first comparator, and increases according to this comparative result or reduce its output voltage values;
Described second comparator first input end receives the output voltage of described voltage generator, and when this voltage is equal with described resistance both end voltage, this second comparator turns off described switching tube (M1);
Described comparative result be described resistance both end voltage be greater than described reference voltage time, the voltage that described voltage generator exports reduces a step-length; At described comparative result for when in current period, described resistance both end voltage is less than described reference voltage all the time, the voltage that described voltage generator exports increases a step-length.
2. a kind of constant-current control circuit as claimed in claim 1, is characterized in that, described voltage generator comprises the first d type flip flop, full adder, the second d type flip flop, decoder;
Described first d type flip flop input is connected to supply voltage, described first d type flip flop output with
Described full adder control end is connected;
Described full adder input is connected with described second d type flip flop output, and described full adder output is connected with described second d type flip flop input;
Described second d type flip flop output is connected to described decoder.
3. a kind of constant-current control circuit as claimed in claim 2, is characterized in that, described voltage generator comprises first input end, the second input, output;
This first input end is connected to described first d type flip flop reset terminal;
This second input is connected with described first d type flip flop clock end by an inverter, and this second input is connected with described second d type flip flop clock end;
The output of described voltage generator is the output of described decoder.
4. a kind of constant-current control circuit as claimed in claim 2, is characterized in that, described decoder is 8421 decoders.
5. a kind of constant-current control circuit as claimed in claim 1, is characterized in that, this circuit also comprises rest-set flip-flop, buffer; This rest-set flip-flop R end is connected with described second comparator output terminal, and this rest-set flip-flop output is connected with described buffer input, and this buffer output end is connected with described switching tube (M1) grid.
6. a kind of constant-current control circuit as claimed in claim 5, is characterized in that, described voltage generator comprises first input end, the second input, output; This first input end is connected to described first comparator output terminal, and this second input is connected to described rest-set flip-flop output; The output of described voltage generator is connected to the first input end of described second comparator.
7. a voltage generator, comprises the first d type flip flop, full adder, the second d type flip flop, decoder;
Described first d type flip flop input is connected to supply voltage, and described first d type flip flop output is connected with described full adder control end;
Described full adder input is connected with described second d type flip flop output, and described full adder output is connected with described second d type flip flop input;
Described second d type flip flop output is connected to described decoder.
8. a kind of voltage generator as claimed in claim 7, is characterized in that, this voltage generator comprises first input end, the second input, output;
This first input end is connected to described first d type flip flop reset terminal;
This second input is connected with described first d type flip flop clock end by an inverter, and this second input is connected with described second d type flip flop clock end;
The output of described voltage generator is the output of described decoder.
9. a kind of voltage generator as claimed in claim 7, is characterized in that, described decoder is 8421 decoders.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1983814A (en) * | 2006-04-05 | 2007-06-20 | 华为技术有限公司 | Accumulation frequency divider |
| CN101783585A (en) * | 2009-12-25 | 2010-07-21 | 美芯晟科技（北京）有限公司 | EMI (Electro-Magnetic Interference) reduction system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1983814A (en) * | 2006-04-05 | 2007-06-20 | 华为技术有限公司 | Accumulation frequency divider |
| CN101783585A (en) * | 2009-12-25 | 2010-07-21 | 美芯晟科技（北京）有限公司 | EMI (Electro-Magnetic Interference) reduction system |
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