CN103094208A - Manufacturing method of transistor - Google Patents
Manufacturing method of transistor Download PDFInfo
- Publication number
- CN103094208A CN103094208A CN2011103384457A CN201110338445A CN103094208A CN 103094208 A CN103094208 A CN 103094208A CN 2011103384457 A CN2011103384457 A CN 2011103384457A CN 201110338445 A CN201110338445 A CN 201110338445A CN 103094208 A CN103094208 A CN 103094208A
- Authority
- CN
- China
- Prior art keywords
- layer
- barrier layer
- manufacture method
- transistorized manufacture
- metal electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
A manufacturing method of a transistor comprises: a substrate is provided, wherein the substrate is divided into a negative channel metal oxide semiconductor (NMOS) area and a positive channel metal oxide semiconductor (PMOS) area; high-K dielectric layers are formed at the substrate; a first work function metal layer, a first barrier layer and a metal electrode layer are sequentially formed on the high-K dielectric layer of the NMOS area, wherein the first barrier layer has compressive stress; and a second work function metal layer, a second barrier layer and a metal electrode layer are sequentially formed on the high-K dielectric layer of the PMOS area, wherein the second barrier layer has stretching stress. The manufacturing method of the transistor can improve electronic mobility of the transistor, so that the performance of the transistor is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to the adjustable transistorized manufacture method of a kind of work function.
Background technology
Consist of integrated circuit especially one of the main devices of very lagre scale integrated circuit (VLSIC) be metal-oxide semiconductor transistor (MOS transistor).Since the MOS transistor invention, its physical dimension is constantly being dwindled according to Moore's Law always, and its characteristic size development has at present entered deep-submicron once.Under this yardstick, the characteristic size of device is scaled becomes more and more difficult.In addition, make the field at MOS transistor device and circuit thereof, tool is challenging be traditional cmos process in the scaled process of device, the leakage problem from grid to substrate that reduces to bring due to polysilicon or silicon dioxide gate dielectric layer height.
For solving above-mentioned electric leakage problem, in MOS transistor technique, adopt the high K dielectric layer to replace traditional silica dioxide medium layer at present, and use metal as gate electrode, both coordinate the grid structure that consists of metal-oxide-semiconductor.In such grid structure, adopt the less high K dielectric layer of thickness just can reach the effect that reduces leakage current.A kind of structure with MOS transistor of metal gate is disclosed in publication number is the U.S. Patent application of US 2011210402A1.
With reference to figure 1, show the schematic diagram of prior art transistor one embodiment.
Described transistor comprises: substrate, be formed with isolation structure 13 in described substrate, described isolation structure 13 is used for substrate is divided into nmos area territory 11 and PMOS zone 12, be formed with successively intermediate layer 17, high K dielectric layer 14, the first workfunction layers 151, metal electrode layer 18 on described nmos area territory 11, form the grid structure of NMOS; Be formed with successively intermediate layer 17, high K dielectric layer 14, the second workfunction layers 152, metal electrode layer 18 on described PMOS zone 12, consist of the grid structure of PMOS.Described the first workfunction layers 151 is different with the material of the second workfunction layers 152, can provide different metal work function to NMOS, PMOS respectively.
In prior art, apply compression stress (compressive stress) on the grid structure of NMOS, and apply tensile stress (tensile stress) on the grid structure of PMOS, can increase the electron mobility of NMOS, PMOS, thereby improve the performance of metal-oxide-semiconductor.
How to improve transistorized electron mobility shown in Figure 1, improve transistorized performance and become those skilled in the art's problem demanding prompt solution.
Summary of the invention
The technical problem that the present invention solves is to provide a kind of transistorized manufacture method, improves transistorized electron mobility.
In order to address the above problem, the invention provides a kind of transistorized manufacture method, comprising: substrate is provided, and described substrate is divided into the nmos area territory and PMOS is regional; Form successively high K dielectric layer, the first workfunction layers, the first barrier layer, metal electrode layer on described nmos area territory, described the first barrier layer has compression stress; Form successively high K dielectric layer, the second workfunction layers, the second barrier layer, metal electrode layer on described PMOS zone, described the second barrier layer has tensile stress.
Alternatively, described the first barrier layer is identical with the material on the second barrier layer.
Alternatively, the material on described the first barrier layer and the second barrier layer is one or more in tantalum nitride or titanium nitride.
Alternatively, the step on formation the first barrier layer comprises: using plasma deposits.
Alternatively, form the first barrier layer and comprise that using plasma strengthens chemical vapour deposition (CVD) or physical vapour deposition (PVD).
Alternatively, the step on formation the second barrier layer comprises: adopt heat deposition to form described the second barrier layer.
Alternatively, form the second barrier layer and comprise employing ald or metallo-organic compound chemical vapour deposition (CVD).
Alternatively, the material of described the first workfunction layers, the second workfunction layers is one or more in tantalum nitride, titanium-aluminium alloy, tungsten nitride.
Alternatively, form described the first workfunction layers or the second workfunction layers by Atomic layer deposition method or physical gas-phase deposite method.
Alternatively, after forming the first barrier layer, before forming metal electrode layer, form metal infiltrating layer on the first barrier layer, be used for promoting the material of metal electrode layer to the diffusion on the first barrier layer.
Alternatively, after forming the second barrier layer, before forming metal electrode layer, form metal infiltrating layer on the second barrier layer, be used for promoting the material of metal electrode layer to the diffusion on the second barrier layer.
Alternatively, the material of described metal electrode layer is aluminium, and the material of described metal infiltrating layer is titanium or titanium-aluminium alloy.
Alternatively, the method by physical vapour deposition (PVD) forms described metal infiltrating layer.
Alternatively, the material of described metal electrode layer is aluminium.
Alternatively, the method by chemical vapour deposition (CVD) or physical vapour deposition (PVD) forms described metal electrode layer.
Alternatively, the work function of described the first workfunction layers is in the scope of 3.9eV～4.2eV.
Alternatively, the work function of described the second workfunction layers is in the scope of 4.9eV～5.2eV.
Compared with prior art, the present invention has the following advantages: the first barrier layer on described nmos area territory has compression stress, the second barrier layer on described PMOS zone has tensile stress, can improve transistorized electron mobility, and then improves transistorized performance.
Description of drawings
Fig. 1 is the schematic diagram of prior art transistor one embodiment;
Fig. 2 is the schematic flow sheet of transistorized manufacture method one execution mode of the present invention;
Fig. 3 to Figure 11 is the transistorized side schematic view that transistorized manufacture method one embodiment of the present invention forms.
Embodiment
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can be in the situation that do similar popularization without prejudice to intension of the present invention, so the present invention is not subjected to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, and when the embodiment of the present invention was described in detail in detail, for ease of explanation, described schematic diagram was example, and it should not limit the scope of protection of the invention at this.
In order to solve the problem of prior art, the invention provides a kind of transistorized manufacture method, with reference to figure 2, show the schematic flow sheet of transistor fabrication process one execution mode of the present invention, described manufacture method roughly comprises the following steps:
Step S1 provides substrate, and described substrate is divided into the nmos area territory and PMOS is regional;
Step S2 forms the high K dielectric layer on substrate;
Step S3 forms the first workfunction layers, the first barrier layer successively on the high K dielectric layer in described nmos area territory, described the first barrier layer has compression stress;
Step S4 forms metal infiltrating layer, metal electrode layer successively on described the first barrier layer;
Step S5 forms the second workfunction layers, the second barrier layer successively on the high K dielectric layer in described PMOS zone, described the second barrier layer has tensile stress;
Step S6 forms metal infiltrating layer, metal electrode layer successively on described the second barrier layer.
Below in conjunction with the drawings and specific embodiments, technical scheme of the present invention is described further.
To Figure 11, show the transistorized side structure schematic diagram that transistorized manufacture method one embodiment of the present invention forms with reference to figure 3.
As shown in Figure 3, execution in step S1 provides substrate, and described substrate can be silicon, germanium or silicon-on-insulator (Silicon-On-Insulator, SOI).
As shown in Figure 4, execution in step S2 forms high K dielectric layer 104 on substrate, and described high K dielectric layer 104 covers described nmos area territory 101, PMOS zone 102 and isolation structure 103.
The material of described high K dielectric layer 104 comprises hafnium oxide or nitrogen hafnium silicon oxide, can pass through ald (Atom Layer Deposition, ALD), chemical vapour deposition (CVD) (Chemical Vapor Deposition, CVD) or physical vapour deposition (PVD) (Physical Vapor Deposition, PVD) form described high K dielectric layer 104.
In the present embodiment, owing to having adopted the dielectric layer of high K dielectric layer 104 as grid structure, described high K dielectric layer 104 can adopt less thickness can reach the required dielectric constant of grid structure of metal-oxide-semiconductor.Easily increase the difficulty that follow-up oxygen or nitrogen diffuse to substrate surface if the thickness of high K dielectric layer 104 is excessive.Therefore, preferably, the thickness of described high K dielectric layer 104 exists
Scope in, described high K dielectric layer 104 has reduced the thickness of the grid structure of multiple-level stack, has improved the integration of semiconductor device.
Deposit spathic silicon layer 105 on high K dielectric layer 104, graphical described polysilicon layer 105, high K dielectric layer 104 afterwards, remove polycrystalline silicon material and the high K dielectric material of described isolation structure 103 tops, formation be positioned at nmos area territory 101 the first sandwich construction, be positioned at the second sandwich construction on PMOS zone 102, described the first sandwich construction and described the second sandwich construction are isolated.
As shown in Figure 5, form respectively the side wall 106 that surrounds described the first sandwich construction and the second sandwich construction, the material of described side wall can be silica or silicon nitride.
Form interlayer dielectric layer 107 on the substrate that the first sandwich construction, the second sandwich construction, side wall 106 expose, the material of interlayer dielectric layer described in the present embodiment 107 is silica.
As shown in Figure 6, polysilicon layer 105 in 101 top the first sandwich constructions of removal nmos area territory, particularly, can remove described polysilicon layer 105 by etching method, after removing polysilicon layer 105, above nmos area territory 101, form in the polysilicon layer 105 former space that occupies the first groove 114 that is surrounded by side wall 106, high K dielectric layer 104.
As shown in Figure 7, execution in step S3, deposition the first workfunction metal material on the high K dielectric layer 104 of described the first groove 114 bottoms forms the first workfunction layers 110 that guarantor's type covers described the first groove 114.
Described the first workfunction layers 110 is positioned at the top in nmos area territory 101, workfunction layers as follow-up formation NMOS, be applicable to the corresponding work function of workfunction layers of NMOS pipe in the scope of 3.9eV～4.2eV, in the present embodiment, the material of described the first workfunction layers 110 is one or more in titanium nitride, titanium-aluminium alloy or tungsten nitride.
Particularly, can form described the first workfunction layers 110 by Atomic layer deposition method or physical gas-phase deposite method.
Continuation is with reference to figure 7, form the first barrier layer 111 that guarantor's type covers on the first workfunction layers 110, described the first barrier layer 111 has compression stress, when being used for preventing the metal electrode layer diffusion of follow-up formation, also have the compression stress that makes the grid structure compression, and then improve the electron mobility of NMOS.
In the present embodiment, the mode that using plasma deposits forms described the first barrier layer 111, and the first barrier layer 111 that forms by plasma mode has certain compression stress.
Particularly, the material on described the first barrier layer 111 is one or more in tantalum nitride (TaN), titanium nitride (TiN), can adopt such as plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD), the method for using plasma in technical process such as physical vapour deposition (PVD) (Physical Vapor Deposition, PVD) forms described tantalum nitride or titanium nitride.
As shown in Figure 8, execution in step S4 forms the metal infiltrating layer 112 that guarantor's type covers on the first barrier layer 111.Described metal infiltrating layer 112 is used for by infiltrating effect, makes the metal electrode layer 113 of follow-up formation to the first barrier layer 111 diffusions.
In the present embodiment, the first workfunction layers 110, the first barrier layer 111, metal infiltrating layer 112 guarantor's types are covered in the first groove 114, form the groove that is surrounded by metal infiltrating layer 112, fill metal material formation metal electrode layer 113 in described groove.
The first barrier layer 111 is bad with the adhesiveness of metal material, easily form the space in groove when filling metal material, by form metal infiltrating layer 112 on the first barrier layer 111, can promote metal material to the diffusion on the first barrier layer 111 by infiltrating effect, thereby prevent from forming the space in metal electrode layer 113.
In the present embodiment, the material of described metal electrode layer 113 is aluminium, can form by chemical vapour deposition (CVD) (Chemical Vapor Deposition, CVD) or physical vapour deposition (PVD) the metal electrode layer 113 of described aluminum.
The material of metal electrode layer 113 is aluminium, and correspondingly, the material of described metal infiltrating layer 112 is titanium or titanium-aluminium alloy, can form by the mode of physical vapour deposition (PVD) described titanium or titanium-aluminium alloy.
In actual process, after forming metal infiltrating layer 112, filling aluminum material in the groove that method by chemical vapour deposition (CVD) or physical vapour deposition (PVD) surrounds to described metal infiltrating layer 112, also remove the first unnecessary workfunction layers 110, the first barrier layer 111, metal infiltrating layer 112 and metal electrode layer 113 by chemico-mechanical polishing afterwards, thereby form the grid structure of NMOS.
Need to prove, after the grid structure of NMOS is completed in manufacturing, also be included on the NMOS grid structure and cover photoresist, be used for the process at the grid structure of follow-up formation PMOS, the grid structure of the established NMOS of protection.
As shown in Figure 9, after covering photoresist on the NMOS grid structure, remove the polysilicon layer 105 in regional 102 top the second sandwich constructions of PMOS, particularly, can remove described polysilicon layer 105 by etching method, after removing polysilicon layer 105, above PMOS zone 102, form in the polysilicon layer 105 former space that occupies the second groove 118 that is surrounded by side wall 106, high K dielectric layer 104.
As shown in figure 10, execution in step S5, deposition the second workfunction metal material on the high K dielectric layer 104 of described the second groove 118 bottoms forms the second workfunction layers 114 that guarantor's type covers described the second groove 118.
described the second workfunction layers 114 is positioned at the top in PMOS zone 102, workfunction layers as follow-up formation PMOS, be applicable to the corresponding work function of workfunction layers of PMOS pipe in the scope of 4.9eV～5.2eV, in the present embodiment, the material of described the second workfunction layers 114 is titanium nitride, one or more in titanium-aluminium alloy or tungsten nitride, the difference of described the second workfunction layers 114 and the first workfunction layers 110 materials is, in the second workfunction layers 114 materials, the element of nonmetalloid and metallic element is than the element ratio greater than nonmetalloid and metallic element in the first workfunction layers 110 materials.
Particularly, can form described the second workfunction layers 114 by Atomic layer deposition method or physical gas-phase deposite method.
Continuation forms with reference to Figure 10 the second barrier layer 115 that guarantor's type covers on the second workfunction layers 114, described the second barrier layer 115 has tensile stress.Described the second barrier layer 115 also has the tensile stress that grid structure is stretched, and then improves the electron mobility of PMOS to be formed when being used for preventing the metal electrode layer diffusion of follow-up formation.
In the present embodiment, the material on described the second barrier layer 115 is identical with the material on the first barrier layer 111, is one or more in tantalum nitride (TaN), titanium nitride (TiN).But the present invention is not restricted to this.
In the present embodiment, adopt heat deposition to form described the second barrier layer 115, the second barrier layer 115 that forms by the heat deposition mode has certain tensile stress.
Particularly, the mode of described heat deposition comprises ald (Atom Layer Deposition, ALD) or metallo-organic compound chemical vapour deposition (CVD) (Metal-Organic Chemical Vapor Deposition, MOCVD).
As shown in figure 11, execution in step S6 forms the metal infiltrating layer 116 that guarantor's type covers on the second barrier layer 115.Described metal infiltrating layer 116 is used for making the metal electrode layer 117 of follow-up formation to the second barrier layer 115 diffusions by infiltrating effect.
In the present embodiment, the second workfunction layers 114, the second barrier layer 115, metal infiltrating layer 116 guarantor's types are covered in the second groove 118, form the groove that is surrounded by metal infiltrating layer 116, fill metal material formation metal electrode layer 117 in described groove.
The second barrier layer 115 is bad with the adhesiveness of metal material, easily form the space in groove when filling metal material, by form metal infiltrating layer 116 on the second barrier layer 115, can promote metal material to the diffusion on the second barrier layer 115 by infiltrating effect, thereby prevent from forming the space in metal electrode layer 117.
In the present embodiment, the material of described metal electrode layer 117 is aluminium, can form by chemical vapour deposition (CVD) (Chemical Vapor Deposition, CVD) or physical vapour deposition (PVD) the metal electrode layer 117 of described aluminum.
The material of metal electrode layer 117 is aluminium, and correspondingly, the material of described metal infiltrating layer 116 is titanium or titanium-aluminium alloy, can form by the mode of physical vapour deposition (PVD) described titanium or titanium-aluminium alloy.
In actual process, after forming metal infiltrating layer 116, filling aluminum material in the groove that method by chemical vapour deposition (CVD) or physical vapour deposition (PVD) surrounds to described metal infiltrating layer 116, also remove the second unnecessary workfunction layers 114, the second barrier layer 115, metal infiltrating layer 116 and metal electrode layer 117 by chemico-mechanical polishing afterwards, thereby form the grid structure of PMOS.
Also need to prove, in the above-described embodiments, before forming PMOS, first form NMOS on substrate, but the present invention is not restricted to this, can also be to form NMOS after forming PMOS again, and those skilled in the art can correspondingly revise, replace and be out of shape.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (17)
1. a transistorized manufacture method, is characterized in that, comprising:
Substrate is provided, and described substrate is divided into the nmos area territory and PMOS is regional;
Form the high K dielectric layer on substrate;
Form successively the first workfunction layers, the first barrier layer, metal electrode layer on the high K dielectric layer in described nmos area territory, described the first barrier layer has compression stress;
Form successively the second workfunction layers, the second barrier layer, metal electrode layer on the high K dielectric layer in described PMOS zone, described the second barrier layer has tensile stress.
2. transistorized manufacture method as claimed in claim 1, is characterized in that, described the first barrier layer is identical with the material on the second barrier layer.
3. transistorized manufacture method as claimed in claim 2, is characterized in that, the material on described the first barrier layer and the second barrier layer is one or more in tantalum nitride or titanium nitride.
4. transistorized manufacture method as claimed in claim 1, is characterized in that, the step that forms the first barrier layer comprises: using plasma deposits.
5. transistorized manufacture method as claimed in claim 4, is characterized in that, forms the first barrier layer and comprise that using plasma strengthens chemical vapour deposition (CVD) or physical vapour deposition (PVD).
6. transistorized manufacture method as claimed in claim 1, is characterized in that, the step that forms the second barrier layer comprises: adopt heat deposition to form described the second barrier layer.
7. transistorized manufacture method as claimed in claim 6, is characterized in that, forms the second barrier layer and comprise employing ald or metallo-organic compound chemical vapour deposition (CVD).
8. transistorized manufacture method as claimed in claim 1, is characterized in that, the material of described the first workfunction layers, the second workfunction layers is one or more in tantalum nitride, titanium-aluminium alloy, tungsten nitride.
9. transistorized manufacture method as claimed in claim 8, is characterized in that, forms described the first workfunction layers or the second workfunction layers by Atomic layer deposition method or physical gas-phase deposite method.
10. transistorized manufacture method as claimed in claim 1, it is characterized in that, after forming the first barrier layer, before forming metal electrode layer, form metal infiltrating layer on the first barrier layer, be used for promoting the material of metal electrode layer to the diffusion on the first barrier layer.
11. transistorized manufacture method as claimed in claim 1, it is characterized in that, after forming the second barrier layer, before forming metal electrode layer, form metal infiltrating layer on the second barrier layer, be used for promoting the material of metal electrode layer to the diffusion on the second barrier layer.
12. transistorized manufacture method as described in claim 10 or 11 is characterized in that the material of described metal electrode layer is aluminium, the material of described metal infiltrating layer is titanium or titanium-aluminium alloy.
13. transistorized manufacture method as claimed in claim 12 is characterized in that, the method by physical vapour deposition (PVD) forms described metal infiltrating layer.
14. transistorized manufacture method as claimed in claim 1 is characterized in that, the material of described metal electrode layer is aluminium.
15. transistorized manufacture method as claimed in claim 14 is characterized in that, the method by chemical vapour deposition (CVD) or physical vapour deposition (PVD) forms described metal electrode layer.
16. transistorized manufacture method as claimed in claim 1 is characterized in that the work function of described the first workfunction layers is in the scope of 3.9eV～4.2eV.
17. transistorized manufacture method as claimed in claim 1 is characterized in that the work function of described the second workfunction layers is in the scope of 4.9eV～5.2eV.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110338445.7A CN103094208B (en) | 2011-10-31 | 2011-10-31 | Manufacturing method of transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110338445.7A CN103094208B (en) | 2011-10-31 | 2011-10-31 | Manufacturing method of transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103094208A true CN103094208A (en) | 2013-05-08 |
| CN103094208B CN103094208B (en) | 2015-04-01 |
Family
ID=48206617
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110338445.7A Active CN103094208B (en) | 2011-10-31 | 2011-10-31 | Manufacturing method of transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103094208B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104752425A (en) * | 2013-12-25 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof |
| CN104752447A (en) * | 2013-12-27 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN104810324A (en) * | 2014-01-24 | 2015-07-29 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN111128869A (en) * | 2019-12-26 | 2020-05-08 | 华虹半导体(无锡)有限公司 | Preparation method for optimizing hot aluminum pore-filling capacity |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1790715A (en) * | 2004-12-15 | 2006-06-21 | 国际商业机器公司 | Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification |
| CN101677087A (en) * | 2008-09-12 | 2010-03-24 | 台湾积体电路制造股份有限公司 | Method of fabricating a semiconductor device |
| CN102054769A (en) * | 2009-10-29 | 2011-05-11 | 中芯国际集成电路制造(上海)有限公司 | Forming method of complementary metal oxide semiconductor (CMOS) structure |
| CN102214579A (en) * | 2010-04-08 | 2011-10-12 | 台湾积体电路制造股份有限公司 | Method of fabricating semiconductor device and semiconductor element |
-
2011
- 2011-10-31 CN CN201110338445.7A patent/CN103094208B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1790715A (en) * | 2004-12-15 | 2006-06-21 | 国际商业机器公司 | Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification |
| CN101677087A (en) * | 2008-09-12 | 2010-03-24 | 台湾积体电路制造股份有限公司 | Method of fabricating a semiconductor device |
| CN102054769A (en) * | 2009-10-29 | 2011-05-11 | 中芯国际集成电路制造(上海)有限公司 | Forming method of complementary metal oxide semiconductor (CMOS) structure |
| CN102214579A (en) * | 2010-04-08 | 2011-10-12 | 台湾积体电路制造股份有限公司 | Method of fabricating semiconductor device and semiconductor element |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104752425A (en) * | 2013-12-25 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof |
| CN104752447A (en) * | 2013-12-27 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN104752447B (en) * | 2013-12-27 | 2017-12-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof |
| CN104810324A (en) * | 2014-01-24 | 2015-07-29 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN104810324B (en) * | 2014-01-24 | 2017-12-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of method for making semiconductor devices |
| CN111128869A (en) * | 2019-12-26 | 2020-05-08 | 华虹半导体(无锡)有限公司 | Preparation method for optimizing hot aluminum pore-filling capacity |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103094208B (en) | 2015-04-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104081531B (en) | For the Atomic layer deposition method of metal gate electrode | |
| TWI759277B (en) | Semiconductor devices, finfet devices and methods of forming the same | |
| US8410555B2 (en) | CMOSFET device with controlled threshold voltage and method of fabricating the same | |
| US10692779B2 (en) | Method and structure for CMOS metal gate stack | |
| CN104701310A (en) | Semiconductor device with profiled work-function metal gate electrode and method of making | |
| US11043591B2 (en) | FeFET transistor | |
| CN101661904A (en) | Semiconductor device and method for fabricating same | |
| TW201533846A (en) | Semiconductor device and fabricating method thereof | |
| TW201543552A (en) | Semiconductor device with gate stacks and method of manufacturing the same | |
| TW201010009A (en) | Method for fabricating a semiconductor device and semiconductor device therefrom | |
| CN106158860A (en) | Semiconductor structure and manufacture method thereof | |
| US10276447B2 (en) | Semiconductor structures and methods of forming the same | |
| TWI462273B (en) | Integrated circuit | |
| CN102437032B (en) | Manufacture method of metal gates in gate-post process | |
| CN106601605A (en) | Grid stack structure, NMOS device, semiconductor device and manufacturing method thereof | |
| CN103681337A (en) | Fin type field effect transistor and forming method thereof | |
| US8674434B2 (en) | Impact ionization devices | |
| CN103094114B (en) | The manufacture method of transistor | |
| CN107195550A (en) | A kind of semiconductor device structure and preparation method thereof | |
| CN103094208B (en) | Manufacturing method of transistor | |
| CN107818946A (en) | Cmos circuit and its manufacture method with the different transistor of threshold voltage | |
| CN105845573A (en) | FinFET device and manufacturing method thereof, and electronic apparatus | |
| CN105097693B (en) | A kind of semiconductor devices and its manufacturing method, electronic device | |
| CN103137456A (en) | Manufacturing method for P-channel metal oxide semiconductor (PMOS) transistor metal grid | |
| US6939770B1 (en) | Method of fabricating semiconductor device having triple LDD structure and lower gate resistance formed with a single implant process |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |