CN103094116A - Technique method of manufacturing groove metal oxide semiconductor (MOS) - Google Patents
Technique method of manufacturing groove metal oxide semiconductor (MOS) Download PDFInfo
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- CN103094116A CN103094116A CN2011103401452A CN201110340145A CN103094116A CN 103094116 A CN103094116 A CN 103094116A CN 2011103401452 A CN2011103401452 A CN 2011103401452A CN 201110340145 A CN201110340145 A CN 201110340145A CN 103094116 A CN103094116 A CN 103094116A
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- silicon dioxide
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- epitaxial loayer
- epitaxial layer
- mos
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Abstract
The invention discloses a technique method of manufacturing a groove metal oxide semiconductor (MOS). The technique method of manufacturing the groove MOS comprises the following steps. The first step is that an epitaxial layer grows on a heavily-doped silicon substrate, and a first lightly-doped epitaxial layer is formed; the second step is that silicon dioxide grows on the first lightly-doped epitaxial layer; the third step is that a photoresist pattern is formed on the silicon dioxide; the fourth step is that the silicon dioxide which is unblocked by photoresist is etched cleanly, so that the first lightly-doped epitaxial layer except the photoresist is exposed, and then the photoresist is eliminated; the fifth step is that a second epitaxial layer grows selectively, a second lightly-doped epitaxial layer grows on the surface of the exposed first lightly-doped epitaxial layer, and yet the silicon dioxide does not grow; the sixth step is the silicon dioxide is etched away through a wet process, and a groove is formed. According to the technique method of manufacturing the groove MOS, selectively epitaxial growth is adopted to form the groove, the position of an epitaxial layer of a double-layer epitaxial groove MOS relative to the groove can be controlled accurately, and thereby the breakdown voltage and the on-state resistance of a device are enabled to be optimized by respectively controlling the dosage concentration of the two layers of epitaxy.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor device, be specifically related to a kind of process of making groove MOS.
Background technology
Existing groove MOS (metal-oxide semiconductor (MOS)) technique forms groove by etching, generally only has one deck extension in heavy doping.When needs have two-layer outer time-delay, existing technical matters is controlled accurate not to the relative position of extension and groove, therefore makes the Comparision difficulty of optimizing epi dopant and device performance.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of process of making groove MOS, and it can accurately control the position of the relative groove of epitaxial loayer of double-deck extension groove MOS.
For solving the problems of the technologies described above, the technical solution that the present invention makes the process of groove MOS is to comprise the following steps:
The first step at heavily doped silicon Grown epitaxial loayer, forms the first light dope epitaxial loayer;
Second step, the silicon dioxide of growing on the first light dope epitaxial loayer;
The thickness of formed silicon dioxide is equal to, or greater than the follow-up gash depth that will form.
The 3rd step, adopt photoetching process, gluing, photoetching on silicon dioxide form photoetching offset plate figure;
The 4th step, etching, the silicon dioxide etching of not blocked by photoresist is clean, expose the first light dope epitaxial loayer beyond photoresist; Then remove photoresist;
The 5th step, selective growth the second epitaxial loayer; At the superficial growth second light dope epitaxial loayer of the first light dope epitaxial loayer that exposes, and do not grow on silicon dioxide;
The gash depth of the thickness of formed the second light dope epitaxial loayer for forming.
The 6th step, fall silicon dioxide with wet etching, form groove.
The technique effect that the present invention can reach is:
The present invention adopts selective epitaxial growth to form groove, can accurately control the position of the relative groove of epitaxial loayer of double-deck extension groove MOS, thereby can by controlling respectively the doping content of two-layer extension, come puncture voltage and the on state resistance of optimised devices.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 to Fig. 5 makes the corresponding structural representation of each step of the process of groove MOS with the present invention;
Fig. 6 is the schematic cross-section that adopts the made groove MOS device of the present invention.
Embodiment
The present invention makes the process of groove MOS, comprises the following steps:
The first step as shown in Figure 1, at heavily doped silicon Grown epitaxial loayer, forms the first light dope epitaxial loayer; The heavy doping bulk concentration is 10
18/ cm
3Above;
Second step, as shown in Figure 1, the silicon dioxide of growing on the first light dope epitaxial loayer, its thickness is equal to, or greater than the follow-up gash depth that will form;
The 3rd step, as shown in Figure 2, adopt photoetching process, gluing, photoetching on silicon dioxide form photoetching offset plate figure;
The 4th step, as shown in Figure 3, etching, the silicon dioxide etching of not blocked by photoresist is clean, expose the first light dope epitaxial loayer beyond photoresist; Then remove photoresist;
The 5th step, as shown in Figure 4, selective growth the second epitaxial loayer; At the superficial growth second light dope epitaxial loayer of the first light dope epitaxial loayer that exposes, and do not grow on silicon dioxide;
The thickness of the second light dope epitaxial loayer is to want the gash depth that forms;
The 6th step, as shown in Figure 5, adopt existing wet etching technique, fall whole silicon dioxide with wet etching, namely form groove.
Adopt the present invention, can make groove MOS device as shown in Figure 6.
Claims (3)
1. a process of making groove MOS, is characterized in that, comprises the following steps:
The first step at heavily doped silicon Grown epitaxial loayer, forms the first light dope epitaxial loayer;
Second step, the silicon dioxide of growing on the first light dope epitaxial loayer;
The 3rd step, adopt photoetching process, gluing, photoetching on silicon dioxide form photoetching offset plate figure;
The 4th step, etching, the silicon dioxide etching of not blocked by photoresist is clean, expose the first light dope epitaxial loayer beyond photoresist; Then remove photoresist;
The 5th step, selective growth the second epitaxial loayer; Superficial growth the second light dope epitaxial loayer at the first light dope epitaxial loayer that exposes;
The 6th step, fall silicon dioxide with wet etching, form groove.
2. the process of making groove MOS according to claim 1, is characterized in that, the thickness of the formed silicon dioxide of described second step is equal to, or greater than the follow-up gash depth that will form.
3. the process of making groove MOS according to claim 1 and 2, is characterized in that, the gash depth of thickness for forming of described the 5th formed the second light dope epitaxial loayer of step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103401452A CN103094116A (en) | 2011-11-01 | 2011-11-01 | Technique method of manufacturing groove metal oxide semiconductor (MOS) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103401452A CN103094116A (en) | 2011-11-01 | 2011-11-01 | Technique method of manufacturing groove metal oxide semiconductor (MOS) |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103094116A true CN103094116A (en) | 2013-05-08 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2011103401452A Pending CN103094116A (en) | 2011-11-01 | 2011-11-01 | Technique method of manufacturing groove metal oxide semiconductor (MOS) |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105225959A (en) * | 2014-07-01 | 2016-01-06 | 北大方正集团有限公司 | The manufacture method of slot type power device and slot type power device |
Citations (6)
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|---|---|---|---|---|
| US20010022379A1 (en) * | 2000-03-14 | 2001-09-20 | Intersil Corporation | Power trench transistor device source region formation using silicon spacer |
| US6373098B1 (en) * | 1999-05-25 | 2002-04-16 | Fairchild Semiconductor Corporation | Trench-gated device having trench walls formed by selective epitaxial growth and process for forming device |
| JP2003209252A (en) * | 2002-01-17 | 2003-07-25 | Oki Electric Ind Co Ltd | High voltage vertical mos transistor and its manufacturing method |
| CN101512777A (en) * | 2006-08-31 | 2009-08-19 | 飞兆半导体公司 | Power trench MOSFET having SiGe/Si channel structure |
| CN102027583A (en) * | 2008-04-14 | 2011-04-20 | 半南实验室公司 | Methods of making lateral junction field effect transistors using selective epitaxial growth |
| CN102097354A (en) * | 2009-12-15 | 2011-06-15 | 中芯国际集成电路制造(上海)有限公司 | Method for forming pressure resistant region of power device |
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2011
- 2011-11-01 CN CN2011103401452A patent/CN103094116A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6373098B1 (en) * | 1999-05-25 | 2002-04-16 | Fairchild Semiconductor Corporation | Trench-gated device having trench walls formed by selective epitaxial growth and process for forming device |
| US20010022379A1 (en) * | 2000-03-14 | 2001-09-20 | Intersil Corporation | Power trench transistor device source region formation using silicon spacer |
| JP2003209252A (en) * | 2002-01-17 | 2003-07-25 | Oki Electric Ind Co Ltd | High voltage vertical mos transistor and its manufacturing method |
| CN101512777A (en) * | 2006-08-31 | 2009-08-19 | 飞兆半导体公司 | Power trench MOSFET having SiGe/Si channel structure |
| CN102027583A (en) * | 2008-04-14 | 2011-04-20 | 半南实验室公司 | Methods of making lateral junction field effect transistors using selective epitaxial growth |
| CN102097354A (en) * | 2009-12-15 | 2011-06-15 | 中芯国际集成电路制造(上海)有限公司 | Method for forming pressure resistant region of power device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105225959A (en) * | 2014-07-01 | 2016-01-06 | 北大方正集团有限公司 | The manufacture method of slot type power device and slot type power device |
| CN105225959B (en) * | 2014-07-01 | 2019-06-11 | 北大方正集团有限公司 | The manufacturing method and slot type power device of slot type power device |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140107 |
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Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
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Effective date of registration: 20140107 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
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Application publication date: 20130508 |