CN103076703B - A kind of display panels and manufacture method thereof - Google Patents
A kind of display panels and manufacture method thereof Download PDFInfo
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- CN103076703B CN103076703B CN201210586237.3A CN201210586237A CN103076703B CN 103076703 B CN103076703 B CN 103076703B CN 201210586237 A CN201210586237 A CN 201210586237A CN 103076703 B CN103076703 B CN 103076703B
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Abstract
The invention provides a kind of display panels and manufacture method thereof, comprising: the IGZO layer on underlay substrate, the source on IGZO layer, drain electrode and pixel electrode, gate insulator on source electrode and drain electrode and between source electrode and drain electrode, be positioned at grid on gate insulator and the sweep trace be connected with grid, the Al be positioned on grid
2o
3insulation course, be positioned at Al
2o
3dielectric film on insulation course and be positioned at the data line of most top layer.The present invention adopts the IGZO-TFT of self-aligned top gate structure, and in the process forming IGZO-TFT, by laying Al rete, through the pyroreaction in oxygen atmosphere, part IGZO layer being reacted and forming source electrode and drain electrode, and Al rete being reacted into Al simultaneously
2o
3insulation course, makes the stray capacitance Cgd of liquid crystal panel only have about 1/5 of conventional panels on the one hand, reduces kick-back voltage, reduces memory capacitance with this, improves aperture opening ratio; On the other hand, the light shield number of TFT panel is reduced to 4, has saved cost.
Description
Technical field
The present invention relates to a kind of manufacture method of liquid crystal panel.
Background technology
Energy-conservation to liquid crystal panel, become more meticulous, maximize and the low cost Shi Ge company direction of pursuing always, and the TFT with excellent switching characteristic is exactly a key point of dealing with problems.
LTPS-TFTLCD(LowTemperaturePoly-silicon, low-temperature polysilicon film transistor liquid crystal display) have the advantages such as high resolving power, reaction velocity are fast, high brightness, high aperture become realize energy-conservation, become more meticulous, the hot topic that maximizes selects, but p-SiTFT exists two problems at present, one is that the off-state current (i.e. leakage current) of TFT is larger; Two is that the preparation of high mobility p-Si material at low temperature large area is more difficult, technique exists certain difficulty.
IGZO(indiumgalliumzincoxide, indium gallium zinc oxide) be a kind of amorphous oxides containing indium, gallium and zinc, carrier mobility is 20 ~ 30 times of amorphous silicon, greatly can improve the charge-discharge velocity of TFT to pixel electrode, improve the response speed of pixel, realize refresh rate faster, respond the line scanning rate also substantially increasing pixel faster simultaneously, make ultrahigh resolution become possibility in TFT-LCD.In addition, reduce due to number of transistors and improve the transmittance of each pixel, IGZO display has higher efficiency level, and efficiency is higher.
But current IGZO-TFT technology still adopts traditional TFT manufacturing process, such as coplanar type TFT or bottom grating structure TFT.In order to protect IGZO, make the impact that can not cause in follow-up etching IGZO characteristic, sometimes also need to form one deck restraining barrier to protect IGZO layer, so general 5 become main flow to 7mask, but just cause the rising of cost like this.And the technology such as existing coplanar type TFT or bottom grating structure TFT due to stray capacitance Cgd larger.
Figure 1 shows that coplanar type TFT, its structure is is all underlay substrate 21, be positioned at corresponding grid 22 on underlay substrate 21 and cover the gate insulator 23 of corresponding grid 22, this coplanar type TFT needs to carry out 3 photoetching process process, form grid 22, source electrode 24 and drain electrode 25, oxide semiconductor layer 26 pattern of totally three layers respectively, general consideration is in the photo-etching technological process forming source-drain electrode, what need grid 22 and source-drain electrode 24,25 crossover region width d to do is slightly bigger, ensure crossover region area with this, ensure TFT characteristic.But the OFF state kick-back voltage that the memory capacitance that just needs Cgd comparatively greatly to be formed causes to balance Cgd, reduces Cgd and becomes the one of dealing with problems most effective method.
Summary of the invention
The object of the present invention is to provide a kind of reduction kick-back voltage, reduce memory capacitance, improve display panels and the manufacture method thereof of aperture opening ratio.
The invention provides a kind of display panels, comprising: the IGZO layer on underlay substrate, the source on IGZO layer, drain electrode and pixel electrode, gate insulator on source electrode and drain electrode and between source electrode and drain electrode, be positioned at grid on gate insulator and the sweep trace be connected with grid, the Al be positioned on grid
2o
3insulation course, be positioned at Al
2o
3dielectric film on insulation course and be positioned at the data line of most top layer.
The present invention provides again a kind of manufacture method of display panels, comprises the steps: on underlay substrate, form IGZO layer; On the basis forming above-mentioned pattern, first at IGZO layer cover gate insulation course, then form grid on gate insulator, then formed the lamination pattern of gate insulator and grid by photoetching process; On the basis forming above-mentioned pattern, cover one deck Al rete, then high annealing in oxygen atmosphere, form Al
2o
3insulation course, source electrode, drain electrode and pixel electrode; On the basis forming said structure, cover insulating film layer, then offer contact hole; On the basis forming above-mentioned pattern, form data line.
The present invention adopts the IGZO-TFT of self-aligned top gate structure, and in the process forming IGZO-TFT, by laying Al rete, through the pyroreaction in oxygen atmosphere, part IGZO layer being reacted and forming source electrode and drain electrode, and Al rete being reacted into Al simultaneously
2o
3insulation course, makes the stray capacitance Cgd of liquid crystal panel only have about 1/5 of conventional panels on the one hand, reduces kick-back voltage, reduces memory capacitance with this, improves aperture opening ratio; On the other hand, the light shield number of TFT panel is reduced to 4, has saved cost.
Accompanying drawing explanation
Figure 1 shows that the structural representation of the display panels of prior art;
Figure 2 shows that the structural representation of display panels of the present invention;
Fig. 2 A is depicted as the cut-open view of Fig. 2 in A-A` direction;
Figure 3 shows that the schematic diagram of one of the manufacturing step of display panels shown in Fig. 2;
Fig. 3 A is depicted as the cut-open view of Fig. 3 in A-A` direction;
Figure 4 shows that the schematic diagram of the manufacturing step two of display panels shown in Fig. 2;
Fig. 4 A is depicted as the cut-open view of Fig. 4 in A-A` direction;
Fig. 5 A is depicted as the schematic diagram of the manufacturing step three of display panels shown in Fig. 2;
Fig. 5 B is depicted as another schematic diagram of the manufacturing step three of display panels shown in Fig. 2;
Figure 6 shows that the schematic diagram of the manufacturing step four of display panels shown in Fig. 2;
Fig. 6 A is depicted as the cut-open view of Fig. 6 in A-A` direction;
Figure 7 shows that the schematic diagram of the manufacturing step five of display panels shown in Fig. 2;
Fig. 7 A is depicted as the cut-open view of Fig. 7 in A-A` direction;
Figure 8 shows that the structural representation of display panels second embodiment of the present invention;
Figure 9 shows that the structural representation of display panels of the present invention 3rd embodiment;
Figure 10 shows that the structural representation of display panels of the present invention 4th embodiment;
Figure 11 shows that the structural representation of display panels of the present invention 5th embodiment.
Embodiment
Below in conjunction with the drawings and specific embodiments, illustrate the present invention further, these embodiments should be understood only be not used in for illustration of the present invention and limit the scope of the invention, after having read the present invention, the amendment of those skilled in the art to the various equivalent form of value of the present invention has all fallen within the application's claims limited range.
The present invention discloses a kind of display panels, and this display panels is IGZO-TFT, and the present invention is the TFT of top gate structure, the application of being reacted by self-aligned top gate structure TFT and Al, reduces light shield number (4mask), improves aperture opening ratio.
As Fig. 2 and Fig. 2 A, this display panels sequentially comprises from the bottom to top: the IGZO layer 20 on underlay substrate 10, the source electrode 61 on IGZO layer 20 and drain electrode 62, gate insulator 30 on source electrode 61 and drain electrode 62 and between source electrode 61 and drain electrode 62, be positioned at grid 40 on gate insulator 30 and the sweep trace 41 be connected with grid 40, the Al be positioned on grid 40
2o
3insulation course 50, be positioned at Al
2o
3dielectric film 70 on insulation course 50 and be positioned at the data line 80 of most top layer.
The present invention, by the annealing in high temperature (temperature is 200400 DEG C) in oxygen atmosphere of Al rete, makes the Al of Al rete 50 and oxygen react and forms Al
2o
3the first half of insulation course 50, IGZO layer forms source electrode 61 and drain electrode 62.
Be below the manufacture method of liquid crystal panel of the present invention, step is as follows:
The first step: as Fig. 3 and Fig. 3 A, forms IGZO layer 20, an IGZO tunic thick by techniques such as photoetching and is 40-60nm, is preferably 50nm on underlay substrate 10.
Second step: as Fig. 4 and Fig. 4 A, on the basis forming above-mentioned pattern, first cover on IGZO layer 20 and form gate insulator 30, the sweep trace 41 forming grid 40 again and be connected with grid 40 on gate insulator 30, then the lamination pattern of gate insulator 30 and grid 40 is formed by techniques such as photoetching, owing to etching metal and insulation course simultaneously, therefore can only etch by dry lithography the lamination pattern forming gate insulator 30 and grid 40 simultaneously.
Wherein, gate insulator 30 is by SiO
2material is formed, and its thickness is 250-350nm; Grid 40 is made up of Mo/Al or Ti/Al lamination metal, and its thickness is 350-450nm.
3rd step: as Fig. 4 A, on the basis forming above-mentioned pattern, cover the Al rete 50 that a layer thickness is 4-6nm, this Al rete 50 covers on grid 50 and IGZO layer 40; Then the middle annealing of high temperature (temperature is 200-400 DEG C) one hours in oxygen bad border, forms Al
2o
3insulation course, source electrode 61 and drain electrode 62.
Al due to the oxygen atom (O) in oxygen and Al rete 50 reacts and forms Al
2o
3insulation course 50; IGZO layer 20 contacts with Al rete 50 and forms source electrode 61 and drain 62 and pixel electrode through pyroreaction, and the position stopped by grid 50 and gate insulator 30 is then channel region (not shown).
Pixel electrode connects with drain electrode 62, therefore in figure, do not mark the numbering of pixel electrode, and pixel electrode and drain electrode are formed and are planar structure simultaneously, in the present embodiment, the pixel electrode of pixel electrode and drain electrode structure and available liquid crystal display panel and drain different, drain electrode and the pixel electrode of available liquid crystal display panel are connected by contact hole, and do not formed with layer.
The present embodiment, by pixel electrode and drain electrode being formed simultaneously, can save a lithographic process steps, cost-saving.
4th step: as Fig. 6 and Fig. 6 A, on the basis forming said structure, cladding thickness is the insulating film layer 70 of 250nm-350nm, then above source electrode 61, offers contact hole 71.
Wherein, insulating film layer 70 is by SiO
2or SiNx material is made.
5th step: as Fig. 7 and Fig. 7 A, on the basis forming above-mentioned pattern, form the data line 80 be connected with contact hole 71, this data line 80 is metal by Mo, Al or Ti, and its thickness is 250-350nm.
The present invention discloses a kind of display panels of top gate structure, this display panels is IGZO-TFT, by the application that self-aligned top gate structure TFT and Al reacts, the present invention is 4 photoetching processes (form IGZO layer, form grid and gate insulator lamination pattern, form insulated hole, form data line), the present invention reduces light shield number for several times, improves aperture opening ratio.
Fig. 8 is the structural representation of the second embodiment of display panels of the present invention, with above-mentioned first embodiment unlike: while forming data line 80, also form the public electrode wire 90 parallel with data line 80.
Public electrode wire 90 has to be formed with gate line simultaneously and has identical technique effect, because public electrode wire and data line are formed simultaneously, the voltage of public electrode can be introduced via source side.Public electrode and pixel electrode form memory capacitance, balance leakage current and kick-back voltage with this.
Fig. 9 is the structural representation of the 3rd embodiment of display panels of the present invention, with above-mentioned second embodiment unlike: form sweep trace 41 at the lamination pattern forming gate insulator 30 and grid 40 simultaneously, sweep trace 41 covers the IGZO layer of a upper pixel cell, with this, public electrode wire 90 is shared with the sweep trace 41 of a upper pixel cell, improve aperture opening ratio with this.
Figure 10 is the structural representation of the 4th embodiment of display panels of the present invention, with above-mentioned first embodiment unlike: in the process forming insulated hole 71, the insulating film layer 70 covered above IGZO layer 20 is excavated simultaneously, thus be that the transparency electrode that main material is made is exposed by IGZO, to improve the driving force of panel heap liquid crystal.
Figure 11 is the structural representation of the 5th embodiment of display panels of the present invention, with above-mentioned first embodiment unlike: because the photoetching number of times of the first embodiment is less, in order to prevent grid can not well and gate drivers (not shown) be electrically connected, this the 5th embodiment need increase by an edge connector be connected with gate drivers 100, in the process of the step 4 of the first embodiment, form the contact hole that is connected with this edge connector 100 simultaneously, make the contact hole exposing surface of the edge connector 100 hidden by insulation course.
The present invention adopts the IGZO-TFT of self-aligned top gate structure, and in the process forming IGZO-TFT, by laying Al rete, through the pyroreaction in oxygen atmosphere, part IGZO layer being reacted and forming source electrode and drain electrode, and Al rete being reacted into Al simultaneously
2o
3insulation course, makes the stray capacitance Cgd of liquid crystal panel only have about 1/5 of conventional panels on the one hand, reduces kick-back voltage, reduces memory capacitance with this, improves aperture opening ratio; On the other hand, the light shield number of TFT panel is reduced to 4, has saved cost.
Claims (8)
1. a manufacture method for display panels, is characterized in that, comprises the steps:
Underlay substrate is formed IGZO layer;
On the basis forming above-mentioned IGZO layer pattern, first at IGZO layer cover gate insulation course, then form grid on gate insulator, then formed the lamination pattern of gate insulator and grid by photoetching process;
On the basis of lamination pattern forming above-mentioned gate insulator and grid, cover one deck Al rete, then high annealing in oxygen atmosphere, form Al
2o
3insulation course, source electrode, drain electrode and pixel electrode;
At the above-mentioned Al of formation
2o
3on the basis of insulation course, source electrode, drain electrode and pixel electrode structure, cover insulating film layer, then offer contact hole;
On the basis forming above-mentioned contact hole pattern, form data line.
2. the manufacture method of display panels according to claim 1, is characterized in that: pixel electrode and drain electrode are formed simultaneously and in planar structure, source electrode and drain electrode react after Al rete contacts with IGZO layer to be formed.
3. the manufacture method of display panels according to claim 1, is characterized in that: Al
2o
3insulation course is reacted by the Al of the oxygen atom in oxygen and Al rete and is formed.
4. the manufacture method of display panels according to claim 1, is characterized in that: the photoetching process forming the lamination pattern of gate insulator and grid is dry carving technology.
5. the manufacture method of display panels according to claim 1, is characterized in that: while formation data line, form the public electrode wire parallel with data line.
6. the manufacture method of display panels according to claim 1, is characterized in that: form sweep trace at the lamination pattern forming gate insulator and grid simultaneously, and sweep trace covers the IGZO layer of a upper pixel cell.
7. the manufacture method of display panels according to claim 1, is characterized in that: while offering contact hole, excavates the insulating film layer above IGZO layer.
8. the manufacture method of display panels according to claim 1, is characterized in that: also comprise an edge connector, forms the contact hole be connected with this edge connector while offering contact hole.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210586237.3A CN103076703B (en) | 2012-12-28 | 2012-12-28 | A kind of display panels and manufacture method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210586237.3A CN103076703B (en) | 2012-12-28 | 2012-12-28 | A kind of display panels and manufacture method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN103076703A CN103076703A (en) | 2013-05-01 |
| CN103076703B true CN103076703B (en) | 2015-11-25 |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104600080B (en) * | 2014-12-30 | 2018-10-19 | 深圳市华星光电技术有限公司 | The preparation method of array substrate, display panel and array substrate |
| CN106024638A (en) * | 2016-07-20 | 2016-10-12 | 深圳市华星光电技术有限公司 | Film transistor and manufacturing method thereof |
Citations (5)
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| US6777309B1 (en) * | 2003-01-28 | 2004-08-17 | Gem Line Technology Co., Ltd. | Method for fabricating thin film transistor display device |
| WO2008059633A1 (en) * | 2006-11-15 | 2008-05-22 | Sharp Kabushiki Kaisha | Semiconductor element, method for fabricating the same and display |
| CN101981676A (en) * | 2008-04-02 | 2011-02-23 | Nec液晶技术株式会社 | Semiconductor device, semiconductor device manufacturing method, liquid crystal display device and electronic apparatus |
| JP2012049211A (en) * | 2010-08-25 | 2012-03-08 | Fujifilm Corp | Method of manufacturing oxide semiconductor thin film, oxide semiconductor thin film, method of manufacturing thin film transistor, thin film transistor, and device having thin film transistor |
| CN102723334A (en) * | 2012-06-07 | 2012-10-10 | 南京中电熊猫液晶显示科技有限公司 | Metal oxide thin-film transistor substrate, manufacture method thereof and liquid crystal display |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100606448B1 (en) * | 2003-12-29 | 2006-07-31 | 엘지.필립스 엘시디 주식회사 | Fabrication method of liquid crystal display device using 2 mask |
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- 2012-12-28 CN CN201210586237.3A patent/CN103076703B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6777309B1 (en) * | 2003-01-28 | 2004-08-17 | Gem Line Technology Co., Ltd. | Method for fabricating thin film transistor display device |
| WO2008059633A1 (en) * | 2006-11-15 | 2008-05-22 | Sharp Kabushiki Kaisha | Semiconductor element, method for fabricating the same and display |
| CN101981676A (en) * | 2008-04-02 | 2011-02-23 | Nec液晶技术株式会社 | Semiconductor device, semiconductor device manufacturing method, liquid crystal display device and electronic apparatus |
| JP2012049211A (en) * | 2010-08-25 | 2012-03-08 | Fujifilm Corp | Method of manufacturing oxide semiconductor thin film, oxide semiconductor thin film, method of manufacturing thin film transistor, thin film transistor, and device having thin film transistor |
| CN102723334A (en) * | 2012-06-07 | 2012-10-10 | 南京中电熊猫液晶显示科技有限公司 | Metal oxide thin-film transistor substrate, manufacture method thereof and liquid crystal display |
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