CN103066170A - Manufacturing method of nanoscale patterned substrate - Google Patents
Manufacturing method of nanoscale patterned substrate Download PDFInfo
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- CN103066170A CN103066170A CN2012105639116A CN201210563911A CN103066170A CN 103066170 A CN103066170 A CN 103066170A CN 2012105639116 A CN2012105639116 A CN 2012105639116A CN 201210563911 A CN201210563911 A CN 201210563911A CN 103066170 A CN103066170 A CN 103066170A
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Abstract
The invention provides a manufacturing method of a nanoscale patterned substrate. The manufacturing method of the nanoscale patterned substrate includes that a substrate is provided, a conducting layer is formed on the substrate layer; electro-deposition technique is used for the substrate layer to decompose metal and to form metal nanoparticles, the metal and the conducting layer are made from different material textures, and time using in the electro-deposition technique is far shorter than time using in film forming of the electro-deposition technique; the metal nanoparticles act as a mask film to corrode the conducting layer and to form a patterned conducting layer; the patterned conducting layer acts as the mask film to corrode the substrate; the patterned conducting layer and the metal nanoparticles are eliminated to form a nanoscale patterned substrate. The manufacturing method of the nanoscale patterned substrate utilizes the electro-deposition technique to form the metal nanoparticles on the conducting layer, and then utilizes the metal nanoparticles to act as the mask film to corrode the conducting layer, and corrode the substrate to form the nanoscale patterned substrate. The manufacturing method of the nanoscale patterned substrate has the advantages of being simple in technique, and low in technique cost.
Description
Technical field
The present invention relates to LED manufacturing technology field, relate in particular to a kind of manufacture method of nano patterned substrate.
Background technology
In the LED manufacturing technology process, because saphire substrate material and epitaxial material all differ greatly to refractive index from lattice constant, thermal expansion factor.These physical property differences directly cause the epitaxial material of Grown of low quality, cause LED internal quantum efficiency (IQE) to be restricted, and then affect the raising of external quantum efficiency (EQE) and light efficiency.
In order to improve LED efficient, industry has been introduced patterned low temperature buffer layer, and described patterned low temperature buffer layer can improve internal quantum efficiency, specifically, then epitaxial growth low temperature buffer layer on substrate carries out graphically other epitaxial loayer of afterwards regrowth to described low temperature buffer layer first.So, namely need three steps of epitaxial growth of epitaxial growth-graphical-again, so that complex process, time-consuming.
Therefore, graphical sapphire substrate (Patterned Sapphire Substrate, PSS) technology is introduced into, itself and method difference before are, the PSS technology has been accomplished the figure on the original low temperature buffer layer on the substrate, that is to say patterned substrate but not graphical low temperature buffer layer has so just overcome above-mentioned shortcoming.The principle that the PSS technology can improve LED efficient is effectively to reduce poor row's density, reduces the epitaxial growth defective, promotes the epitaxial wafer quality, reduces non-radiative recombination center, has improved interior quantum effect; In addition, the PSS structure has increased the order of reflection of photon at the sapphire interface place, the probability of photon effusion LED active area is increased, thereby light extraction efficiency is improved.PSS mainly makes flow process and comprises: mask layer is made, mask layer is graphical, mask pattern is removed four steps to transfer and the mask layer of substrate.Photoetching technique conventional on micron order just can satisfy the graphical process requirements of mask layer, but, along with the pattern of PSS technology is seted out towards nanoscale by micron order, cost and the difficulty of the process of conventional patterned substrate can't be applicable to large-scale production.
The patterned method of nanoscale PSS (NPSS:nano-PSS) technology mask layer is mainly nano impression at present.The basic thought of nano impression is by forming nano level pattern at mould, with die marks on the medium that is formed on the substrate, medium is the very thin polymer film of one deck normally, by mould the hot pressing of medium or the methods such as irradiation that see through mould are made the media structure sclerosis, thereby retain figure.Nano impression has very high requirement to the resolution of mould, planarization, uniformity, surface etc., and, in the moulding process, aiming between mould and the impression materials, the depth of parallelism, pressure uniformity, temperature homogeneity, ejection technique etc. all exist more problem.
Summary of the invention
The invention provides a kind of manufacture method of nano patterned substrate, utilize electrodeposition technology to form metal nanoparticle at conductive layer, and then utilize metal nanoparticle to be the mask etching conductive layer, then etched substrate is to form nano patterned substrate.The method has the advantage that technique is simple, process costs is low.
The invention provides a kind of manufacture method of nano patterned substrate, comprising:
Substrate is provided, forms conductive layer at described substrate;
Use electrodeposition technology to form metal nanoparticle at described conductive layer, described metal is different from the material of conductive layer;
As mask, the described conductive layer of etching forms patterned conductive layer with described metal nanoparticle;
Take described patterned conductive layer as mask, the described substrate of etching;
Remove described patterned conductive layer and metal nanoparticle, form nano patterned substrate.
Optionally, described conductive layer is metal level or the ITO rete that Ag, Au, Cu form.
Optionally, the thickness of described conductive layer is 10nm～100nm.
Optionally, the metal material of described electrodeposition technology deposition is Ag, Au or Cu.
Optionally, the electrodeposition technology time of formation metal nanoparticle is 5 seconds～15 seconds.
Optionally, described wet-etching technology or the described conductive layer of plasma etching of utilizing.
Optionally, the etching liquid of described wet-etching technology is FeCl
3
Optionally, utilize wet-etching technology or plasma etching industrial to come the described substrate of etching
Optionally, utilize the method for cmp or etching to remove described patterned conductive layer and metal nanoparticle.
The invention provides a kind of manufacture method of nano patterned substrate, the manufacture method of described nano patterned substrate forms conductive layer at substrate, then carry out electrodeposition technology at conductive layer, form metal nanoparticle by shortening the electrodeposition technology time afterwards, with metal nanoparticle as the mask etching conductive layer, at last take conductive layer as the mask etching substrate, to form the nano patterned substrate of figure.The method need not be used high-precision photoetching equipment, also impresses without mould, and it is simple to have technique, the advantage that process costs is low.
Description of drawings
Fig. 1 is the flow chart of manufacture method of the nano patterned substrate of the embodiment of the invention;
Fig. 2 A～2E is the generalized section of each step of manufacture method of the nano patterned substrate of the embodiment of the invention.
Embodiment
Mention that in background technology existing NPSS method has defective separately, and process costs is had higher requirement.The invention provides a kind of manufacture method of nano patterned substrate, the manufacture method of described nano patterned substrate forms conductive layer at substrate, then carry out electrodeposition technology at conductive layer, form metal nanoparticle by shortening the electrodeposition technology time, afterwards with metal nanoparticle as the mask etching conductive layer, at last take conductive layer as the mask etching substrate, to form the nano patterned substrate of figure.The method need not be used high-precision photoetching equipment, also impresses without mould, and it is simple to have technique, the advantage that process costs is low.
Below in conjunction with accompanying drawing the present invention is described in more detail, has wherein represented the preferred embodiments of the present invention, should the described those skilled in the art of understanding can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.In the following description, be not described in detail known function and structure, the confusion because they can make the present invention owing to unnecessary details.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details to realize developer's specific objective, for example according to relevant system or relevant commercial restriction, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but only be routine work to those skilled in the art.
In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-accurately ratio, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
Please refer to Fig. 1, it is the flow chart of manufacture method of the nano patterned substrate of the embodiment of the invention, and described method comprises the steps:
Step S021 provides substrate, forms conductive layer at described substrate;
Step S022 uses electrodeposition technology to form metal nanoparticle at described conductive layer, and described metal is different from the material of conductive layer;
Step S023, as mask, the described conductive layer of etching forms patterned conductive layer with described metal nanoparticle;
Step S024, take described patterned conductive layer as mask, the described substrate of etching;
Step S025 removes described patterned conductive layer and metal nanoparticle, forms nano patterned substrate.
The core concept of the method is, form conductive layer at substrate, then carry out electrodeposition technology at conductive layer, form metal nanoparticle by shortening the electrodeposition technology time, afterwards with metal nanoparticle as the mask etching conductive layer, at last take conductive layer as the mask etching substrate, to form the nano patterned substrate of figure.
With reference to Fig. 2 A, execution in step S021 provides substrate 101, forms conductive layer 102 at described substrate 101.In the present embodiment, described substrate 101 is Sapphire Substrate, conductive layer 102 provides the place for follow-up electrodeposition technology, conductive layer 102 is conductive material, be preferably Ag, Au, Cu or ITO(Indium tin oxide, tin indium oxide), in the present embodiment, conductive layer 102 is the ito thin film layer, and thickness is 10nm～100nm.
With reference to figure 2B, execution in step S022 uses electrodeposition technology to form metal nanoparticle 103 at described conductive layer 102.Electrodeposition technology usually is used for film forming, in its incipient stage, metal ion is separated out at conductive layer from electric depositing solution by electrochemical reaction and is formed nucleus, metal ion continues to form nucleus at conductive layer on the one hand under electrochemical action, enter on the other hand nucleus, make nucleus growth, finally form continuous membrane structure at conductive layer.Electrodeposition technology is in order to form metal nanoparticle in the application's the scheme, need not to form continuous film, thereby the time of electrodeposition technology controlled, make it much smaller than the time that forms continuous membrane structure, only form nano level metallic crystal on conductive layer 102 surfaces like this, that is, metal nanoparticle 103.Make owing in subsequent step, need utilize metal nanoparticle 103 to come etching conductive layer 102 as mask, therefore the material of metal nanoparticle 103 need to be different from conductive layer 102 materials, be preferably Ag, Au or Cu, the material of metal nanoparticle 103 is elected Ag as in the present embodiment, and the time of electrodeposition technology is 5 seconds～15 seconds.
With reference to figure 2C, execution in step S023, as mask, the described conductive layer 102 of etching forms patterned conductive layer 102 ' with described metal nanoparticle 103.Can utilize wet etching or plasma etching to come the described conductive layer 102 of etching, utilize wet-etching technology in the present embodiment, etching liquid is elected FeCl as
3Solution.Those skilled in the art can come selective etching mode and etching liquid or etching gas according to the concrete material of conductive layer 102 and metal nanoparticle 103.
With reference to figure 2D, execution in step S024, take described patterned conductive layer 102 ' as mask, the described substrate 101 of etching.Can utilize wet etching or plasma etching to come the described substrate 101 of etching.The preferred graphical described substrate 101 of wet-etching technology that adopts in the present embodiment, for example, can select that the etching liquid of the patterned conductive layer 102 ' of etching hardly to form hole 104 at substrate smoothly, forms patterned substrate 101 ' to described substrate 101 etch rates are higher.Certainly, as select the etching liquid that can both carry out etching to patterned conductive layer 102 and Sapphire Substrate 101, temperature and the process time of etching technics are controlled, can be implemented in completing steps S023 and step S024 in the step.
With reference to figure 2E, execution in step S025 removes described patterned conductive layer 102 ' and metal nanoparticle 103, forms nano patterned substrate 101 '.Can remove by the method for cmp or etching described patterned conductive layer 102 ' and metal nanoparticle 103.Afterwards, finish patterned Sapphire Substrate 101 ' and can enter the follow-up techniques such as epitaxial growth.
In sum, the invention provides a kind of manufacture method of nano patterned substrate, the manufacture method of described nano patterned substrate forms conductive layer at substrate, then carry out electrodeposition technology at conductive layer, form metal nanoparticle by shortening the electrodeposition technology time, afterwards with metal nanoparticle as the mask etching conductive layer, at last take conductive layer as the mask etching substrate, to form the nano patterned substrate of figure.The method need not be used high-precision photoetching equipment, also impresses without mould, and it is simple to have technique, the advantage that process costs is low.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (9)
1. the manufacture method of a nano patterned substrate comprises:
Substrate is provided, forms conductive layer at described substrate;
Use electrodeposition technology to form metal nanoparticle at described conductive layer, described metal is different from the material of conductive layer;
As mask, the described conductive layer of etching forms patterned conductive layer with described metal nanoparticle;
Take described patterned conductive layer as mask, the described substrate of etching;
Remove described patterned conductive layer and metal nanoparticle, form nano patterned substrate.
2. the manufacture method of nano patterned substrate as claimed in claim 1 is characterized in that: described conductive layer is metal level or the ITO rete that Ag, Au, Cu form.
3. the manufacture method of nano patterned substrate as claimed in claim 1, it is characterized in that: the thickness of described conductive layer is 10nm～100nm.
4. the manufacture method of nano patterned substrate as claimed in claim 1 is characterized in that: the metal material of described electrodeposition technology deposition is Ag, Au or Cu.
5. the manufacture method of nano patterned substrate as claimed in claim 1 is characterized in that: the electrodeposition technology time that forms metal nanoparticle is 5 seconds～15 seconds.
6. the manufacture method of nano patterned substrate as claimed in claim 1 is characterized in that: utilize wet-etching technology or the described conductive layer of plasma etching industrial etching.
7. the manufacture method of nano patterned substrate as claimed in claim 6, it is characterized in that: the etching liquid of described wet-etching technology is FeCl
3
8. the manufacture method of nano patterned substrate as claimed in claim 1 is characterized in that: utilize wet-etching technology or the described substrate of plasma etching industrial etching.
9. the manufacture method of nano patterned substrate as claimed in claim 1 is characterized in that: utilize cmp or etching technics to remove described patterned conductive layer and metal nanoparticle.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105679905A (en) * | 2016-01-19 | 2016-06-15 | 上海万寅安全环保科技有限公司 | Semiconductor chip |
| CN108428566A (en) * | 2018-01-23 | 2018-08-21 | 浙江工业大学 | A kind of high efficiency preparation method of the planar miniature electrode of super capacitor of interdigital structure |
| CN108609579A (en) * | 2018-04-25 | 2018-10-02 | 中原工学院 | A method of preparing patterned silicon substrate without photoetching technique |
| CN109216521A (en) * | 2018-10-30 | 2019-01-15 | 扬州乾照光电有限公司 | A kind of preparation method and LED chip of LED chip |
| CN109239815A (en) * | 2017-07-10 | 2019-01-18 | 上海箩箕技术有限公司 | Cover board and forming method thereof, cover board motherboard, electronic equipment |
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| CN101308219A (en) * | 2008-06-27 | 2008-11-19 | 吉林大学 | Method for constructing anti-reflection microstructure using single layer nanometer particle as etching blocking layer |
| JP2010258456A (en) * | 2009-04-27 | 2010-11-11 | Aurotek Corp | Silicon substrate with periodical structure |
| CN102299055A (en) * | 2011-06-13 | 2011-12-28 | 协鑫光电科技（张家港）有限公司 | Method for manufacturing nanospheres on surface of sapphire substrate |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101308219A (en) * | 2008-06-27 | 2008-11-19 | 吉林大学 | Method for constructing anti-reflection microstructure using single layer nanometer particle as etching blocking layer |
| JP2010258456A (en) * | 2009-04-27 | 2010-11-11 | Aurotek Corp | Silicon substrate with periodical structure |
| CN102299055A (en) * | 2011-06-13 | 2011-12-28 | 协鑫光电科技（张家港）有限公司 | Method for manufacturing nanospheres on surface of sapphire substrate |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105679905A (en) * | 2016-01-19 | 2016-06-15 | 上海万寅安全环保科技有限公司 | Semiconductor chip |
| CN109239815A (en) * | 2017-07-10 | 2019-01-18 | 上海箩箕技术有限公司 | Cover board and forming method thereof, cover board motherboard, electronic equipment |
| CN108428566A (en) * | 2018-01-23 | 2018-08-21 | 浙江工业大学 | A kind of high efficiency preparation method of the planar miniature electrode of super capacitor of interdigital structure |
| CN108609579A (en) * | 2018-04-25 | 2018-10-02 | 中原工学院 | A method of preparing patterned silicon substrate without photoetching technique |
| CN109216521A (en) * | 2018-10-30 | 2019-01-15 | 扬州乾照光电有限公司 | A kind of preparation method and LED chip of LED chip |
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| CN103066170B (en) | 2016-03-30 |
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Effective date of registration: 20180627 Address after: 201306 N1128 room 23, 2 New Town Road, mud town, Pudong New Area, Shanghai Patentee after: Gallium semiconductor technology (Shanghai) Co., Ltd. Address before: 201306 1889 Hong Yin Road, Lingang industrial area, Pudong New Area, Shanghai Patentee before: EnRay Tek Optoelectronics (Shanghai) Co., Ltd. |
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