CN103065008A - Sequential logic circuit reverse design method based on 2 sequence decomposition (2SD)/ virtual reconstruction circuit (VRC) composite EHW - Google Patents
Sequential logic circuit reverse design method based on 2 sequence decomposition (2SD)/ virtual reconstruction circuit (VRC) composite EHW Download PDFInfo
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Abstract
The invention discloses a sequential logic circuit reverse design method based on 2 sequence decomposition (2SD)/ virtual reconstruction circuit (VRC) composite EHW (2SD: input sequence decomposition and output sequence decomposition; VRC: virtual reconstruction circuit and EHW circuit evolution). By means of the method, a simple input/ output sequence can be utilized to achieve multi input/ output or reverse design of a sequential logic circuit when device connection relation is not clear. The method includes recording input/ output waveform of the circuit in work online to obtain the input/ output sequence, conducting analysis on the input/ output sequence according to circuit function and signal definition to obtain a plurality of input/ output sub sequence pairs, conducting circuit evolution on each sub sequence pair with a virtually reconstructed circuit model as base to obtain a corresponding sub circuit model, finally utilizing the obtained sub circuit models as base to conduct composite circuit evolution on the input/ output sequence of the sequential logic circuit to obtain a circuit model of the sequential logic circuit and adopting manual interfering mode to obtain a circuit principle diagram according to the model to achieve reverse design of the sequential logic circuit principle. The method effectively resolves the problem that circuit principle reverse design is conducted when input/ output of the sequential logic circuit is much, circuit structure is not known, or device and device connection relation are not clear when an electronic device is introduced.
Description
Technical field
The invention belongs to technical field of measurement and test, it is more or circuit structure not clear or device not clear or the reverse engineer of the not clear sequential logical circuit principle of work of device annexation to be mainly used in introducing input and output in the electronic equipment, realized by sequential logical circuit input/output signal waveform is enrolled, the Wave data conversion, input and output Series Decomposition (2SD), the virtual reconstruct of circuit model (VRC), electronic circuit is evolved, the compound evolution of sequential logical circuit obtains the circuit model of sequential logical circuit, obtains the Reverse Design of its circuit theory diagrams by the manual intervention to this model.
Background technology
Because between the sequential logical circuit device or have feedback link between the input and output, more or circuit structure is not clear or device is not clear or device annexation when not clear when the circuit input signal output signal, becomes unusually difficult with the schematic diagram of conventional means acquisition cuicuit.At present to the equal less sequential logical circuit of input signal and output signal, the virtual reconfigurable circuit of integrated use and circuit are evolved and can be utilized evolve out the circuit model of sequential logical circuit of its list entries and output sequence, and this circuit model has the function identical with primary circuit; When sequential logical circuit input signal and output signal were more, the method that adopts circuit to evolve often can not obtain desired result.Because the input and output of sequential logical circuit are more in a lot of introduction electronic equipments, therefore, obtain its Reverse Design by the circuit evolution of studying the multiple-input and multiple-output sequential logical circuit and have great importance.
Summary of the invention
The problem that the present invention solves is: overcome now methodical deficiency, for the more or indefinite sequential logical circuit of circuit relationships of input and output in some introduction electronic equipment, having realized is only evolved by virtual reconfigurable circuit and circuit by the input and output sequence obtains the method for its circuit theory diagrams.Having filled up China can't obtain and introduce in the electronic equipment multiple-input and multiple-output or circuit relationships is indefinite or device is indefinite or the blank of the indefinite sequential logical circuit principle of work of device annexation reverse engineer present stage.
Technical solution of the present invention is:
A kind of based on the compound EHW sequential logical circuit of 2SD/VRC Reverse Design method, by the circuit evolution Model of the admission of sequential logical circuit input/output signal, Wave data conversion, input and output Series Decomposition (2SD), the virtual reconstruct of circuit model (VRC), electronic circuit being evolved, the compound evolution of sequential logical circuit obtains sequential logical circuit, can obtain corresponding circuit theory diagrams by the manual intervention to this model, realize the reverse engineer of sequential logical circuit.It is characterized in that: may further comprise the steps:
(1) at first the sequential logical circuit input/output signal of the unknown is enrolled online, obtain its input-output wave shape, and be binary data file with waveform transformation, form list entries and output sequence.
(2) according to sequential logical circuit function and circuit pinout list entries and output sequence are resolved into a plurality of sub-list entries and sub-output sequence pair, and use the dynamic generating algorithm of compressive state network to form the right state-transition table of subsequence.
(3) make up the virtual circuit model, take this model as base unit a plurality of subsequences are evolved to carrying out circuit, obtain subsequence to the sub circuit model of correspondence.Made up the fitness evaluating function fitness3 based on entropy and objective function in the evolutionary process, its form of presentation is as follows:
Wherein: T is the actual measurement output sequence, and C is the simulation data sequence;
Wherein: o
I, jBe the capable j row of i in the corresponding output matrix of an individuality element; O '
I, jBe the capable j row of i in a target output matrix element.
(4) to obtain sub circuit model as base unit, list entries and output sequence are carried out the circuit evolution, obtain the circuit model of sequential logical circuit.
(5) the sequential logical circuit model that obtains is carried out manual intervention, obtain the circuit theory diagrams of sequential logical circuit reverse engineer.
2, the described input-output wave shape of step (1) is converted to the binary file method according to claim 1, realization is by the conversion of admission waveform to data file, can obtain simultaneously sequential logical circuit list entries and output sequence that determine, complete, it is characterized in that: enroll online according to the described signal of step (1), obtain input signal and the signal output waveform of sequential logical circuit; Simultaneously, signal admission equipment becomes binary data file with the waveform transformation of admission; Under the effect of known control signal, this binary file is become a plurality of list entries and output sequence pair by automatic classifying; Carried out omnidistance signal admission when sequential logical circuit is worked, the list entries that therefore obtains and output sequence are to having completeness.
3, the described list entries of step (2) decomposes and the output sequence decomposition according to claim 1, it is characterized in that: may further comprise the steps: the function of analyzing sequential logical circuit, and determine function and the definition of its pin by the superior and the subordinate's circuit, then list entries is decomposed; Sub-list entries according to decomposing decomposes output sequence, forms sub-list entries and sub-output sequence pair.Antithetical phrase list entries and sub-output sequence obtain sub-list entries and the right state-transition table of sub-output sequence to using the dynamic generating algorithm of compressive state network.
4, the acquisition methods of the described sub circuit model of step (3) according to claim 1, it is characterized in that: may further comprise the steps: according to the feature of sequential logical circuit, make up the minimum unit model of virtual reconfigurable circuit, this model can effectively solve the feedback problem of sequential logical circuit; Use the minimum unit model, carry out the circuit evolution to requiring the subsequence in 1 step (2) to using genetic algorithm and ant algorithm; Using Matlab software that evolution Model is carried out emulation, obtain the simulation data sequence under sub-list entries; Structure is based on the fitness evaluating function of entropy and objective function; And use this valuation functions simulation data sequence and corresponding sub-output sequence are carried out the fitness assessment; If satisfy evaluation condition, then to evolve and finish, expression has obtained the virtual reconstruction model of electronic circuit; If do not satisfy evaluation condition, then revise the configuration bit string of evolving, continue to evolve, until satisfy evaluation condition.
5, the described sequential logical circuit circuit model of step (4) acquisition methods according to claim 1, it is characterized in that: may further comprise the steps: will require sub circuit model in 1 step (3) as virtual reconfiguration unit, to require list entries in 1 step (1) and output sequence to use genetic algorithm and ant algorithm carries out circuit and evolves, in Matlab software, evolution Model is carried out emulation, the simulation data sequence of acquisition under list entries, the fitness evaluating function of structure carries out the fitness assessment to simulation data sequence and list entries in application requirements 1 step (3), until satisfy evaluation condition, then evolve and finish, namely obtained the circuit model of sequential logical circuit.
6, the described circuit theory picture capturing method of step (5) according to claim 1, it is characterized in that: may further comprise the steps: according to the sequential logical circuit circuit model that requires 1 step (4) to obtain, contrast existing digital logic chip, adopt the mode of manual intervention that circuit model is converted to digital circuit figure, namely obtain the circuit theory diagrams of sequential logical circuit, finish the reverse engineer of sequential logical circuit.
The advantage that the present invention has is: the Reverse Design of having studied a kind of sequential logical circuit based on the compound EHW of 2SD/VRC.When more and device, layout or annexation are indefinite when the input and output of sequential logical circuit, at first the sequential logical circuit input/output signal being enrolled online, is binary file with the waveform transformation of admission, obtains list entries and output sequence; Secondly, list entries and output sequence are resolved into a plurality of sub-list entries and sub-output sequence pair, the right input and output of subsequence are less; And then, adopt virtual reconfigurable circuit and circuit to evolve and obtain subsequence to the sub circuit model of correspondence; Then take sub circuit model as the basis, still adopt the circuit model of sequential logical circuit corresponding to virtual reconfigurable circuit and circuit evolution acquisition list entries and output sequence; Have most, adopt the manual intervention mode, obtain the circuit theory diagrams of sequential logical circuit, realize reverse engineer.It is not clear or circuit structure is not clear or the device annexation is introduced the reverse problem of obtaining of electronics sequential logical circuit principle of work when not clear that the method efficiently solves the more or device of input and output.
Description of drawings
Fig. 1 is the sequential logical circuit reverse engineer process flow diagram based on the compound EHW of 2SD/VRC;
Fig. 2 is the dynamic generating algorithm process flow diagram of compressive state network;
Fig. 3 is virtual reconfigurable circuit minimum unit model;
Fig. 4 is electronic circuit evolution process flow diagram;
Fig. 5 is parity checking module input/output signal oscillogram;
Fig. 6 is that subsequence is to 1 circuit model of evolving;
Fig. 7 is the circuit model that sequential logical circuit is evolved;
The circuit theory diagrams that Fig. 8 obtains for the circuit model by sequential logical circuit.
Embodiment
The below utilizes process of the sequential logical circuit M36Y of certain type introduction electronic equipment being carried out reverse engineer generating principle figure based on the sequential logical circuit Reverse Design of the compound EHW of 2SD/VRC of the present invention.
(1) input/output signal is enrolled formation list entries and output sequence online
Adopt the admission of signal on-line monitoring and analytical equipment that the input and output signal of sequential logical circuit M36Y is enrolled, portion waveshape as shown in Figure 5.The input/output signal waveform is changed, obtained list entries and output sequence.
(2) two steps were decomposed to form sub-list entries and sub-output sequence pair
This sequential logical circuit M36Y finishes the input data mode and triggers, keeps in circuit, the driving translation function is finished in input to part simultaneously.According to the function of this module, the list entries of this sequential logical circuit and output sequence can be divided into 3 antithetical phrase list entries and sub-output sequence; Wherein 2 pairs relevant with sequential, be sequential logical circuit; 1 pair is data drive circuit, is combinational circuit; Wherein a pair of relevant with sequential sub-list entries input number is that 4, sub-output sequence output number are 1; Another is that 6, sub-output sequence output number are 3 to relevant with sequential sub-list entries input number; Utilize the dynamic generating algorithm of compressive state network to obtain the state-transition table of 2 pairs of sub-list entries of sequential logical circuit and sub-output sequence.
(3) antithetical phrase list entries and sub-output sequence obtain sub circuit model to carrying out the circuit evolution
The minimum unit model that makes up take Fig. 3 is as the basis, respectively 2 pairs of sub-list entries of sequential logical circuit and sub-output sequence are carried out the circuit evolution, its fitness evaluating function is the fitness evaluating function based on entropy and objective function, thereby has obtained its sub circuit model; Subsequence such as 1 output of 4 inputs is Fig. 6 to the circuit model of evolving, and all the other 4 right evolution Model of subsequence are no longer listed.
(4) list entries and output sequence are carried out circuit evolution acquisition sequential logical circuit circuit model
The 5 sub-circuits models that obtain in (3) carry out circuit as elementary cell to list entries of obtaining in (1) and output sequence evolves, and obtains the circuit evolution Model of whole sequential logical circuit, as shown in Figure 7.
(5) adopt manual intervention to obtain the sequential logical circuit schematic diagram
Adopt the manual intervention mode that the sequential logical circuit evolution Model that obtains in (4) is carried out circuit analysis, replace evolution Model with digit chip commonly used, obtain the schematic diagram of sequential logical circuit M36Y, as shown in Figure 8.
Sequential logical circuit Reverse Design based on the compound EHW of 2SD/VRC provided by the invention, realized that multiple-input and multiple-output or device are not clear or circuit structure not clear or the obtaining of the indefinite sequential logical circuit schematic diagram of device annexation, for domestic function development and the maintenance of equipment of introducing the electronic equipment sequential logical circuit provides method foundation and means.
Claims (6)
1. one kind based on the compound EHW sequential logical circuit of 2SD/VRC Reverse Design method, by the circuit evolution Model of the admission of sequential logical circuit input/output signal, Wave data conversion, input and output Series Decomposition (2SD), the virtual reconstruct of circuit model (VRC), electronic circuit being evolved, the compound evolution of sequential logical circuit obtains sequential logical circuit, can obtain corresponding circuit theory diagrams by the manual intervention to this model, realize the reverse engineer of sequential logical circuit.It is characterized in that: may further comprise the steps:
(1) at first the sequential logical circuit input/output signal of the unknown is enrolled online, obtain its input-output wave shape, and be binary data file with waveform transformation, form list entries and output sequence.
(2) according to sequential logical circuit function and circuit pinout list entries and output sequence are resolved into a plurality of sub-list entries and sub-output sequence pair, and use the dynamic generating algorithm of compressive state network to form the right state-transition table of subsequence.
(3) make up the virtual circuit model, take this model as base unit a plurality of subsequences are evolved to carrying out circuit, obtain subsequence to the sub circuit model of correspondence.
(4) to obtain sub circuit model as base unit, list entries and output sequence are carried out the circuit evolution, obtain the circuit model of sequential logical circuit.
(5) the sequential logical circuit model that obtains is carried out manual intervention, obtain the circuit theory diagrams of sequential logical circuit reverse engineer.
2. the described input-output wave shape of step (1) is converted to the binary file method according to claim 1, realization is by the conversion of admission waveform to data file, can obtain simultaneously sequential logical circuit list entries and output sequence that determine, complete, it is characterized in that: enroll online according to the described signal of step (1), obtain input signal and the signal output waveform of sequential logical circuit; Simultaneously, signal admission equipment becomes binary data file with the waveform transformation of admission; Under the effect of known control signal, this binary file is become a plurality of list entries and output sequence pair by automatic classifying; Carried out omnidistance signal admission when sequential logical circuit is worked, the list entries that therefore obtains and output sequence are to having completeness.
3. the described list entries of step (2) decomposes and the output sequence decomposition according to claim 1, it is characterized in that: may further comprise the steps: the function of analyzing sequential logical circuit, and determine function and the definition of its pin by the superior and the subordinate's circuit, then list entries is decomposed; Sub-list entries according to decomposing decomposes output sequence, forms sub-list entries and sub-output sequence pair.Antithetical phrase list entries and sub-output sequence obtain sub-list entries and the right state-transition table of sub-output sequence to using the dynamic generating algorithm of compressive state network.
4. the acquisition methods of the described sub circuit model of step (3) according to claim 1, it is characterized in that: may further comprise the steps: according to the feature of sequential logical circuit, make up the minimum unit model of virtual reconfigurable circuit, this model can effectively solve the feedback problem of sequential logical circuit; Use the minimum unit model, carry out the circuit evolution to requiring the subsequence in 1 step (2) to using genetic algorithm and ant algorithm; Using Matlab software that evolution Model is carried out emulation, obtain the simulation data sequence under sub-list entries; Structure is based on the fitness evaluating function of entropy and objective function; And use this valuation functions simulation data sequence and corresponding sub-output sequence are carried out the fitness assessment; If satisfy evaluation condition, then to evolve and finish, expression has obtained the virtual reconstruction model of electronic circuit; If do not satisfy evaluation condition, then revise the configuration bit string of evolving, continue to evolve, until satisfy evaluation condition.
5. the described sequential logical circuit circuit model of step (4) acquisition methods according to claim 1, it is characterized in that: may further comprise the steps: will require sub circuit model in 1 step (3) as virtual reconfiguration unit, to require list entries in 1 step (1) and output sequence to use genetic algorithm and ant algorithm carries out circuit and evolves, in Matlab software, evolution Model is carried out emulation, the simulation data sequence of acquisition under list entries, the fitness evaluating function of structure carries out the fitness assessment to simulation data sequence and list entries in application requirements 1 step (3), until satisfy evaluation condition, then evolve and finish, namely obtained the circuit model of sequential logical circuit.
6. the described circuit theory picture capturing method of step (5) according to claim 1, it is characterized in that: may further comprise the steps: according to the sequential logical circuit circuit model that requires 1 step (4) to obtain, contrast existing digital logic chip, adopt the mode of manual intervention that circuit model is converted to digital circuit figure, namely obtain the circuit theory diagrams of sequential logical circuit, finish the reverse engineer of sequential logical circuit.
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| CN116542188A (en) * | 2023-07-06 | 2023-08-04 | 深圳市鑫迅维科技有限公司 | PCB schematic diagram generation method, electronic equipment and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1497445A (en) * | 2002-10-09 | 2004-05-19 | 富士通株式会社 | Validation support method and equipment and computer product for support |
| CN102611684A (en) * | 2011-12-15 | 2012-07-25 | 东南大学 | Physical unclonable function module based on feed-forward mode and realization method thereof |
| CN202395810U (en) * | 2011-12-15 | 2012-08-22 | 东南大学 | Physical unclonable functional module based on feedforward mode |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1497445A (en) * | 2002-10-09 | 2004-05-19 | 富士通株式会社 | Validation support method and equipment and computer product for support |
| CN102611684A (en) * | 2011-12-15 | 2012-07-25 | 东南大学 | Physical unclonable function module based on feed-forward mode and realization method thereof |
| CN202395810U (en) * | 2011-12-15 | 2012-08-22 | 东南大学 | Physical unclonable functional module based on feedforward mode |
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| CN116542188A (en) * | 2023-07-06 | 2023-08-04 | 深圳市鑫迅维科技有限公司 | PCB schematic diagram generation method, electronic equipment and storage medium |
| CN116542188B (en) * | 2023-07-06 | 2024-04-05 | 深圳市鑫迅维科技有限公司 | PCB schematic diagram generation method, electronic equipment and storage medium |
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