CN103038748B - The technology based on region for accurate predicting access of storage - Google Patents

The technology based on region for accurate predicting access of storage Download PDF

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Publication number
CN103038748B
CN103038748B CN201180041024.6A CN201180041024A CN103038748B CN 103038748 B CN103038748 B CN 103038748B CN 201180041024 A CN201180041024 A CN 201180041024A CN 103038748 B CN103038748 B CN 103038748B
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China
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ptb
signature
access
project
processor
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Chinese (zh)
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CN103038748A (en
Inventor
L.索亚列斯
N.切鲁库里
A.库马
M.阿兹米
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Intel Corp
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Intel Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6024—History based prefetching

Abstract

In one embodiment, the present invention includes processor, and described processor includes: page tracker buffer (PTB), and this PTB includes multiple project to store the address of caching page and to store signature to follow the tracks of the access of each cache lines to caching page；And PTB handler, project is loaded into PTB and updates signature by this PTB handler.Also describe and claim other embodiments.

Description

The technology based on region for accurate predicting access of storage
Background technology
In order to improve performance and the efficiency of calculating system (such as PC, server etc.), data and instruction that prefetching (prefetch) processor may need after a while are considered as favourable.But, routine prefetches which cache lines that can not calculate to a nicety (cache line) should be prefetched or should not prefetch.
Brief description
Fig. 1 is the block diagram of example processor according to an embodiment of the invention and memory；
Fig. 2 is the block diagram of example page tracker buffer according to an embodiment of the invention；
Fig. 3 is according to an embodiment of the invention for utilizing the flow chart of the exemplary method of access signature；
Fig. 4 is according to an embodiment of the invention for utilizing the flow chart of the exemplary method reusing signature；
Fig. 5 is the block diagram of example system according to an embodiment of the invention.
Detailed description of the invention
In various embodiments, it is proposed that the method and apparatus that predictability prefetches.In the following description, for purposes of explanation, set forth a large amount of concrete details in order to provide the thorough explanation of the present invention.But, to those skilled in the art it would be apparent that embodiments of the invention can be implemented in the case of not having these concrete details.In other instances, show structure and equipment to avoid obscuring the present invention in block diagram form.
Run through this specification to mean to include specific feature, structure or the characteristic describing together with embodiment at least one embodiment of the present invention to mentioning of " embodiment " or " embodiment ".Therefore, phrase " in one embodiment " or " in an embodiment " appearance in each place running through this specification is not necessarily all referring to identical embodiment.Furthermore, it is possible to combine special characteristic, structure or characteristic in one or more embodiments in any suitable manner.
With reference now to Fig. 1, show the block diagram of example processor according to an embodiment of the invention and memory.As shown in Figure 1, system 100 can include processor 102 and memory 104.Processor 102 can include core (one or more) the 106th, level cache the 108th, translation look-aside (translation Lookaside) buffer (TLB) the 110th, page tracker buffer (PTB) the 112nd, L2 cache 114 and PTB handler 116.Although processor 102 is shown as including level cache 108 and L2 cache 114, but processor 102 can include any amount of caching rank.Same, although processor 102 is shown as the TLB 110 including storing the address conversion from virtual address to physical address, but the present invention can implement in the processor do not have TLB.
As illustrated in greater detail with reference to Fig. 2, PTB 112 can comprise to indicate the project (entry) which part (for example, which cache lines of particular cache page or other memory areas) of particular area of memory had previously been accessed by core (one or more) 106.In one embodiment, PTB 112 also comprises to indicate the project which cache lines of particular cache page has repeatedly been accessed by core (one or more) 106, and this indicates potentially and highly desirable may keep resident those cache lines in the buffer.
The instruction and data that core (one or more) 106 will need it is possible, as will be seen in more detail below, PTB handler 116 can be attempted calculating to a nicety.In one embodiment, PTB handler 116 prefetch PTB 112 indicate previously instantiate during be accessed, (such as TLB failure after) add those cache lines of the caching page of TLB 110 to.PTB handler 116 can read PTB 112 project from page tracker memory table 118, and PTB 112 project is write back to a page tracker memory table 118.For example when the additional cache lines of core (one or more) 106 access, PTB handler 116 can also update the project in PTB 112.PTB handler 116 can be realized with the combination of other hardware (for example prefetching module) or software or hardware and software.PTB handler 116 can be applied independently for data and instruction prefetch and can coexist with other prefetchers.
Memory 104 can represent any kind of memory, for example either statically or dynamically random-access memory (ram).In one embodiment, memory 104 represents double data rate synchronous dynamic ram (DDR-SDRAM), but the present invention is not limited to any kind of memory.Memory 104 can be logically divided into page (such as page 120) and is used for caching and addresses.Each page 120 can comprise the row 122 of fixed qty.In one embodiment, page 120 comprises 64 row 122.In another embodiment, page 120 represents the memory area that can pass through firmware or its size of software merit rating.
With reference now to Fig. 2, the block diagram of example page tracker buffer according to an embodiment of the invention is shown.Going out as shown in FIG. 2, page tracker buffer 112 can include can be by any amount of projects of index 208 access, and each of described project can include that the 202nd, address accesses signature (access Signature) 204 and reuse signature (reuse Signature) 206.In one embodiment, PTB 112 can include the project with TLB 110 equal number.In other embodiments, PTB 112 can include the project more or more less than TLB 110.In one embodiment, PTB 112 can include 64 projects.In another embodiment, PTB 112 can include 1024 projects.
Although address 202 being shown as including 28 bits, but address 202 can comprise more or less bit for identifying page 120(or another memory area).Although access signature 204 and reuse signature 206 are shown as including 64 bits, but access signature 204 can comprise with reuse signature 206 or more or less bit is for identifying the row 122 of page 120.In one embodiment, by the row 122 of the page 120 of core (one or more) 106 access in the previously addressing of page 120 in TLB 110 for set (set bit) instruction of access signature 204.In one embodiment, the set reusing signature 206 indicates at TLB By the row 122 of the page 120 of more than 106 access of core (one or more) in the previously addressing of the page 120 in 110.
With reference now to Fig. 3, illustrate according to an embodiment of the invention for utilizing the flow chart of the exemplary method of access signature.Go out as shown in FIG. 3, the method start from PTB handler 116 after any project being expelled out of (evicted) is write back to page tracker memory table 118 by access signature 204 loading (302) that associates with caching page 120 in PTB 112.In one embodiment, at TLB After 110 failures (miss), PTB handler 116 is loaded into access signature 204 and writes back any access signature being just replaced.Then, PTB handler 116 can be designated as previously being prefetched (304) to L2 cache 114 by the row 122 of core (one or more) 106 access by access signature 204 by for example.Finally, PTB handler 116 can update (306) access signature 204.In one embodiment, when request and when taking out any additional row, PTB handler 116 is to the access signature 204 increase bits fetched.In another embodiment, the access signature 204 fetched can be used for prefetching and can regenerate access signature and is used for writing back to memory and uses in page access subsequently by PTB handler 116.
With reference now to Fig. 4, illustrate according to an embodiment of the invention for utilizing the flow chart of the exemplary method reusing signature.As shown in Figure 4, the method start from PTB handler 116 after any dispossessed project is write back to page tracker memory table 118 by reuse signature 206 loading (402) that associates with caching page 120 in PTB 112.In one embodiment, PTB handler 116 is loaded into after TLB 110 failure and reuses signature 206.Then, PTB handler 116 can be designated as previously repeatedly by the replacement policy of those cache lines in the L2 cache 114 of core (one or more) 106 access by reusing signature 206 with priorization (404).In one embodiment, those cache lines can be set at most use recently by PTB handler 116 by the hyte reusing in signature 206.In another embodiment, those cache lines can be set to least recently used by PTB handler 116, and without reusing the hyte in signature 206.Finally, when repeatedly asking any additional row, PTB handler 116 can update (406) and reuse signature 206.
Embodiment can realize with many different system types.With reference now to Fig. 5, the block diagram of system according to an embodiment of the invention is shown.Going out as shown in FIG. 5, multicomputer system 500 is point-to-point interconnection system, and includes the first processor 570 via point-to-point interconnection 550 coupling and the second processor 580.Going out as shown in FIG. 5, each of processor 570 and 580 can be to include the polycaryon processor of the first and second processor cores (that is, processor core 574a and 574b and processor core 584a and 584b).Each processor can include PTB hardware, software and firmware according to an embodiment of the invention.
Referring still to Fig. 5, first processor 570 also includes storage control hub (MCH, memory controller Hub) 572 and point-to-point (P-P) interface 576 and 578.Similarly, the second processor 580 includes MCH 582 and P-P interface 586 and 588.Go out as shown in FIG. 5, MCH 572 and 582 couple the processor to corresponding memory (i.e. memory 532 and memory 534), it can be to be locally attached to the main storage of respective processor (for example, dynamic random access memory (DRAM)) a part, according to one embodiment of present invention, each of described respective processor can include a page tracker memory table.First processor 570 and the second processor 580 can be respectively coupled to chipset 590 via P-P interconnection 552 and 554.Going out as shown in FIG. 5, chipset 590 includes P-P interface 594 and 598.
Additionally, chipset 590 includes the interface 592 for coupling chipset 590 with high performance graphics engine 538.And chipset 590 can be coupled to the first bus 516 via interface 596.Going out as shown in FIG. 5, various I/O equipment 514 can be coupled to the first bus 516 together with the first bus 516 is coupled to the bus bridge 518 of the second bus 520.Various equipment may be coupled to the second bus 520 in one embodiment, including for example, and keyboard/mouse the 522nd, communication equipment 526 and data storage cell 528(such as disc driver or other mass-memory units that code 530 can be included).Additionally, audio frequency I/O 524 may be coupled to the second bus 520.
Embodiment can realize with code and can be stored on the storage medium with the instruction being stored thereon, and storage medium can be used for System Programming to perform these instructions.Storage medium can include but is not limited to: any kind of dish (includes floppy disk, CD, compact disc read-only memory (CD-ROM), CD-RW (CD-RW) and magneto-optic disk), semiconductor equipment (such as read-only storage (ROM), random-access memory (ram) (such as dynamic random access memory (DRAM), static RAM (SRAM)), Erarable Programmable Read only Memory (EPROM), flash memory, EEPROM (EEPROM), magnetic or optical card) or it is suitable for storing the media of any other type of e-command.
Although the embodiment already in connection with limited quantity describes the present invention, but those skilled in the art will therefrom recognize substantial amounts of modifications and changes.Appending claims is intended to cover this type of modifications and changes all falling within the true spirit and scope of the present invention.

Claims (15)

1. a processor, comprising:
First core；
Level cache；
Translation lookaside buffer TLB；
L2 cache；
Page tracker buffer PTB, described PTB includes that multiple project is signed to store the address of storage page and memory access to follow the tracks of the access of each row to described storage page；And
PTB handler, described PTB handler is used for project is loaded into described PTB and updates described access signature,
Wherein, each PTB project reuses, for storing, the repeated access that signature follows the tracks of each row to described storage page, and described PTB handler is used for updating the described signature that reuses, and described PTB handler for priorization by the described replacement policy reusing those row that signature is designated as in the L2 cache being repeatedly accessed.
2. processor as claimed in claim 1, wherein said access signature and each reusing in signature described include 64 bits.
3. processor as claimed in claim 1, wherein said PTB comprises 64 projects.
4. processor as claimed in claim 1, wherein said PTB comprises 1024 projects.
5. processor as claimed in claim 1, project is loaded into described PTB and includes that page tracker memory table from memory for the project is loaded into described PTB by described PTB handler by wherein said PTB handler.
6. processor as claimed in claim 5, also includes the page tracker memory table that described PTB handler will store in described memory from the project that described PTB evicts from.
7. processor as claimed in claim 1, project is loaded into described PTB and includes that project is loaded into described PTB after TLB failure by described PTB handler by wherein said PTB handler.
8. the system for memory access, comprising:
Processor, described processor includes the first core, caching and page tracker buffer PTB performing instruction, the access signature which row that described PTB includes multiple project to store instruction storage page has been accessed, and store the reuse signature indicating which row of described storage page has repeatedly been accessed；
Being coupled to dynamic random access memory DRAM of described processor, described DRAM comprises the page tracker memory table of PTB project for storage；And
PTB handler, described PTB handler for being loaded into described PTB project from described page tracker memory table, described PTB handler for the described PTB project row that had previously been accessed of instruction is loaded into caching, and described PTB handler for priorization by the described replacement policy reusing those row that signature is designated as in the described caching being repeatedly accessed.
9. system as claimed in claim 8, also includes that PTB handler updates described PTB project to indicate that row has been accessed.
10. system as claimed in claim 8, also includes that described PTB project is write back to described page tracker memory table by described PTB handler.
11. systems as claimed in claim 8, wherein said processor also includes translation lookaside buffer TLB, and wherein when TLB failure, described PTB handler is loaded into PTB project.
12. 1 kinds of methods for memory access, comprising:
Reading the access signature associating with storage page and reusing signature, which row of the described storage page of described access signature instruction has been accessed, and described which row reusing the described storage page of signature instruction is repeatedly accessed；And
The row that described access signature instruction had previously been accessed is loaded into the caching of processor；And
Priorization is by the described replacement policy reusing those row that signature is designated as in the described caching being repeatedly accessed.
13. methods as claimed in claim 12, also include fetching described access signature from storage page tracker memory table in memory and described reuse signature.
14. methods as claimed in claim 13, also include updating described access signature and described reuse signature when the row of the described storage page of described processor access.
15. methods as claimed in claim 14, also include, when evicting described access signature and described reuse signature from, described access signature and described reuse signature storage are arrived described page tracker memory table.
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US20110320762A1 (en) 2011-12-29
CN103038748A (en) 2013-04-10
KR20130040952A (en) 2013-04-24
KR101485651B1 (en) 2015-01-22
WO2011163407A3 (en) 2012-04-12
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TW201224923A (en) 2012-06-16
TW201528136A (en) 2015-07-16

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