CN103036557B - The method of electronic equipment and control controlled oscillator including phaselocked loop - Google Patents

Abstract

The invention provides a kind of phaselocked loop（PLL）.The PLL includes controlled stage, and the controlled stage includes N number of memory element, wherein each memory element has the output for the output for being coupled to the controlled stage.N number of memory element coupling bunchiness, and each memory element can be configured with simulation model, and the storage signal wherein at the memory node of memory element continuously changes in response to the output signal of charge pump.Each memory element can configure in digital mode, storage value is a value from one group of predetermined value in the pattern, and for figure pattern and if the value with different storage signals, the memory element may be set to simulation model if first memory element and in rear memory element.

Description

The method of electronic equipment and control controlled oscillator including phaselocked loop

The cross reference of related application

This application claims the priority for the European Provisional Patent Application No. 11183369.5 submitted for 29th in September in 2011, The application is combined herein by quoting with its full text.

Technical field

The application is related to electronic equipment and method for phaselocked loop, and more particularly relates to control phaselocked loop Controlled oscillator frequency of oscillation electronic equipment and method.

Background technology

Phaselocked loop is commonly equipped with controlled oscillator, such as voltage controlled oscillator (VCO).VCO is coupled in feedback loop, so as to Produce the high frequency clock from low frequency reference clock.The frequency of this reference clock is relatively low, because it easily gives birth at low frequency Into different stabilizations and accurate clock signal.Figure 1 illustrates the example of the phaselocked loop according to prior art.Exist VCO, Phase frequency detector PFD, charge pump, frequency divider and compensation capacitor C1SVS including resistor R's and capacitor C2 is integrated Analogue unit.Phase frequency detector PFD is compared reference clock REFCKL phase and feedback clock signal SYSCLK phase Compared with both has identical clock frequency.Feedback clock signal SYSCLK be by PLL output clock signal PLLOUT and Divided by frequency divider DIV.If feedback clock signal SYSCLK frequency or phase are different from reference clock signal REFCKL's Phase or frequency, then charge pump CP one signal is applied on VCO so as to increase or decrease VCO output signal PLLOUT phase Position or frequency.The signal ICH sent by charge pump is the difference between reference clock REFCKL and feedback clock signal SYSCLK Function.

VCO may be embodied as ring oscillator.Ring oscillator topological structure provides a series of cascading delay stages, leads to It is often phase inverter.Output signal from last delay-level is fed back to the input of the first delay-level.By these cascades The total delay of level, including signal in system are any net anti-phase, are designed to meet persistent oscillation standard.Generally, Mei Geyan Slow level has by the variable delay of individually input control.VCO frequency of oscillation is then so as to changing by input signal control Level delay.The frequency of oscillation of ring oscillator can be tuned on a wide range of, as VCO nominal center frequency 20% to 50%.

PLL of the prior art is using the real-time clock input signal in the range of 32KHz and generating, there is tens of arrive to count The output signal PLLOUT of the frequency of hundred MHz ranges.In order to meet this extremely low incoming frequency, PLL must have very small Bandwidth, such as in 3KHz or more a small range.This small bandwidth requirement external component and a large amount of electric energy can be also consumed, especially It is in the situation of digital PLL.However, hand-held or mobile device require to reduce power consumption and external component count.

The content of the invention

It is a principal object of the present invention to provide a kind of to require less external component and than according to the PLL of prior art disappearing Consume the PLL of less electric energy.

In one aspect of the invention, a kind of electronic equipment including phaselocked loop be present.The phaselocked loop includes phase frequency Detector (PFD), the first charge pump, controlled oscillator, frequency divider and the second charge pump.Controlled stage further be present.Phase frequency The output of detector is coupled to first charge pump.The output of first charge pump is coupled to the of the controlled oscillator One control input.The output of phase frequency detector is also coupled to the input of second charge pump.The output of second charge pump It is coupled to the input of the controlled stage.The output of the controlled stage is coupled to the second control input of the controlled oscillator.Institute The output for stating controlled oscillator is coupled to the input of frequency divider.The output of frequency divider is coupled to the input of phase frequency detector.

Controlled stage includes N number of memory element.Each memory element can have the output for the output for being coupled to controlled stage.This N number of memory element preferably couples bunchiness, so that each memory element in the string is coupled to multiple formerly storage members Part and multiple in rear memory element.Term " first " refers to the position in string and referred to closer to the first memory element in string Followed by current memory element.Term refers to the position in string " rear " and referred to closer to last storage in string Element followed by current memory element.In string configures, first memory element and last memory element can not have There are two adjacent elements.First memory element can not have last memory element in first memory element and string To not have in rear memory element.First memory element and it can not be the direct neighbor member of a memory element in rear memory element Part, but they can have further away from the position of the memory element.

According to an aspect of the present invention, at least two memory elements share a storage.This means at least two Individual memory element can be alternatively coupled to storage capacitance so as to the storage capacitance charged and discharged.Each memory element Itself it can not then include storage capacitance.

In in one aspect of the invention, two memory elements for sharing storage are not intended to be the storage Direct neighbor element in element string.Storage signal can be then the voltage level of the electric capacity side (plate).In multiple storages Shared between element storage (storage capacitance) can reduce in large quantities required storage number and by This is reduced for implementing the area needed for storage capacitance, especially in integrated semiconductor circuit.

In one embodiment, it provide only the k storage (electricity that can be shared between all memory elements Hold).Parameter k then may be greater than 2 positive integer.In the described embodiment, the number of the memory element of shared memory is to deposit Store up the sum divided by k of element.In other words, each k-th of adjacent elements memory element of memory element uses same capacitor.This will The number of storage reduces the factor of the number divided by k equal to memory element.In an advantageous embodiment, storage Number can be 4 (k=4).If such as used 200 memory elements, the number of storage reduces 200 and removed With 4, that is, 50.

The voltage level in storage capacitance can be changed by adding and removing the electric charge from shared electric capacity.

Each memory element can then include transmission gate, the transmission gate couple storage inside node in memory element with Between storage.

The transmission gate of each memory element is by not being the defeated of the memory element of the direct neighbor element of the memory element Go out control.This is realized：Any switching of storage between memory element does not interfere with the activation memory element in string.

Then charged and discharged can be carried out to storage in response to the output signal of the second charge pump.Memory element In switch (transistor) control gate then the output of charge pump can be coupled to.If memory element is to be in digital mould Formula, first switch or second switch close (connection), then can go to enable by the electric discharge of shared storage capacitance and charging.

Then each memory element can be configured as taking simulation model.In the simulation mode, the storage of memory element Storage signal at node can continuously change in response to the output signal of the second charge pump.

Further, each memory element can be configured as taking figure pattern.In figure pattern, storage value is come From the value of one group of predetermined value.If first memory element and in rear memory element deposited in figure pattern and with different Signal value is stored up, then memory element can be further configured to take simulation model.

Therefore, the aspects of the invention provides a kind of half font phaselocked loop, and the phaselocked loop is by that can simulate The multiple memory elements control configured in pattern and figure pattern.In the simulation mode, the output signal of memory element can connect Change continuously.In figure pattern, output signal is fixed (being maintained at steady state value, i.e., for example high or low).Output signal is then It can be the logically high or logic low in data signal.Generally required large-scale loop filter electric capacity can be by use according to this The half font circuit arrangement of the memory element of the aspect of invention replaces.Set according to the electronics of the aspects of the invention It is standby to consume low-down electric current and do not require external component.Further, according to the integration realization of the electronic equipment of the present invention Required chip size is equally very small.

Preferably, analog loopback damping mechanism uses with reference to the half font phase-locked-loop configuration.

In one aspect of the invention, if memory element can be configured as being in number formerly and in rear memory element Word pattern and with identical storage signal value then take digital simulation.

In one embodiment, at least first memory element and/or can be in simulation model in rear memory element The direct neighbor element of memory element.

In one embodiment, at least first memory element and/or rear memory element can be from simulation model change To figure pattern and/or the direct neighbor element of the memory element that vice versa.

Further, each memory element can be configured as producing output signal, and the output signal can be deposited Store up signal, the storage signal in memory element, function.Then the output signal can be fed to controlled oscillator and be used for It is adapted to the frequency of oscillation of controlled oscillator.

Therefore, controlled oscillator can be controlled by the output signal of memory element.Because some memory elements are in numeral Pattern and other memory elements, preferably it is two memory elements of direct neighbor element simultaneously, it is controlled to shake in simulation model Device is swung to be controlled by the combination of the digital and analog outputs signal of memory element.The aspect of the present invention provides a kind of control machine Structure, the controlling organization is using data signal but is not limited to certain number of discrete rate-determining steps.Data signal is only used only To control controlled oscillator to be always constrained to the number of discrete step.The invention provides a kind of mechanism, wherein memory element certainly It is dynamic to be switched to simulation model, so as to cover all discrete step scopes.Therefore the scheme of the controlling organization is substantially unlimited 's.However, because only one or two memory element be in simulation model, control circuit provides a kind of very efficient and can The mechanism leaned on, the mechanism use considerably less part (that is, memory element).

The grid that memory node in memory element can be coupled to transistor is used to control the electricity for flowing through the transistor Stream.The electric current may then serve as the output signal of memory element.The electric current can be fed to controlled oscillator and be used for It is adapted to and changes the clock frequency of controlled oscillator.Controlled oscillator will directly be fed current to and reduce further circuit to dry The sensitivity disturbed and this be very efficient on part and part count.The output current of memory element is used as numeral and believed Number, whether instruction memory element is in the digital state of figure pattern.Further, the output current of memory element is if deposited Storage element is in the analog output signal that simulation model then continuously changes between minimum value and maximum.

In a preferred embodiment, memory element can include first switch and second switch.The first switch can To couple between the first supply voltage and the memory node of memory element.The second switch can be coupled in the second power supply electricity Between pressure and the memory node of memory element.

Then the first switch can be configured to respond to the storage signal of first memory element and be additionally in response to Switch in the level of the storage signal of rear memory element.

The second switch can be additionally configured in response to the horizontal of the storage signal in rear memory element and also ring It should switch in the level of the storage signal of first memory element.

Then the first switch can be configured as only when (formerly and after memory element) the two storage signals (memory node is coupled to the first supply voltage) is closed during less than one or more predetermined threshold levels.

Then the second switch can be configured as only when (formerly and after memory element) the two storage signals (memory node is coupled to the second supply voltage) is closed during higher than one or more predetermined threshold levels.This means storage saves Point is either pulled to the first supply voltage level (for example, VDD) or is pulled down to ground connection level.

If the level of first memory element and the storage signal in rear memory element is different, memory node both will not The second supply voltage level will not be also pulled to by being pulled to the first supply voltage.If explained with reference to other aspects of the present invention , then memory element may be at simulation model.

First switch can include two transistors and second switch can also include two transistors.The two crystal Pipe can be coupled to the memory node in rear and first memory element respectively with their control gate.

One group of predetermined value that the storage signal of memory element is switched to thereon in figure pattern can include two values.Cause This, memory element can be then binary storage element.These values can be then minimum value and maximum.Minimum value can be connect Ground and maximum can be supply voltage level.

Present invention also offers a kind of method for controlling controlled oscillator.The output clock letter of controlled oscillator can be determined Phase difference and/or difference on the frequency number between reference clock signal.The first input signal for controlled oscillator can be generated. First control signal can be used for the frequency of fine tuning controlled oscillator.Fine tuning can be the phase based on determined by Potential difference and/or difference on the frequency.Then the second input signal for controlled oscillator can be generated.Second input signal can be with Frequency for coarse tuning controlled oscillator.Equally, second input signal can be based on reference signal and controlled oscillator Output clock signal phase difference and/or difference on the frequency determine.The secondary signal can be quantization unit including a numeral Divide and simulation is non-quantized part.The numerical portion can be formed by first group of data signal and second group of data signal 's.During the analog portion can be configured as between the value of first group of data signal of instruction and the value of second group of data signal Between be worth.The value of first group of data signal can be proportional to logically high data signal number or corresponding thereto.Second group of number The value of word signal can be proportional to logically high data signal number or corresponding thereto.This aspect of the present invention provides ：It is by mould by the digital value of first group of digital signal representation and by the scope between the digital value of second group of digital signal representation Intend signal covering.

Then memory element can be controlled as optionally being coupled to the shared storage of a small group.The storage member Each k-th of adjacent elements in part string then can use same storage in the different time.

Brief description of the drawings

For the more complete understanding present invention and its advantage, reference described below is obtained in conjunction with accompanying drawing, wherein：

Fig. 1 shows the phaselocked loop according to prior art；

Fig. 2 shows the simplification circuit and block diagram of the phaselocked loop according to the present invention；

Fig. 3 shows the simplified electrical circuit diagram of controlled oscillator according to an embodiment of the invention；

Fig. 4 shows the simplified electrical circuit diagram of delay controlled stage according to an embodiment of the invention；

Fig. 5 shows the simplified electrical circuit diagram of memory element according to an embodiment of the invention；

Fig. 6 shows the simplification waveform of the charging principle of shared capacitor according to an embodiment of the invention；

Fig. 7 shows the charge pump for being used for memory element according to an embodiment of the invention；

Fig. 8 is shown is used for the charge pump for damping phaselocked loop according to an embodiment of the invention；And

Fig. 9 shows the simplified electrical circuit diagram of the configuration according to an embodiment of the invention for compensation deals difference.

Embodiment

Fig. 2 shows the electronic equipment 1 of many aspects according to the present invention, and the electronic equipment includes phase-locked loop pll 2. The PLL 2 includes phase frequency detector PFD, and it exports the input for being coupled to the first charge pump CP1.The first charge pump CP1 Output be coupled to controlled oscillator VCO input and tank capacitors C1 side.Tank capacitors C1 another side joint Ground is coupled to supply voltage level.Controlled oscillator VCO output OUTVCO is coupled to level displacement shifter LS input simultaneously And it is PLL output signal PLLOUT.Controlled oscillator is voltage controlled oscillator VCO in the present embodiment.Output signal PLLOUT couplings Connection returns to frequency divider DIV.Output signal PLLOUT clock frequency is divided and provides clock signal by frequency divider DIV SYSCLK.The signal SYSCLK is fed back to phase frequency detector PFD input.Phase frequency detector PFD another input Receive reference clock signal REFCLK.

Further, according to many aspects of the present invention, the second charge pump CP2 and delay controlled stage DCONT be present.Institute Stating the second charge pump CP2 can also couple to receive phase frequency detector PFD output.The output SHN of the second charge pump CP2 Delay controlled stage DCONT input is coupled to LNG.These inputs for postponing controlled stage DCONT are FS and FL.FS refers to accelerate (increase VCO clock signal frequency) and FL refer to slow down (reduce VCO clock signal frequency).Postpone controlled stage to provide It is fed to VCO FSUP output signal D.

Reference clock REFCLK can be the input clock of the real-time clock from electronic equipment 1.Reference clock signal REFCLK frequency can be in the range of 32KHz.This low incoming frequency usually requires that PLL 2 loop bandwidth in 1KHz To 3KHz.Reference clock signal REFCLK is directly fed into phase frequency detector PFD.Phase frequency detector PFD can be with Conventional phase frequency detector, this conventional phase frequency detector be configured as by reference clock signal REFCLK phase with it is anti- Feedback clock signal SYSCLK phase is compared.Phase frequency detector is believed upwards based on detected phase/frequency difference generation Number UP and down signal DN.The two outputs UP and DN is fed to the first charge pump CP1 and the second charge pump CP2.

If DVCO is not to be used for producing full pendulum output clock signal OUTVCO, the level at DVCO output Shifter LS is only optional.The output (or, in alternative embodiments, DVCO output) of level displacement shifter is then PLL 2 Feedback and output signal PLLOUT.Frequency divider DIV defines clock multiplexing factor.The output of frequency divider is by as signal SYSCLK It is fed back into phase frequency detector PFD input.

Delay controlled stage DCONT output signal D is preferably analog signal.In embodiment, output signal D can be Electric current.Delay controlled stage DCONT also generates data signal A<1:N>.A<1:N>Representative is stored in delay controlled stage DCONT Content/value of signal.These digit order numbers are fed back to the first charge pump CP1 and the second charge pump CP2.They are used to compensate by temperature Difference caused by degree, supply voltage or production range.

Fig. 3 shows the simplified electrical circuit diagram of the embodiment for the VCO that can be used according to an embodiment of the invention in phaselocked loop. VCO includes five delay-level INV1, INV2, INV3, INV4 and INV5.Delay-level INV5 output OUTVCO is coupled to VCO The first delay-level INV1 input.VCO is implemented as ring oscillator.All grades of INV1 to INV5 series connection couple.Last Level INV5 provides first order INV1 feedback.Delay-level INV1 to INV5 can all be embodied as Fig. 3 relatively lower part.Cause This, delay-level INV1 to INV5 is configured as the phase inverter for including PMOS transistor PMOSI and nmos pass transistor NMOSI.PMOS Transistor PMOSI is used as phase inverter together with generally being coupled with nmos pass transistor NMOSI raceway groove.PMOS transistor PMOSI and Nmos pass transistor NMOSI control gate is coupled to receive the input signal from previous stage.The output signal OUT of phase inverter is then It is coupled to next stage.VCO further comprises PMOS transistor P1, and the transistor defines the grid for simulating damping.Stream Electric current through PMOS transistor P1 combines the electric current of the current definition oscillator for flowing through node VSUP received.VSUP couple for Receive delay-level DCONT output signal.Delay-level DCONT output is signal D.PMOS transistor P1 connects at control gate Receive input signal PROP.The first input signal that the input signal PROP is VCO is used in response to the first electric charge shown in Fig. 2 Pump CP1 output and define simulation damping (fine tuning of frequency of oscillation).VCO VSUP the second input is coupled to delay control Level DCONT processed output.This is used to provide coarse tuning.

Fig. 4 illustrates in greater detail delay controlled stage DCONT.Delay-level includes N number of memory element S1 to SN.N can be 200.Each memory element has input L, input H, input L2, input H2, input FS and input FL, input INITB, output OUT and output CC and output INH.

The output INH of memory element is coupled in the input L of the rear memory element and input H of first memory element.

Further, output INH provides signal A<1:N>, the signal be fed back to charge pump CP1 shown in Fig. 2 and CP2。

Signal B<1:N>For memory element to be initialized as into specific initial value.

Signal INITB is used to initialize memory element.Memory element S1 to SN couples bunchiness.First memory element S1 does not have There is first memory element.Last memory element S1 is not in rear memory element.Other memory elements Si (S2 to SN-1) is total It is formerly and in rear memory element with corresponding.For example, memory element S2 has first memory element S1 and in rear storage member Part S3 to SN.Memory element S3 has in rear memory element S4 to SN and first memory element S1 and S2.

More generally, memory element Si have first memory element S1 to Si-1 and in rear memory element Si+1 extremely SN.Memory element Si function and content be then by be stored in one or more of first memory element S1 to Si-1 one Individual or multiple values and being stored in one or more define in one or more of rear memory element Si+1 to SN value.

Determine that the memory element of operator scheme and memory element Si content can not be Si direct neighbor element, but In one or more farther string middle-range Si formerly and in rear memory element.Therefore, memory element Si content and operator scheme It is then as defined in the value for being stored in first memory element Si-K1 and being stored in rear memory element Si+K2.K1 and K2 are then It may be greater than 1 positive integer.

All single memory element S1 to SN are coupled at node D.This node D is the group for postponing controlled stage DCONT Close output signal.Further, together with input pin ML equally couples with FS and for all memory element S1 to SN For be identical.This is equally applicable to MH and FL.Input pin INITB is equally coupled together at node INIT.Signal INIT can be used for initializing all memory element S1 to SN immediately.

For memory element S2, input H and L can have 4 possible values.Or it is low-low, low-high, high-low or Gao-height.

Further there are k=4 shared storage C1, C2, C3 and C4.Be not in each memory element S1 into SN Storage is provided, but in these memory elements S1 to these shared capacitors between SN.Can by memory element according to Specific order is each charged and discharged in storage C1 to C4.For example, memory element S3 is received from storage Element S2 input signal L, the signal L2 from memory element S1, the signal H from memory element S4 and from storage member Part S5 signal H2.Storage C3 is coupled to memory element S3 by signal L2 and H2 control.Signal L and H be used for control by The charging and discharging for the storage C3 that memory element S3 is performed.

In the first scene, it is understood that there may be the continuous UP signals from phase frequency detector PFD (as shown in Figure 2).Institute State in scene, the charging of memory element is since memory element S1 and continuously with memory element S2, S3, S4 until storage member Part Si continuously continues.Memory element S1 output CC is coupled to capacitor C1 side.During initialization (upper electricity), own Memory element S1 to SN be initialized to the voltage level corresponding with logic LOW.If the voltage on storage C1 The half that level reaches such as supply voltage level is VDD/2, then it is charged by memory element S1 output CC.Signal L2 Change from LOW to HIGH and be used for memory element S3, and signal L is also used for memory element S2 using logic level HIGH.This In situation, due to first power-on sequence, signal H2 is to be in logic LOW for memory element S3.This enables storage member Part S3 two internal transmission doors (shown in Fig. 5) (that is, transmission gate is opened=coupled).Storage C3 is then at output CC It is coupled to memory element S3 output node OUT (=memory node SNOD).

As described above, during the operation of the PLL according to the present invention, what two memory elements always activated, and it is remaining Memory element then be not activation.During initialization, memory element S1 is activation and signal L and L2 are coupled to power supply electricity Voltage levels VDD.Then memory element S2 is activated and it exports CC and is coupled to C2.C1 then charged by memory element S1 and Voltage level at storage inside node SNOD rises.Memory element S2 memory node SNOD is being charged to supply voltage water After flat half is VDD/2, it is coupled to memory element S3 memory element S2 signal L, is coupled to memory element S4 storage Element S2 signal L2 and it is coupled to memory element S1 memory element S2 signal L and is changed into logic HIGH.This provide with The lower fact：Memory element S3 activate and storage C4 be coupled to by exporting CC memory element S4 output node (or Memory node SNOD).Then memory element S1 is not activated and it exports OUT and is digitally wired to VDD.

Because memory element S1 output OUT is wired to VDD, storage C1 can with and for example, if can when needing To be used by memory element S5.In this case, memory element S2 and S3 is activated and remaining memory element does not activate.Under One step is that storage C3 is charged by memory element S3.Memory element S3 output node OUT (or memory node SNOD) One reaches the half i.e. VDD/2 of supply voltage level, and memory element S4 is just activated.Then memory element S2 output OUT connects Line is coupled to memory element S5 output to supply voltage level VDD and storage C1.Storage C1 is by depositing Storage element S1 is charged to supply voltage level VDD.If then storage C1 is coupled to such as memory element S5, store Capacitor C1 discharges into ground connection (logic LOW), because memory element S5 output OUT is digitally wired to logic LOW.This is enabled Storage C1 and make it can be used for charging, thus avoid any voltage glitch of the input of voltage controlled oscillator VCO. Voltage glitch can occur because of storage C1 any precharge.Memory element S4 output OUT (output signals CC) half i.e. a VDD/2 for reaching supply voltage level, memory element S5 is just activated and memory element S3 output OUT Supply voltage level VDD is wired to, thus deactivates memory element S3.Storage C3 is then available.Memory element S5's Signal L2 mono- becomes HIGH (S5 L2 is coupled to S7), and shared storage C3 is just coupled to memory element S7, so as to be shared Storage C3 charges.Because what two memory elements always activated, it is possible to which activation is from a frequency to higher frequency Smooth transition.This smooth frequency transition prevents any frequency spurs and thus prevent any not wishing of PLL outputs The shake of prestige.

For the continuous DOWN signals from phase frequency detector PFD to the second charge pump CP2, continuous SLOW pulses (signal LNG) is fed to the switching transistor (N2 shown in Fig. 5) in memory element.In this case, deposited from the rightmost side Store up the switching that element SN to leftmost side memory element S1 performs shared capacitor C1 to C4.For example, capacitor C3 is from memory element S7 is switched to memory element S3.Storage C2 is switched to memory element S2 from memory element S6.Storage C1 is from depositing Storage element S5 is switched to memory element S1.

In a kind of scene, wherein in PLL phase locking process in response to first UP signals and by memory element S1 extremely S5 charges, might as well be it is further assumed that such as memory element S5 and S6 is the memory element activated.At the rising edge of DOWN signals, Memory element S5 and S6 start shared capacitor C1 and C2 electric discharge corresponding to it.Memory element S5 output signal INH reaches The half of supply voltage level is VDD/2, and the signal H2 that memory element S3 is fed to from memory element S5 becomes LOW.Further, Memory element S4 signal H2 change LOW are fed to from memory element S5 and memory element S6 letter is fed to from memory element S5 Number H2 becomes LOW.Therefore, memory element S6 output INH is wired to logic LOW.Because signal H and L are logic HIGH (storage members Part S3 is in supply voltage level VDD), so memory element S4 is activated.Because signal L2 and R2 are logic HIGH, storage member Part S3 is coupled to shared storage C3 so as to which capacitor C3 is discharged.Further, capacitor C2 (counts from memory element S6 It is wired to logic LOW word) go to couple and so if can be used for memory element S2 when needing.Coupling before storage C3 Memory element S7 is linked to, the output INH of the memory element is wired to logic LOW now.Therefore, the voltage at capacitor C3 both ends Level is also in logic LOW.However, when storage C3 is coupled to memory element S3 and memory element S3 output INH When being wired to logic HIGH, storage C3 is charged to supply voltage level VDD within the very short time.The present invention's It is very short for period for being charged to storage (being C3 in this example) in embodiment, so as to by storage C3 prepares for that can be configured as capacitor discharge in rear memory element.Memory element S3 is from memory element S4's Logic LOW is reached at signal H, memory element S3 is activated and capacitor C3 discharged so that the frequency required for realizing changes Become.Therefore, sharing principle by using the electric capacity of many aspects according to the present invention realizes memory element charging and discharging The fine tuning of the frequency of voltage controlled oscillator VCO.The frequency rank of fully charged or electric discharge memory element storage voltage controlled oscillator The simulation fine tuning of the digital information of jump and the memory element that activates to the frequency required for providing.

Fig. 5 illustrates in greater detail memory element Si.Memory node SNOD is coupled to PMOS transistor P4 control gate. PMOS transistor P4 source class is coupled to supply voltage level DVDD.PMOS transistor P4 coupled drain is to output node D.Deposit Storage node SNOD is also coupled to first switch SW1 and second switch SW2.

First switch SW1 is configured to respond to signal L and H and memory node is coupled into the first supply voltage level DVDD.Second switch SW2 is configured to respond to signal L and H and memory node SNOD is coupled into the second supply voltage level DVSS.Signal L and H are from first and in rear memory element input signal as shown in Figure 4.Memory node SNOD is also coupled To PMOS transistor P4 and nmos pass transistor N5 grid.PMOS transistor P4 and nmos pass transistor N5 form phase inverter INV1, the phase inverter are used for the storage signal on buffer memory node SNOD and its is anti-phase.So or in phase inverter INV1 Output be under output signal INH the storage content that memory element S1 is provided in the form of data signal.Deposited to initialize Element Si is stored up, using signal INITB and is coupled to PMOS transistor P6 control gate.If INITB is low, store Node SNOD is coupled to DVDD and is pulled to the first supply voltage level DVDD.

Memory element Si can be configured in both of which.The first pattern is properly termed as simulation model.Second of pattern It is properly termed as figure pattern.If memory node SNOD is coupled to the first supply voltage level DVDD by switch SW2 or switch SW1 Or the second supply voltage level DVSS, then memory element Si be in figure pattern.Therefore, the voltage level at node SNOD can To be DVSS or DVDD.This is considered the output of two different digital values (high and low).If however, SW1 and SW2 It is not to close (coupling), then the voltage level at memory node SNOD can change in response to signal MH and ML.These Signal is received from the second charge pump CP2.If such as output signal H is low (threshold voltage for being less than transistor P2) and signal MH is also low, then electric current can flow to memory node SNOD from DVDD.However, if signal L is high, if signal ML is also high In N2 threshold voltage level, then electric current can flow to the second supply voltage level DVSS from memory node SNOD.

Signal H is received from rear memory element Si+1.Signal L is received from first memory element Si-1.As shown in the figure, Signal INH is the anti-phase storage signal at memory node SNOD.(it is coupled to if signal H and L are low levels less than them Corresponding transistor threshold value), then PMOS transistor P2 and PMOS transistor P3 be enabled and nmos pass transistor N1 and Nmos pass transistor N3 goes to enable.Therefore, capacitor terminal OUT is pulled to level high DVDD.If H and L are high level (threshold voltage level for being higher or lower than transistor), then capacitor terminal OUT or memory node SNOD are pulled to the second power supply Voltage level DVSS.Voltage one at memory node SNOD is anti-phase more than being formed by PMOS transistor P5 and nmos pass transistor N5 Device INV1 threshold value, the level at node INH just uprises from high step-down or from low, depending on the voltage at memory node SNOD It is raised and lowered.

Shared capacitor (such as C1 as shown in Figure 4 to C4) can be coupled to memory node optionally through transmission gate SNOD (=OUT).Two the transmission gates TR1 and TR2 that series connection couples between memory node SNOD and output node CC be present.

If signal H and L are low, shared capacitor is pulled to level high.If signal H and L are low and high, Then share capacitor and keep its voltage.If signal H and L is pulled down to low level in high level, condenser voltage.During beginning (upper electricity, initialization), all memory element S1 to SN are initialized to high level.This means be coupled to memory node SNOD's PMOS transistor P6 does not provide any electric current.

Therefore VCO does not receive any electric current for carrying out self-dalay control gate DCONT.Therefore, VCO is under minimum frequency of oscillation Vibration.In order to meet reference input clock REFCLK required frequency and phase, phase frequency detector PFD and ensuing electricity Lotus pump CP2 sends signal so as to increase VCO frequency.

Phase frequency detector generates pulse UP at output node.In response to these UP signals, the second charge pump CP2 is in node Reference voltage is generated at SHN.The node SHN is coupled to the input FS of delay control gate.

Memory element S1 is coupled to ML and attempts memory node to discharge and thus by shared capacitor (not shown) Electric discharge.Memory element S2 to SN has two terminals H and L under low level.Therefore, any memory element S2 is coupled to as far as possible Corresponding storage to SN is pulled to high level by transistor P2 and P3.However, memory element S1 memory node (phase inverter INV1 threshold voltage level can be the threshold voltage that storage signal one at SNOD drops to less than phase inverter INV1 First supply voltage level DVDD half (DVDD/2)), memory element S1 signal INH just uprises from low.Memory element S1 This of signal INH the memory node SNOD in the memory element S2 when transistor P3 is closed is moved to from the low change uprised First voltage level (height) goes to enable.Therefore, memory element S1 and S2 two shared capacitors can be coupled to by by phase frequency The pulse up and down (signal UP and DN) that detector PFD is sent influences.The voltage at node SNOD in memory element S2 Phase inverter INV1 of the level one more than memory element S2 threshold voltage level, memory element S3 are just activated.Memory element S3 It is activated, memory element S1 input signal H receives high level and memory element S1 transistor N1 and N3 are activated.Storage Level at node SNOD is pulled down to the second supply voltage level DVSS (ground connection) now.This means always have two storages Actuating elements are used for analog tuner and every other memory element is in figure pattern, it means that they are in response to its phase The value of adjacent element and be in high level or low level.

The two transmission gates TR1, TR2 include by signal L2 and H2 control corresponding PMOS and nmos pass transistor P7, P8, N6 and N7.Transmission gate TR1, TR2 be used for by output node be coupled to from node CC (and be thus coupled to memory node SNOD or Go to couple from it) it is coupled to corresponding shared capacitor or goes to couple from it.Specifically, if memory element un-activation and Not close to the memory element of activation, then exporting OUT/ memory nodes SNOD should go to couple from corresponding capacitor, so as to other Memory element can use shared capacitor.Control signal L2 and H2 are to be never direct neighbor element but be proximate to memory element What the memory element of the adjacent elements of the right side of (the second adjacent elements) and the direct neighbor element in left side received.In order to control this A little transmission gates, H2 and L2 complementary signal are generated by phase inverter INV, as shown in Fig. 5 upper right side.

Fig. 6 shows the waveform related to the charging process of the capacitor of the embodiment shown in Fig. 4.In the presence of four figure (a), (b)、(c)、(d).First figure (a) is relevant with the voltage at capacitor C4 both ends.Second figure (b) and the electricity at capacitor C3 both ends Pass is pressed with, the 3rd figure is relevant with the voltage drop at capacitor C2 both ends, and the 4th figure and the voltage drop at capacitor C1 both ends It is relevant.Therefore, these voltage drops represent the voltage at the corresponding memory node for the memory element for being coupled to shared capacitor.Ginseng It is relevant with memory element S1 to S8 to examine signal S1 to S8.Since being schemed (d), it can be seen that memory element S1 enters to capacitor C1 Row charging starts.Therefore, voltage VC1 smoothly rises, until reaching the only about half of of supply voltage level.In supply voltage water At flat only about half of VDD/2, memory element S2 (memory element S1 in rear adjacent elements) starts to give capacitor C2 chargings.Cause This, the voltage level VC2 at capacitor C2 both ends smoothly rises, until reaching the only about half of VDD/2 of supply voltage level. VC2 reaches VDD/2, and the 3rd memory element (memory element S2 in rear adjacent elements) begins to give capacitor C3 chargings.If Capacitor C3 voltage VC3 reaches VDD/2, then the 4th memory element S4 (memory element S3 in rear adjacent elements) starts to electricity Container C4 charges.However, memory element S3 starts to reach to capacitor C3 chargings and voltage level VC3 mono-, capacitor C1 is just Electric discharge.Then capacitor C1 can be used by memory element S5.Capacitor C3 can be used by memory element S6, and capacitor C3 can To be used by memory element S7 and capacitor C4 can be used by memory element S8 so as in response to from phase frequency detector PFD UP signals and smoothly increase frequency.

Fig. 7 shows the simplified electrical circuit diagram of the charge pump according to an embodiment of the invention for memory element Si.Fig. 7 shows The possible implementation of the charge pump CP2 shown in Fig. 2 is gone out.Received from phase frequency detector PFD input signal UP and DN couples It is coupled to nmos pass transistor N3 and N4 grid with answering.These transistors act as switches.PMOS transistor P1 and nmos pass transistor N2 is formd by signal SHN and LNG and inside the memory element with PMOS transistor P1 and nmos pass transistor N2 Two current mirrors.PMOS transistor P1 and P2 and nmos pass transistor N3 and N4 and nmos pass transistor N1 and N2 match simultaneously And should have identical length-width ratio and other characteristics.This means the electric current for flowing through two branch roads will be identical.This A little level SR1 and SR2 are made up of multiple resistors, and this is illustrated in more detail in fig.9.These grade of SR1 and SR2, which is used to adjust, to flow Electric current through these branch roads, to carry out process, temperature and voltage variation (PVT compensation) compensation.

Fig. 8 shows the simplified electrical circuit diagram of the embodiment of the first charge pump CP1 shown in Fig. 2.Charge pump is also received and come from The signal up and down (DOWN, UP, UPB and DOWNB) of phase frequency detector.Also exist be similar to Fig. 7 shown in level SR1 and SR2 level SR1.This grade of SR2 is used to define the electric current for flowing through nmos pass transistor N1.Nmos pass transistor N1 electric current is flowed through by mirror As arriving nmos pass transistor N2 and N3.Resistor R1 and R2 form frequency divider, and the frequency divider generates the one of supply voltage level Half AVDD.If signal DOWN uprises from low, PMOS transistor P1 start by current mirror to so that provide current to node ICH PMOS transistor P4.As shown in Fig. 2 electric capacity is coupled to node ICH.If signal UP is uprised, nmos pass transistor N7 is closed Close and the electric current from node ICH is sunk.In the normal course of operation of phaselocked loop, it will be come from by then supplying or sinking It is coupled to caused by the phase frequency detector of the electric current of ICH capacitor pulse train up and down.This will so that for each to Upper or down pulse provides voltage jump or voltage drop.If however, without any pulse up or down, resistance frequency divider R1 and R2 moves the voltage at ICH to AVDD/2.

Fig. 9 shows grade SR1 and SR2 simplified electrical circuit diagram.There are multiple resistor R1 to RN series connection to couple.Each resistor R1 to RN is coupled to NMOSN by corresponding nmos pass transistor NMOS1.The impedance of these resistors in series and nmos pass transistor is Reduced by opening nmos pass transistor NMOS1 to NMOSN.If opened without transistor, impedance is maximum, and such as All transistors of fruit are opened, then impedance is minimum value.This is to be used to adjust electric current so as to be deteriorated to process, temperature or supply voltage Compensate.

Therefore, the present invention is described by reference to some preferred embodiments, it should be noted that disclosed embodiment is to say Bright property rather than actual limitation, and widely change in foregoing disclosure, change, change and replace and can envision, In some cases, can be using some features of the present invention and without using other corresponding functions.Therefore, extensively and with model of the present invention Enclose consistent mode and explain that appended claims are appropriate.

Claims (13)

1. a kind of electronic equipment, including：Phase-locked loop pll, the phase-locked loop pll include phase frequency detector PFD, the first charge pump CP1, controlled oscillator VCO, frequency divider DIV, the second charge pump CP2 and controlled stage DCONT, wherein the phase frequency detector PFD output is coupled to the first charge pump CP1 and the output of the first charge pump CP1 is coupled to the controlled oscillation Device VCO the first control input, the output of the phase frequency detector PFD are also coupled to the defeated of the second charge pump CP2 Enter, the output of the second charge pump CP2 is coupled to the input of the controlled stage DCONT, the output coupling of the controlled stage DCONT The second control input of the controlled oscillator VCO is linked to, the output of the controlled oscillator VCO is coupled to the frequency divider DIV input, the output of the frequency divider DIV are coupled to the input of the phase frequency detector PFD, the controlled stage DCONT bags Include N number of memory element S1 ..., SN, wherein each memory element have be coupled to the controlled stage DCONT output output, N number of memory element is coupled into a string so that except first memory element S1 and last storage in the string Each memory element Si outside element SN is coupled to first memory element Si-K1 and in rear memory element Si+K2, and often Individual memory element can be configured with simulation model, wherein the storage signal at the memory node of the memory element is in response to described Two charge pump CP2 output signal and continuously change, and each memory element can configure in digital mode, and wherein storage value is One from one group of predetermined value value and if formerly memory element and for figure pattern and there is institute in rear memory element The different values of storage signal are stated, then the memory element is further configured to use simulation model, and wherein at least two Individual memory element shares the storage capacitance for storing the storage signal at the memory node.

2. electronic equipment according to claim 1, wherein at least two memory element of shared storage exists It is not direct neighbor in the string of the memory element.

3. electronic equipment according to claim 1, which provide the k storage electricity shared between all memory elements Appearance and wherein k are greater than 2 integer.

4. electronic equipment according to claim 3, wherein k are equal to 4.

5. the electronic equipment according to any one of the claims, if wherein the formerly memory element and it is described Memory element is figure pattern and has the identical value of the storage signal afterwards, then the memory element is further configured To use the figure pattern.

6. electronic equipment according to claim 1, wherein the storage letter of the memory element in the figure pattern Number two values be minimum value and maximum.

7. electronic equipment according to claim 1, two of which or more adjacent memory element Si, Si+1 are to locate simultaneously In simulation model.

8. electronic equipment according to claim 1, wherein each memory element includes transmission gate, the transmission gate couples Between the memory node and storage.

9. electronic equipment according to claim 8, wherein the transmission gate of each memory element is by first not with the storage The output control of the memory element of part direct neighbor.

10. electronic equipment according to claim 1, wherein each memory element is configured as producing output signal D, it is described Output signal D be it is described storage signal function and be fed to the controlled oscillator VCO for be adapted to it is described controlled Oscillator VCO frequency of oscillation.

11. electronic equipment according to claim 1, wherein the memory node of each memory element is coupled to the grid of transistor Pole is used to control the electric current for flowing through the transistor, and the electric current is used as the output signal D of the memory element and coupled To the second input of the controlled oscillator VCO.

12. electronic equipment according to claim 1, wherein memory element include first switch and second switch, and its Described in first switch couple between the first supply voltage and the memory node and the second switch is coupled second Between supply voltage and the memory node, and the first switch is configured to respond to the storage of the formerly memory element Signal and described switch in the storage signal of rear memory element and the second switch is configured to respond to described deposit after Store up the storage signal of element and the storage signal of the first memory element and switch, so that the first switch is only when two Individual storage signal closes when being below threshold level, that is, connects, and the second switch only stores signal when two and is all higher than Close, that is, connect during threshold level.

13. a kind of method for controlling controlled oscillator, the described method comprises the following steps：Determine the output of the controlled oscillator Phase difference and/or difference on the frequency between clock signal and reference clock signal, generate the first input letter of the controlled oscillator Number be used for based on described in identified phase difference and/or difference on the frequency fine tuning controlled oscillator frequency, generation it is described controlled Second input signal of oscillator is used for phase difference and/or frequency coarse tuning based on determined by, wherein the second input letter Number include first group of data signal, second group of data signal and instruction first group of data signal and described second group numeral The analog signal of median between signal.