CN103036539A - Signal generator capable of generating a plurality of ultra narrow pulses and achieving method thereof - Google Patents
Signal generator capable of generating a plurality of ultra narrow pulses and achieving method thereof Download PDFInfo
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Abstract
The invention discloses a signal generator capable of generating a plurality of ultra narrow pulses and an achieving method thereof. The signal generator comprises a field programmable gate array (FPGA), at least one delay line device, a plurality of pulse-width modulation (PWM) generators, a multi-way high speed or logic block and a linear driving device. The first output end of the FPGA is connected with the input end of a first PWM generator, other output ends of the FPGA are respectively connected with the input end of the delay line device, the output end of the delay line device is respectively connected with the input ends of other PWM generators except the first PWM generator, the output end of each PWM generator is respectively connected with the input end of the multi-way high speed or logic block in one-to-one correspondence mode, and the output end of the multi-way high speed or logic block is connected with the linear driving device. The signal generator has the advantages being capable of continuously generating the plurality of ultra narrow pulses by adopting the delay line device, the PWM generators and the multi-way high speed or logic block and being capable of resolving contradiction between power increase and non linearity in temperature measurement of a data transmission service (DTS) system to achieve the aim of long distance measurement by driving a multi narrow pulse laser light source in the DTS system.
Description
Technical field
The present invention relates to the Fiber Optic Pyrometer field, particularly the generating technique of a plurality of super burst pulses of the LASER Light Source in the Fiber Optic Pyrometer field.
Background technology
Temperature-measuring system of distributed fibers (hereinafter referred to as the DTS system) is a kind of temperature measurement system that develops based on OTDR and Raman scattering principle, and its temperature sensor is optical fiber.DTS system composition generally comprises high power pulse laser light source, optical fibre wavelength-division multiplex coupler, sensing optic cable, photodetector, signal amplification module, data acquisition module and system host (PC or industrial computer).The DTS system is through years of researches and development, the at present very ripe and in a large number listing of the system of the short-distance and medium-distance length of measuring distance (but refer to).But the system of long distance for example can measure 12km and still be in development to the system of 25km, at present, and the DTS system that also has on the market some can measure long distance, but it is with high costs, has limited the universal of this system.
Experiment shows, when high power laser transmits in optical fiber, when power is higher than certain threshold value, easily produces spontaneous radiation at about tens kms; And for DTS, when spontaneous radiation acquired a certain degree, it is non-linear that system produces, and at this moment system just can't demodulate temperature information.And if reduce light source power, can eliminate non-linear, but according to the ODTR principle, because the loss of light in optical cable, distance has increased, and the Raman scattering luminous power of optical cable end will become lower, transmit the light path of returning from tail end simultaneously longer, loss is also larger, a little less than luminous power became very when this had caused scattered light to get back to photodetector, is difficult for surveying.---measuring distance increases, but produces non-linearly, and system can't demodulate temperature information and light source power reduction---is eliminate non-linear so this has just produced the light source power increase, but the contradiction that measuring distance shortens.Therefore, the DTS system of present short-distance and medium-distance, the power that can not increase simply its light source reaches the increase of measuring distance.
At present in the DTS system, generally be the narrow-pulse laser light source as the high power pulse laser light source of core component.Traditional narrow-pulse laser light source is the single-pulse laser light source, its pulse driving circuit is relatively simple, can only produce periodic pulse and drive signal, thereby this narrow-pulse laser light source can only produce the pulse laser of the certain pulse duration with certain repetition rate.But, based on the DTS system of this single-pulse laser light source, can only satisfy the measurement requirement of short-distance and medium-distance, can't satisfy the measurement of long distance and use.
Summary of the invention
In order to solve problems of the prior art, the invention provides a kind of signal generator that produces a plurality of super burst pulses, described signal generator can be used as a kind of driving of many narrow-pulse lasers light source, DTS system based on this many narrow-pulse lasers light source, increased power and nonlinear contradiction in the time of can solving thermometric reach the purpose of long range measurements.
In order to achieve the above object, the present invention adopts a kind of signal generator that produces a plurality of super burst pulses, comprise FPGA, at least one delay line device, a plurality of PWM generator, multipath high-speed or logical block and line drive spare, it is characterized in that: first output of FPGA connects the input of first PWM generator, other outputs of FPGA connect respectively the input of delay line device, the output of delay line device connects respectively the input of other PWM generator except first PWM generator, connect one to one the respectively input of multipath high-speed or logical block of the output of each PWM generator, the output connecting line driving element of multipath high-speed or logical block.
Described FPGA is connected with host computer through communication interface, and its function is to produce the triggering signal that multichannel has identical repetition rate, and the repetition rate of triggering signal can be by the communication interface setting of upper computer software by FPGA.
Described communication interface adopts the RS232 interface.
Described delay line device, its function are that the triggering signal of input is delayed time, and namely are input to the triggering signal of delay line device after the output of delay line device, and the output signal ratio input signal has been delayed time the regular hour.
Described delay line device can be by the communication interface setting of upper computer software by FPGA to the delay time of output signal.
Further, the delay time of each road triggering signal after through delay line device arranges difference, and the unit of delay time is generally take the narrow pulse width of final system output as unit.
Further, described delay line device is DS1021S.
Described PWM generator, its function is when triggering signal be arranged (generally is the rising edge signal, pulsewidth is not limit) when inputting, this device produces a narrow pulse signal, the frequency of this narrow pulse signal is identical with the frequency of triggering signal, and pulse duration can be passed through by upper computer software the communication interface setting of FPGA, so pulse duration is adjustable.
Further, described PWM generator is DS1023S, and the I of the pulsewidth of the narrow pulse signal that this device can produce reaches 5ns, belongs to super burst pulse type; And the minimum adjustable stepping of this device is 0.25ns.
Described multipath high-speed or logical block, its function are that the multiple signals of input are done exclusive disjunction (a kind of logical operation), and its output is exactly the exclusive disjunction output of multichannel input signal.
Further, described multipath high-speed or logical block adopt basic 2 inputs at a high speed or door is realized by cascade system.
Described line drive spare 5, its function are to input driving force more weak pulse signal, export after strengthening its driving force, improve simultaneously the rising edge of signal, thus the more perfect pulse signal of acquisition.
The invention discloses a kind of implementation method that produces the signal generator of a plurality of super burst pulses, comprise the steps:
The first step: FPGA produces multichannel and has the triggering signal of same frequency, first via triggering signal is directly inputted PWM generator and is exported the narrow pulse signal that the first via does not have time-delay by FPGA, all the other each road triggering signals are inputted respectively with it corresponding delay line device, are delayed time respectively by the delay line device and export after the different time;
Second step: each different road triggering signal of delay time is inputted respectively PWM generator, becomes the different narrow pulse signal of delay time after PWM generator output;
The 3rd step: two inputs that the narrow pulse signal that the described first via not have the narrow pulse signal and the second tunnel of time-delay to delay time is inputted respectively multipath high-speed or logical block carry out exclusive disjunction; Two inputs that the narrow pulse signal of Third Road time-delay and the narrow pulse signal of the four tunnel time-delay are inputted respectively multipath high-speed or logical block carry out exclusive disjunction; By that analogy, the result of every two-way exclusive disjunction is proceeded exclusive disjunction more as stated above, until finally only have the output of one road signal, namely export the one tunnel many narrow pulse signals with a plurality of burst pulses;
The 4th step: above-mentioned many narrow pulse signals input line driving element, then export more perfect many narrow pulse signals that a driving force strengthens, rising edge improves.
Beneficial effect of the present invention is: adopt delay line device, PWM generator and multipath high-speed or logical block, each cycle that can realize having certain repetition rate can produce the signal generator of a plurality of super burst pulses continuously, the duty ratio form flexibly changing of a plurality of pulses, thereby the convenient signal of realizing various patterns; The sort signal generator can be used to drive a kind of many narrow-pulse lasers light source, and this many narrow-pulse lasers light source is as the LASER Light Source of DTS system, and increased power and nonlinear contradiction in the time of can solving DTS system thermometric reach the purpose of long range measurements.
Description of drawings
Fig. 1 is structural representation of the present invention;
Fig. 2 is the structural representation of example 1 of the present invention;
The burst pulse sequential chart of Fig. 3 embodiment of the invention 1.
The implementation formula
Further specify the specific embodiment of the present invention below in conjunction with accompanying drawing.
As shown in Figure 1: a kind of signal generator that produces a plurality of super burst pulses, comprise FPGA1, delay line device 2, PWM generator 3, multipath high-speed or logical block 4 and line drive spare 5, first output of FPGA1 connects the input of first PWM generator 3, other outputs of FPGA1 connect respectively the input of delay line device 2, the output of delay line device 2 connects respectively the input of other PWM generator 3 except first PWM generator 3, connect one to one the respectively input of multipath high-speed or logical block 4 of the output of each PWM generator 3, the output connecting line driving element 5 of multipath high-speed or logical block 4.
Described FPGA1 is connected with host computer through communication interface, produces simultaneously the triggering signal that N road (N 〉=2) has identical repetition rate, and the repetition rate of triggering signal can be by the communication interface setting of upper computer software by FPGA;
Described communication interface adopts the RS232 interface.
Described delay line device 2, its function are that the triggering signal of input is delayed time, and delay time is by the communication interface setting of upper computer software by FPGA;
Further, the delay time of each road triggering signal after through delay line device 2 arranges difference, and the unit of delay time is generally take the narrow pulse width of final system output as unit; For example system's output narrow pulse width is 5ns, and delay time can be set to the multiple of 5ns so, such as 5ns, and 10ns, 15ns etc.
Further, described delay line device 2 is DS1021S.
Described PWM generator 3, its function is when triggering signal be arranged (generally is the rising edge signal, pulsewidth is not limit) when inputting, this device produces a narrow pulse signal, the frequency of this narrow pulse signal is identical with the frequency of triggering signal, and pulse duration can be passed through by upper computer software the communication interface setting of FPGA1, so pulse duration is adjustable.
Further, described PWM generator 3 is DS1023S, and the I of the pulsewidth of the narrow pulse signal that this device can produce reaches 5ns, belongs to super burst pulse type; The minimum adjustable stepping of this device is 0.25ns.
Described multipath high-speed or logical block 4, its function are that the multiple signals of input are done exclusive disjunction (a kind of logical operation), and its output is exactly the exclusive disjunction output of multichannel input signal.
Further, described multipath high-speed or logical block 4 adopt basic 2 inputs at a high speed or door 6 is realized by cascade system.
Described line drive spare 5, its function are to input driving force more weak pulse signal, export after strengthening its driving force, improve simultaneously the rising edge of signal, thus the more perfect pulse signal of acquisition.
A kind of implementation method that produces the signal generator of a plurality of super burst pulses, specific as follows:
The first step: FPGA1 produces N road (N 〉=2) and has the triggering signal of same frequency, first via triggering signal S11 is directly inputted PWM generator 3 and is exported the narrow pulse signal S13 that the first via does not have time-delay by FPGA1, all the other each road triggering signal S21, S31......SN1 input respectively each delay line device 2, by delay line device 2 delay time respectively output time delayed signal S22, S32......SN2 after the different time;
Second step: each different road time delayed signal S22, S32......SN2 of delay time inputs respectively PWM generator 3, becomes delay time different narrow pulse signal S23, S33......SN3 after PWM generator 3 outputs;
The 3rd step: two inputs that the narrow pulse signal that the described first via not have the narrow pulse signal S13 and the second tunnel of time-delay to delay time divides S23 not input multipath high-speed or logical block 4 carry out exclusive disjunction; Two inputs that the narrow pulse signal S33 of Third Road time-delay and the narrow pulse signal of the four tunnel time-delay are inputted respectively multipath high-speed or logical block 4 carry out exclusive disjunction; By that analogy, the result of every two-way exclusive disjunction is proceeded exclusive disjunction more as stated above, until finally only have the output of one road signal, namely export the one tunnel many narrow pulse signals So with a plurality of burst pulses;
The 4th step: above-mentioned many narrow pulse signals So input line driving element 5, then export more perfect many narrow pulse signals that one tunnel driving force strengthens, rising edge improves.
Embodiment 1: as shown in Figure 2: get N=4, first output of FPGA1 connects the input of first PWM generator 3, other outputs of FPGA1 connect respectively the input of three delay line devices 2, the output of three delay line devices 2 connect respectively second and third, the input of four PWM generator 3, connect one to one respectively four inputs of multipath high-speed or logical block 4 of the output of four PWM generator 3, the output connecting line driving element 5 of multipath high-speed or logical block 4.
Such as Fig. 2, shown in Figure 3: the width of a burst pulse of supposing many narrow pulse signals So of output is T, the model of PWM generator 3 is DS1023S, FPGA1 exports four tunnel triggering signals and is respectively: S11, S21, S31, S41, first via triggering signal S11 is time-delay not, be S22 after the second tunnel triggering signal S21 time-delay 2T output, being S32 after the Third Road triggering signal S31 time-delay 4T output, is S42 after the four tunnel triggering signal time-delay 6T output; S11, S22, S32, S42 export respectively four tunnel super narrow pulse signal S13, S23, S33, S43 after PWM generator 3, wherein S13 and S23 do exclusive disjunction, S33 and S43 do exclusive disjunction, and then the result of two-way exclusive disjunction done exclusive disjunction again, finally export one tunnel signal So that four super burst pulses are arranged;
The signal So input line driving element 5 that four super burst pulses are arranged is exported the signal that four super burst pulses are more perfectly arranged that a driving force strengthens, rising edge improves at last.
Above demonstration and description be basic principle of the present invention, principal character and advantage of the present invention; the technical staff of the industry should understand the restriction that the present invention is not subjected to said method; that describes in said method and the specification just says principle of the present invention; the present invention also has various changes and modifications without departing from the spirit and scope of the present invention, and these changes and improvements all fall in the protection range that is defined by appending claims of the present invention and equivalent thereof.
Claims (11)
1. signal generator that can produce a plurality of super burst pulses, comprise FPGA, at least one delay line device, a plurality of PWM generator, multipath high-speed or logical block and line drive spare, it is characterized in that: first output of FPGA connects the input of first PWM generator, other outputs of FPGA connect respectively the input of delay line device, the output of delay line device connects respectively the input of other PWM generator except first PWM generator, connect one to one the respectively input of multipath high-speed or logical block of the output of each PWM generator, the output connecting line driving element of multipath high-speed or logical block.
2. a kind of signal generator that produces a plurality of super burst pulses according to claim 1 is characterized in that: described FPGA produces multichannel and has the triggering signal of same frequency.
3. a kind of signal generator that produces a plurality of super burst pulses according to claim 2, it is characterized in that: the triggering signal that described multichannel has same frequency arranges different delay times.
4. a kind of signal generator that produces a plurality of super burst pulses according to claim 1 is characterized in that: the repetition rate of the multichannel triggering signal that described FPGA produces is by the communication interface setting of upper computer software by FPGA.
5. a kind of signal generator that produces a plurality of super burst pulses according to claim 1, it is characterized in that: the model of described delay line device is DS1021S.
6. a kind of signal generator that produces a plurality of super burst pulses according to claim 1 is characterized in that: the delay time of described delay line device can be by the communication interface setting of upper computer software by FPGA.
7. it is characterized in that according to claim 4 or 6 described a kind of signal generators that produce a plurality of super burst pulses: described communication interface adopts the RS232 interface.
8. a kind of signal generator that produces a plurality of super burst pulses according to claim 1, it is characterized in that: the model of described PWM generator is DS 1023S.
9. a kind of signal generator that produces a plurality of super burst pulses according to claim 1 is characterized in that: the pulse duration of described PWM generator output can be by the communication interface setting of upper computer software by FPGA.
10. a kind of signal generator that produces a plurality of super burst pulses according to claim 1 is characterized in that: described multipath high-speed or logical block adopt basic 2 inputs at a high speed or door is realized by cascade system.
11. the implementation method that can produce the signal generator of a plurality of super burst pulses comprises the steps:
The first step: FPGA produces multichannel and has the triggering signal of same frequency, first via triggering signal is directly inputted PWM generator and is exported the narrow pulse signal that the first via does not have time-delay by FPGA, all the other each road triggering signals are inputted respectively with it corresponding delay line device, are delayed time respectively by the delay line device and export after the different time;
Second step: each different road triggering signal of delay time is inputted respectively PWM generator, becomes the different narrow pulse signal of delay time after PWM generator output;
The 3rd step: two inputs that the narrow pulse signal that the described first via not have the narrow pulse signal and the second tunnel of time-delay to delay time is inputted respectively multipath high-speed or logical block carry out exclusive disjunction; Two inputs that the narrow pulse signal of Third Road time-delay and the narrow pulse signal of the four tunnel time-delay are inputted respectively multipath high-speed or logical block carry out exclusive disjunction; By that analogy, the result of every two-way exclusive disjunction is proceeded exclusive disjunction more as stated above, until finally only have the output of one road signal, namely export the one tunnel many narrow pulse signals with a plurality of burst pulses;
The 4th step: above-mentioned many narrow pulse signals input line driving element, then export more perfect many narrow pulse signals that a driving force strengthens, rising edge improves.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103762964A (en) * | 2014-01-17 | 2014-04-30 | 北京航空航天大学 | Multi-channel high-precision PWM signal sampling and generation device |
| CN108011619A (en) * | 2017-12-08 | 2018-05-08 | 成都前锋电子仪器有限责任公司 | A kind of pulse pattern generator |
| CN109660302A (en) * | 2018-12-05 | 2019-04-19 | 中国人民解放军国防科技大学 | Radio frequency pulse width modulator based on digital delay line unit and modulation method |
| CN114415364A (en) * | 2022-02-08 | 2022-04-29 | 南京邮电大学 | Time division based multi-focus imaging system |
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2011
- 2011-09-30 CN CN 201110295199 patent/CN103036539A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103762964A (en) * | 2014-01-17 | 2014-04-30 | 北京航空航天大学 | Multi-channel high-precision PWM signal sampling and generation device |
| CN103762964B (en) * | 2014-01-17 | 2016-05-18 | 北京航空航天大学 | A kind of multi-channel high-accuracy pwm signal sampling and generating apparatus |
| CN108011619A (en) * | 2017-12-08 | 2018-05-08 | 成都前锋电子仪器有限责任公司 | A kind of pulse pattern generator |
| CN108011619B (en) * | 2017-12-08 | 2024-01-30 | 成都前锋电子仪器有限责任公司 | Pulse code pattern generator |
| CN109660302A (en) * | 2018-12-05 | 2019-04-19 | 中国人民解放军国防科技大学 | Radio frequency pulse width modulator based on digital delay line unit and modulation method |
| CN114415364A (en) * | 2022-02-08 | 2022-04-29 | 南京邮电大学 | Time division based multi-focus imaging system |
| CN114415364B (en) * | 2022-02-08 | 2023-11-14 | 南京邮电大学 | Time division based multi-focus imaging system |
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Application publication date: 20130410 |