CN103036535A - Phase interpolation circuit - Google Patents
Phase interpolation circuit Download PDFInfo
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- CN103036535A CN103036535A CN2011103040740A CN201110304074A CN103036535A CN 103036535 A CN103036535 A CN 103036535A CN 2011103040740 A CN2011103040740 A CN 2011103040740A CN 201110304074 A CN201110304074 A CN 201110304074A CN 103036535 A CN103036535 A CN 103036535A
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Abstract
A phase interpolation circuit comprises a first multiplexer, a second multiplexer, an interpolator and a work cycle modifier. The first multiplexer receives multiple even term signals. The second multiplexer receives multiple odd term signals. The interpolator receives a first reference signal formed by one of the multiple even term signals through the first multiplexer, and receives a second reference signal formed by the multiple odd term signals through the second multiplexer. Besides, the interpolator divides a phase difference between the first reference signal and the second reference signal into multiple sub phases according to a digital control signal and selects one of the multiple sub phases to generate a differential input signal. The work cycle modifier adjusts the work cycle of the differential input signal so as to generate a differential input signal with a work cycle which is 50% of the work cycle of the original differential input signal.
Description
Technical field
The invention relates to a kind of phase interpolation circuit, and particularly relevant for a kind of in order to produce the phase interpolation circuit that the work period is 50% differential output signal.
Background technology
The interface module of existing high-speed transfer (for example: USB 3.0 interface modules) be typically provided with a clock pulse data recovery circuit (clock and data recovery circuit), being reduced with the signal of noise component.Wherein, phase interpolation circuit (phase interpolation circuit) is again the core circuit that consists of clock pulse data restore circuit.Therefore, how to improve phase interpolation circuit and become an important topic with the overall performance that promotes clock pulse data restore circuit.
In general, phase interpolation circuit can adopt CML (current mode logic) to form, to meet the demand of high-speed transfer.Yet, but comprise following shortcoming take CML as main phase interpolation circuit: 1 linearity is subject to the impact of parasitic capacitance and front stage circuits load easily, and then cause the work period (duty cycle) of output signal to vary widely, especially under the impact of process shifts, obvious especially; 2 are unfavorable for the operation in low-voltage, and then cause being limited in scope between the operating space.
Therefore, how adjusting the work period of output signal or be conducive to the operation of low-voltage, has been the in design problem that solves of institute's wish of phase interpolation circuit.
Summary of the invention
The invention provides a kind of phase interpolation circuit, adjust the work period of differential output signal by the work period corrector.Thus, can solve under the impact of process shifts the situation of the easy acute variation of work period of differential output signal.
The present invention proposes a kind of phase interpolation circuit, comprising:
One first multiplexer (multiplexer) receives a plurality of even item signals;
One second multiplexer receives a plurality of odd item signals;
One interpolater, receive one first reference signal that the one by described even item signal consists of by this first multiplexer, and receive one second reference signal that the one by described odd item signal consists of by this second multiplexer, and this interpolater is divided into a plurality of sub-phase places according to a digital controlled signal with the phase difference between this first reference signal and this second reference signal, and the one of selecting described sub-phase place is to produce a differential input signal; And
One work period corrector (duty-cycle repeater) is adjusted work period of this differential input signal, to produce the differential output signal of work period as 50%.
In other words, the present invention proposes a kind of phase interpolation circuit, comprises the first multiplexer, the second multiplexer, interpolater and work period corrector.Wherein, the first multiplexer receives a plurality of even item signals.The second multiplexer receives a plurality of odd item signals.Interpolater receives the first reference signal that the one by these even item signals consists of by the first multiplexer, and receives the second reference signal that the one by these odd item signals consists of by the second multiplexer.In addition, interpolater is divided into a plurality of sub-phase places according to digital controlled signal with the phase difference between the first reference signal and the second reference signal, and provides thinner phase signal according to the demand of the work period corrector of rear class.The work period corrector is adjusted the work period of differential input signal, to produce the differential output signal of work period as 50%.
In one embodiment of this invention, the first above-mentioned multiplexer is selected each other two even item signals of complement code from these even item signals, and interpolater chooses one as the first reference signal from two selected even item signals.In addition, the second multiplexer is selected each other two odd item signals of complement code from these odd item signals, and interpolater chooses one as the second reference signal from two selected odd item signals.
In one embodiment of this invention, above-mentioned interpolater comprises bias voltage generation unit, current source, load unit and input unit.Wherein, the bias voltage generation unit produces a plurality of the first bias voltages according to digital controlled signal, and produces a plurality of the second bias voltages according to the complement code of digital controlled signal.Current source receives these first bias voltages and these the second bias voltages, and produces according to this first electric current and the second electric current.Input unit is electrically connected between load unit and the current source, and switches the first electric current and the second current lead-through to the path of load unit, to produce differential input signal according to the first reference signal and the second reference signal.
Based on above-mentioned, the present invention adjusts the work period of differential output signal by the work period corrector, and then avoids the work period of differential output signal to produce violent variation in response to the impact of process shifts.In addition, the bias voltage generation unit in the interpolater of the present invention independently is arranged on outside the formed framework that splices of load unit, input unit and current source.Thus, interpolater will be conducive to the operation of low-voltage, and then promote the range of application of phase interpolation circuit.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended accompanying drawing to be described in detail below.
Description of drawings
Fig. 1 is the block schematic diagram according to the phase interpolation circuit of one embodiment of the invention.
Fig. 2 is the circuit diagram according to the interpolater of one embodiment of the invention.
Fig. 3 is the circuit diagram according to the work period corrector of one embodiment of the invention.
Fig. 4 is the circuit diagram according to the phase blender of one embodiment of the invention.
[main element symbol description]
100: phase interpolation circuit
110,120: multiplexer
130: interpolater
140: the work period corrector
P0～P7: phase signal
CKI, CKIB: in order to consist of two input signals of differential input signal
CKO, CKOB: in order to consist of two output signals of differential output signal
210: the bias voltage generation unit
220: current source
230: load unit
240: input unit
VD: supply voltage
VT1, VT2: fixed voltage
MP11～MP1n, MP21～MP2n, MP31～MP3n, MP41～MP4n, MP5～MP11:P transistor npn npn
MN11～MN1n, MN21～MN2n, MN3～MN9:N transistor npn npn
P0, P1: reference signal
/ P0 ,/P1: the inversion signal of reference signal
B0～bn: digital controlled signal
/ b0～/bn: the complement code of digital controlled signal
VA0～VAn, VB0～VBn: bias voltage
I1, I2: electric current
311～314: phase blender
321～324,420: inverter
/ CKIB ,/CKI: rp input signal
410: delay element.
Embodiment
Fig. 1 is the block schematic diagram according to the phase interpolation circuit of one embodiment of the invention.With reference to Fig. 1, phase interpolation circuit 100 comprises multiplexer 110, multiplexer 120, interpolater 130 and work period corrector (duty-cycle repeater) 140.Wherein, phase interpolation circuit 100 can be applicable in the clock pulse data restore circuit, especially for the interface module of high-speed transfer (for example: the clock pulse data restore circuit USB 3.0 interface modules).
Please continue with reference to Fig. 1, multiplexer 110 receives respectively a plurality of phase signals with multiplexer 120.For instance, in a preferred embodiment, by 360 degree are divided into 8 five equilibriums, obtaining 8 phase signal P0～P7, that is 0 °, 45 °, 90 °, 135 ° ..., 315 °.Wherein, described 8 phase signal P0～P7 differ 45 degree separately.In addition, phase signal P0, P2, P4, P6 are respectively the even-multiples of basic phase places of 45 degree, so phase signal P0, P2, P4, P6 can be considered again a plurality of even items (even order) signal.Moreover phase signal P1, P3, P5, P7 then are respectively the odd-multiple of basic phase places of 45 degree, so phase signal P1, P3, P5, P7 can be considered again a plurality of odd items (odd order) signal.
In preferred embodiment, multiplexer 110 receives 4 phase signal P0, P2, P4, P6, that is 4 even item signal P0, P2, P4, P6.In addition, multiplexer 120 receives 4 phase signal P1, P3, P5, P7, that is 4 odd item signal P1, P3, P5, P7.In other words, control for the ease of phase place, present embodiment is the phase signal that the mode that adopts odd even to separate distributes two multiplexers to receive, for example: multiplexer 110 is the phase signals (that is even item signal) that receive even item (P0, P2, P4, P6), and multiplexer 120 is the phase signals (that is odd item signal) that receive odd item (P1, P3, P5, P7).
In other words, interpolater 130 can receive by phase signal P0, P2, P4, P6 (namely by multiplexer 110, even item signal) one consist of a reference signal (for example: phase signal P0), and (for example: phase signal P1) receive a reference signal that the one by phase signal P1, P3, P5, P7 (that is, odd item signal) consists of by multiplexer 120.After the action of choosing signal was complete, the reference signal that phase interpolation circuit 100 is about to selected taking-up was passed to phase interpolator 130, the action of cutting apart to carry out phase place.At this, interpolater 130 can be divided into a plurality of sub-phase places with the phase difference between two reference signals according to a digital controlled signal, and the one of selecting described a plurality of sub-phase places is to produce a differential input signal.
Thus, interpolater 130 can mark off a plurality of sub-phase places between two reference signals.In addition, by the switching of multiplexer 110 and 120, interpolater 130 can receive two reference signals that are made of the out of phase signal, and then produces how different sub-phase places.In addition, in the present embodiment, interpolater 130 is that the mode with differential input receives respectively two reference signals, and produces a differential input signal in the mode of differential output.Therefore, the differential input signal of present embodiment is made of input signal CKI and input signal CKIB.
On the other hand, work period corrector 140 can be adjusted the work period of differential input signal, and to produce according to this work period be 50% differential output signal, and wherein the differential output signal is made of output signal CKO and output signal CKOB.In other words, phase interpolation circuit 100 can be adjusted by work period corrector 140 work period of differential output signal, and then solves under the impact of process shifts the situation of the easy acute variation of work period of differential output signal.
Usually know that in order to cause this area to have the knowledgeable can more understand the present invention, below will describe for the thin section structure of interpolater 130 with work period corrector 140.
Fig. 2 is the circuit diagram according to the interpolater of one embodiment of the invention.With reference to Fig. 2, interpolater 130 comprises bias voltage generation unit 210, current source 220, load unit 230 and input unit 240.At this, suppose that two reference signals that interpolater 130 receives are phase signal P0 and phase signal P1, and for convenience of description, below two reference signals are denoted as P0 and P1.In addition, the digital controlled signal that interpolater 130 receives be expressed as bn ..., b1, b0}, and the complement code of digital controlled signal be/bn ... ,/b1 ,/b0}.
As shown in Figure 2, bias voltage generation unit 210 can according to digital controlled signal bn ..., b1, b0} produce a plurality of bias voltage VA0～VAn, and according to the complement code of digital controlled signal/bn ... ,/b1 ,/b0} produce a plurality of voltage bias VB 0～VBn.Current source 220 will receive bias voltage VA0～VAn and VB0～VBn, and according to this generation current I1 and electric current I 2.In addition, input unit 230 is electrically connected between load unit 240 and the current source 220, and according to reference signal P0 and P1 switch current I1 and the I2 conducting path to load unit 240.Thus, input unit 230 can produce the differential input signal that is made of input signal CKI and CKIB.
It is worth mentioning that, circuit structure with regard to interpolater 130, load unit 240, input unit 230 and current source 220 splice together mutually, and then form and to be stacked into 3 layers the framework that splices, and bias voltage generation unit 210 then independently is arranged on outside this framework that splices.And know that if the stacking number of plies is higher, the required supply voltage of circuit is also just larger.Therefore, with traditional interpolater in comparison because traditional interpolater has the framework that splices that is stacked into more than 4 layers, so the interpolater 130 of present embodiment not only is conducive to the operation of low-voltage, more because reducing the effect of parasitic capacitance, so under the high speed operation environment, also better usefulness can be arranged.
Further, current source 220 comprises N-type transistor MN11～MN1n and N-type transistor MN21～MN2n.Wherein, the drain electrode of N-type transistor MN11～MN1n and MN21～MN2n all is electrically connected input unit 230, and the source electrode of N-type transistor MN11～MN1n and MN21～MN2n all is electrically connected to earth terminal.In addition, N-type transistor MN11～MN1n and N-type transistor MN21～MN2n are controlled by bias voltage VA0～VAn and the VB0～VBn that bias voltage generation unit 210 produces, to adjust the size of electric current I 1 and I2.
Input unit 230 comprises N-type transistor MN3～MN6.Wherein, the drain electrode of N-type transistor MN3～MN6 all is electrically connected load unit 240.In addition, the source electrode of N-type transistor MN3 and MN4 all is electrically connected the drain electrode of N-type transistor MN11～MN1n, and the source electrode of N-type transistor MN5 and MN6 all is electrically connected the drain electrode of N-type transistor MN21～MN2n.At this, it is right that N-type transistor MN3 and MN4 form a differential input, and utilize respectively its grid to receive inversion signal/P0 of reference signal P0 and reference signal P0.Similarly, it is right that N-type transistor MN5 and MN6 form another differential input, and utilize respectively its grid to receive inversion signal/P1 of reference signal P1 and reference signal P1.
Load unit 240 comprises P transistor npn npn MP5～MP8.Wherein, 1 source electrode of P transistor npn npn MP5～MP8 all receives supply voltage VD.In addition, the grid of P transistor npn npn MP6 be electrically connected its drain electrode, and the grid of P transistor npn npn MP8 be electrically connected its drain electrode, with the connection framework of each self-forming diode.Moreover P transistor npn npn MP5 and P transistor npn npn MP6 are in electrically upper connected with each other, and the grid of P transistor npn npn MP5 receives fixed voltage VT2.Similarly, P transistor npn npn MP7 and P transistor npn npn MP8 are in electrically upper connected with each other, and the grid of P transistor npn npn MP7 receives fixed voltage VT2.Thus, in twos and the P transistor npn npn that connects the better linearity and noise resisting ability can be provided.
Bias voltage generation unit 210 comprises P transistor npn npn MP11～MP1n, P transistor npn npn MP21～MP2n, P transistor npn npn MP31～MP3n and P transistor npn npn MP41～MP4n.Wherein, the source electrode of P transistor npn npn MP11 receives supply voltage VD, and the grid of P transistor npn npn MP11 receives the position b0 in the digital controlled signal, and the drain electrode of P transistor npn npn MP11 is electrically connected the grid of the N-type transistor MN1 in the current source 220.In addition, the source electrode of P transistor npn npn MP21 is electrically connected the drain electrode of P transistor npn npn MP11, and the grid of P transistor npn npn MP21 receives fixed voltage VT1, and the drain electrode of P transistor npn npn MP21 is electrically connected to earth terminal.By that analogy, be connected framework between P transistor npn npn MP12～MP1n and the P transistor npn npn MP22～MP2n.
In addition, be connected framework between P transistor npn npn MP31～MP3n and the P transistor npn npn MP41～MP4n, with between P transistor npn npn MP11～MP1n and the P transistor npn npn MP21～MP2n to be connected framework similar.And both maximum differences are, the grid of P transistor npn npn MP11～MP1n be receive digital controlled signal bn ..., and b1, b0}, the grid of P transistor npn npn MP31～MP3n then be the complement code that receives digital controlled signal/bn ... ,/b1 ,/b0}.Therefore, in practical operation, the conducting state of the P transistor npn npn MP11～MP1n just conducting state with P transistor npn npn MP31～MP3n is opposite.
The total sight, interpolater 130 is the frameworks that adopt differential input and differential output, so all has similar framework in the unit and receive or produce inversion signal.In addition, the phase interpolation that carries out of interpolater 130 can utilize the basic operation formula shown in the formula 1 to represent:
Wherein, Φ
AWith Φ
BBe respectively the phase place of reference signal P0 and P1, W is total interpolation amount, and w is the interpolation amount, Φ
ABThe phase place of the differential input signal that goes out for institute's interpolation.
In operation, the fixed voltage VT1 in the bias voltage generation unit 210 is in order to P transistor npn npn MP21～MP2n and P transistor npn npn MP41～MP4n are biased in linear zone.Therefore, the P transistor npn npn MP11 and the MP21 that just are connected in series in twos, when P transistor npn npn MP11 conducting, bias voltage VA0 will be pulled to supply voltage VD.At this moment, the N-type transistor MN11 in the current source 220 is with conducting, and then the magnitude of current of raising electric current I 1.Otherwise when not conducting of P transistor npn npn MP11, bias voltage VA0 will be pulled down to earthed voltage.At this moment, the N-type transistor MN11 in the current source 220 is with not conducting, and then the magnitude of current of reduction electric current I 1.In other words, along with the change of bias voltage VA0～VAn and VB0～VBn, the N-type transistor MN11～MN1n in the current source 220 and the conducting number of MN21～MN2n are also with different.Thus, electric current I 1 and the I2 that current source 220 provides also will produce corresponding the variation, and then reach the adjustment of the interpolation amount w when carrying out phase interpolation.
For instance, if current source 220 comprises 6 N-type transistor MN11～MN13 and MN21～MN23, and the phase place of reference signal P0 and P1 be respectively 0 the degree with 45 the degree, then in the control of interpolation phase place, the resolution of digital controlled signal then is 3.In addition, when digital controlled signal be { during 011}, 1 P transistor npn npn MN11 conducting only to be arranged among 3 P transistor npn npn MP11～MP13.That is this moment is in order to only to have N-type transistor MN11 conducting among 3 N-type transistor MN11～MN13 that control electric current I 1.Therefore, in the calculating of formula 1, Φ
A=0, Φ
B=45, W=3, w=1 are so the phase place of the input signal CKI that MN3 and MN4 is produced by differential input is 30 degree.
Fig. 3 is the circuit diagram according to the work period corrector of one embodiment of the invention.With reference to Fig. 3, work period corrector 140 comprises phase blender (phase blender) 311～314 and inverter 321～324.Wherein, the input of inverter 322 is electrically connected the output of phase blender 311 and phase blender 312 simultaneously, and the input of phase blender 312 is electrically connected the output of inverter 321.At this, phase blender 311 can give input signal CKI anti-phase, and adjusts the work period of the input signal CKI after anti-phase.
On the other hand, inverter 321 gives input signal CKIB anti-phase, to produce rp input signal/CKIB.Phase blender 312 gives rp input signal/CKIB anti-phase, and adjusts the work period of the rp input signal/CKIB after anti-phase.In addition, different along with the level of input signal CKI and rp input signal/CKIB, two phase place blender 311 and 312 promotes the mode of inverters 322 also with different.Thus, the output signal CKO that produces of inverter 322 can be expressed as: CKO=(CKI+/CKIB)/2.Thus, the work period of the output signal CKO that inverter 322 produces will be adjusted to 50%, and the skew of output signal CKO (skew) also can be removed.
Similarly, the input of inverter 324 is electrically connected the output of phase blender 313 and phase blender 314 simultaneously, and the input of phase blender 314 is electrically connected the output of inverter 323.At this, phase blender 313 can give input signal CKIB anti-phase, and adjusts the work period of the input signal CKIB after anti-phase.In addition, inverter 323 gives input signal CKI anti-phase, to produce rp input signal/CKI.Phase blender 314 gives rp input signal/CKI anti-phase, and adjusts the work period of the rp input signal/CKI after anti-phase.In addition, the output signal CKOB that produces of inverter 324 can be expressed as: CKOB=(CKIB+/CKI)/2.Thus, the work period of the output signal CKOB that inverter 324 produces will be adjusted to 50%, and the skew of output signal CKOB also can be removed.
Fig. 4 is the circuit diagram according to the phase blender of one embodiment of the invention.The circuit of present embodiment is to replace traditional phase blender, therefore, when being applied in Fig. 3,311 and 312,313 and 314 equal and opposite in direction.This is different from traditional take inverter as main phase blender, if its shortcoming is output phase will be adjusted to 50% accurately, then the large young pathbreaker of above-mentioned four phase blenders is unequal, for example, and periodical: B.W.Garlepp et al., " A PortableDigital DLL for High-Speed CMOS Interface Circuits ", IEEE JOURNALOF SOLID-STATE CIRCUITS, VOL.34, No.5, pp.632-644, May 1999.With reference to Fig. 4, phase blender 311 comprises P transistor npn npn MP9～MP11, N-type transistor MN7～MN9, delay element 410 and inverter 420.Wherein, the source electrode of P transistor npn npn MP9 and P transistor npn npn MP10 receives supply voltage VD.The grid of P transistor npn npn MP9 is electrically connected to earth terminal, and the drain electrode of P transistor npn npn MP9 is electrically connected the drain electrode of P transistor npn npn MP10.The source electrode of P transistor npn npn MN11 is electrically connected the drain electrode of P transistor npn npn MP10, and the grid of P transistor npn npn MP11 receives input signal CKI, and the drain electrode of P transistor npn npn MP11 is electrically connected inverter 322.
Moreover the drain electrode of N-type transistor MN7 is electrically connected the drain electrode of P transistor npn npn MP11, and the grid of N-type transistor MN7 receives input signal CKI.The drain electrode of N-type transistor MN8 and N-type transistor MN9 is electrically connected the source electrode of N-type transistor MN7.In addition, the grid of N-type transistor MN8 receives supply voltage VD, and the drain electrode of N-type transistor MN8 is electrically connected to earth terminal.The grid of N-type transistor MN9 is electrically connected the grid of P transistor npn npn MP10, and the drain electrode of N-type transistor MN9 is electrically connected to earth terminal.Delay element 410 is in order to delay input signal CKI.Input signal CKI after inverter 420 will postpone gives anti-phase, and outputs signal to the grid of N-type transistor MN9 and the grid of P transistor npn npn MP10.
In operation, P transistor npn npn MP11 and N-type transistor MN7 can form an inverter, and carry out anti-phase to input signal CKI.In addition, input signal CKI can the delay via delay element 410 after, undertaken anti-phase by inverter 420.Afterwards, the output signal that inverter 420 produces will in order to control P transistor npn npn MP10 and N-type transistor MN9, be supplied to the charging current of P transistor npn npn MP11 and the discharging current that flows through N-type transistor MN7 with adjustment.For instance, when the level of the output signal that produces when inverter 420 descends, the charging current that is supplied to P transistor npn npn MP11 will become greatly, and the discharging current that flows through N-type transistor MN7 will diminish, and then cause the work period of the input signal CKI after anti-phase to become large.Otherwise during the electrical level rising of the output signal that produces when inverter 420, the work period of the input signal CKI after anti-phase will diminish.Thus, input signal CKI is being carried out in the anti-phase process, can adjust the work period of the input signal CKI after anti-phase.
In sum, the work period of the signal that phase interpolator is exported produces change easily, therefore the present invention adjusts the work period of the signal that phase interpolator exports by the work period corrector, and then solves under the impact of process shifts the situation of easy acute variation of work period.In addition, the present invention causes the bias voltage generation unit of interpolater independent outside the framework that splices by changing the mode of internal bias voltage.Thus, interpolater will be conducive to the operation of low-voltage, and then promote the range of application of phase interpolation circuit.
Although the present invention discloses as above with embodiment; so it is not to limit the present invention; any person of ordinary skill in the field without departing from the spirit and scope of the present invention, when can doing a little change and retouching, so protection scope of the present invention is when looking being as the criterion that claim defines.
Claims (9)
1. phase interpolation circuit comprises:
One first multiplexer receives a plurality of even item signals;
One second multiplexer receives a plurality of odd item signals;
One interpolater, receive one first reference signal that the one by described even item signal consists of by this first multiplexer, and receive one second reference signal that the one by described odd item signal consists of by this second multiplexer, and this interpolater is divided into a plurality of sub-phase places according to a digital controlled signal with the phase difference between this first reference signal and this second reference signal, and the one of selecting described sub-phase place is to produce a differential input signal; And
One work period corrector is adjusted work period of this differential input signal, to produce the differential output signal of work period as 50%.
2. phase interpolation circuit according to claim 1, wherein this first multiplexer is selected two even item signals from described even item signal, and this interpolater chooses one as this first reference signal from two selected even item signals, this second multiplexer is selected two odd item signals from described odd item signal, and this interpolater chooses one as this second reference signal from this selected two odd items signal.
3. phase interpolation circuit according to claim 1, wherein this interpolater comprises:
One bias voltage generation unit produces a plurality of the first bias voltages according to this digital controlled signal, and produces a plurality of the second bias voltages according to the complement code of this digital controlled signal;
One current source receives described the first bias voltage and described the second bias voltage, and produces according to this one first electric current and one second electric current;
One load unit; And
One input unit is electrically connected between this load unit and this current source, and switches this first electric current and this second current lead-through to the path of this load unit according to this first reference signal and this second reference signal, to produce this differential input signal.
4. phase interpolation circuit according to claim 3, wherein this bias voltage generation unit comprises:
A plurality of P transistor npn npns, the source electrode of a wherein said P transistor npn npn receives a supply voltage, and the grid of a described P transistor npn npn receives this digital controlled signal, and the drain electrode of a described P transistor npn npn produces described the first bias voltage;
A plurality of the 2nd P transistor npn npns, the source electrode of wherein said the 2nd P transistor npn npn is electrically connected the drain electrode of a described P transistor npn npn, the grid of described the 2nd P transistor npn npn receives one first fixed voltage, and the drain electrode of described the 2nd P transistor npn npn is electrically connected to an earth terminal;
A plurality of the 3rd P transistor npn npns, the source electrode of wherein said the 3rd P transistor npn npn receives this supply voltage, and the grid of described the 3rd P transistor npn npn receives the complement code of this digital controlled signal, and the drain electrode of described the 3rd P transistor npn npn produces described the second bias voltage; And
A plurality of the 4th P transistor npn npns, the source electrode of wherein said the 4th P transistor npn npn is electrically connected the drain electrode of described the 3rd P transistor npn npn, the grid of described the 4th P transistor npn npn receives this first fixed voltage, and the drain electrode of described the 4th P transistor npn npn is electrically connected to this earth terminal.
5. phase interpolation circuit according to claim 4, wherein this current source comprises:
A plurality of the first N-type transistors, the transistorized drain electrode of wherein said the first N-type is electrically connected this input unit, the transistorized grid of described the first N-type is electrically connected the drain electrode of a described P transistor npn npn, and the transistorized source electrode of described the first N-type is electrically connected to this earth terminal; And
A plurality of the second N-type transistors, the transistorized drain electrode of wherein said the second N-type is electrically connected this input unit, the transistorized grid of described the second N-type is electrically connected the drain electrode of described the 3rd P transistor npn npn, and the transistorized source electrode of described the second N-type is electrically connected to this earth terminal.
6. phase interpolation circuit according to claim 5, wherein this input unit comprises:
One the 3rd N-type transistor, wherein the transistorized drain electrode of the 3rd N-type is electrically connected this load unit, and the transistorized grid of the 3rd N-type receives this first reference signal, and the transistorized source electrode of the 3rd N-type is electrically connected the transistorized drain electrode of described the first N-type;
One the 4th N-type transistor, wherein the transistorized drain electrode of the 4th N-type is electrically connected this load unit, the transistorized grid of the 4th N-type receives the inversion signal of this first reference signal, and the transistorized source electrode of the 4th N-type is electrically connected the transistorized drain electrode of described the first N-type;
One the 5th N-type transistor, wherein the transistorized drain electrode of the 5th N-type is electrically connected this load unit, and the transistorized grid of the 5th N-type receives this second reference signal, and the transistorized source electrode of the 5th N-type is electrically connected the transistorized drain electrode of described the second N-type; And
One the 6th N-type transistor, wherein the transistorized drain electrode of the 6th N-type is electrically connected this load unit, the transistorized grid of the 6th N-type receives the inversion signal of this second reference signal, and the transistorized source electrode of the 6th N-type is electrically connected the transistorized drain electrode of described the second N-type.
7. phase interpolation circuit according to claim 6, wherein this load unit comprises:
One the 5th P transistor npn npn, wherein the source electrode of the 5th P transistor npn npn receives this supply voltage, the grid of the 5th P transistor npn npn receives one second fixed voltage, and the drain electrode of the 5th P transistor npn npn is electrically connected the transistorized drain electrode of the 3rd N-type and the transistorized drain electrode of the 5th N-type;
One the 6th P transistor npn npn, wherein the source electrode of the 6th P transistor npn npn receives this supply voltage, and the grid of the 6th P transistor npn npn is electrically connected the drain electrode of the 6th P transistor npn npn and the drain electrode of the 5th P transistor npn npn;
One the 7th P transistor npn npn, wherein the source electrode of the 7th P transistor npn npn receives this supply voltage, the grid of the 7th P transistor npn npn receives this second fixed voltage, and the drain electrode of the 7th P transistor npn npn is electrically connected the transistorized drain electrode of the 4th N-type and the transistorized drain electrode of the 6th N-type; And
One the 8th P transistor npn npn, wherein the source electrode of the 8th P transistor npn npn receives this supply voltage, and the grid of the 8th P transistor npn npn is electrically connected the drain electrode of the 8th P transistor npn npn and the drain electrode of the 7th P transistor npn npn.
8. phase interpolation circuit according to claim 1, wherein this differential input signal comprises one first input signal and one second input signal, this differential output signal comprises one first output signal and one second output signal, and should comprise by the work period corrector:
One first phase blender gives this first input signal anti-phase, and adjusts work period of this first input signal after anti-phase;
One first inverter, this second input signal is given anti-phase, to produce one first rp input signal;
One second phase blender gives this first rp input signal anti-phase, and adjusts work period of this first rp input signal after anti-phase;
One second inverter is electrically connected this first phase blender and this second phase blender, and this second inverter signal that this first phase blender and this second phase blender are produced gives anti-phasely, and produces according to this this first differential output signal;
One third phase position blender gives this second input signal anti-phase, and adjusts work period of this second input signal after anti-phase;
One the 3rd inverter, this first input signal is given anti-phase, to produce one second rp input signal;
One the 4th phase blender gives this second rp input signal anti-phase, and adjusts work period of this second rp input signal after anti-phase; And
One the 4th inverter is electrically connected this third phase position blender and the 4th phase blender, and the 4th inverter signal that this third phase position blender and the 4th phase blender are produced gives anti-phasely, and produces according to this this second differential output signal.
9. phase interpolation circuit according to claim 8, wherein this first phase blender comprises:
One the 9th P transistor npn npn, wherein the source electrode of the 9th P transistor npn npn receives a supply voltage, and the grid of the 9th P transistor npn npn is electrically connected to an earth terminal;
The tenth a P transistor npn npn, wherein the source electrode of the tenth P transistor npn npn receives this supply voltage, and the drain electrode of the tenth P transistor npn npn is electrically connected the drain electrode of this nine P transistor npn npn;
The 11 a P transistor npn npn, wherein the source electrode of the 11 P transistor npn npn is electrically connected the drain electrode of the tenth P transistor npn npn, the grid of the 11 P transistor npn npn receives this first input signal, and the drain electrode of the 11 P transistor npn npn is electrically connected this second inverter;
One the 7th N-type transistor, wherein the transistorized drain electrode of the 7th N-type is electrically connected the drain electrode of the 11 P transistor npn npn, and the transistorized grid of the 7th N-type receives this first input signal;
One the 8th N-type transistor, wherein the transistorized drain electrode of the 8th N-type is electrically connected the transistorized source electrode of the 7th N-type, and the transistorized grid of the 8th N-type receives this supply voltage, and the transistorized drain electrode of the 8th N-type is electrically connected to this earth terminal;
One the 9th N-type transistor, wherein the transistorized drain electrode of the 9th N-type is electrically connected the transistorized source electrode of the 7th N-type, the transistorized grid of the 9th N-type is electrically connected the grid of the tenth P transistor npn npn, and the transistorized drain electrode of this nine N-type is electrically connected to this earth terminal;
One delay element is in order to postpone this first input signal; And
One the 5th inverter gives this first input signal after postponing anti-phase, and outputs signal to the grid of the transistorized grid of the 9th N-type and the tenth P transistor npn npn.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011103040740A CN103036535A (en) | 2011-09-29 | 2011-09-29 | Phase interpolation circuit |
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| CN2011103040740A CN103036535A (en) | 2011-09-29 | 2011-09-29 | Phase interpolation circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105634451A (en) * | 2015-12-29 | 2016-06-01 | 龙迅半导体（合肥）股份有限公司 | Data clock recovery circuit and phase interpolator |
| JP2019507548A (en) * | 2016-01-28 | 2019-03-14 | ザイリンクス インコーポレイテッドＸｉｌｉｎｘ Ｉｎｃｏｒｐｏｒａｔｅｄ | Phase interpolator and method for implementing phase interpolator |
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| CN1612478A (en) * | 2003-10-27 | 2005-05-04 | 扬智科技股份有限公司 | Automatic correcting device and method for pulse working period |
| US20080164930A1 (en) * | 2007-01-04 | 2008-07-10 | Micron Technology, Inc. | Phase interpolation apparatus, systems, and methods |
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- 2011-09-29 CN CN2011103040740A patent/CN103036535A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1612478A (en) * | 2003-10-27 | 2005-05-04 | 扬智科技股份有限公司 | Automatic correcting device and method for pulse working period |
| US20080164930A1 (en) * | 2007-01-04 | 2008-07-10 | Micron Technology, Inc. | Phase interpolation apparatus, systems, and methods |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105634451A (en) * | 2015-12-29 | 2016-06-01 | 龙迅半导体（合肥）股份有限公司 | Data clock recovery circuit and phase interpolator |
| CN105634451B (en) * | 2015-12-29 | 2018-08-28 | 龙迅半导体（合肥）股份有限公司 | A kind of data clock recovery circuit and its phase interpolator |
| JP2019507548A (en) * | 2016-01-28 | 2019-03-14 | ザイリンクス インコーポレイテッドＸｉｌｉｎｘ Ｉｎｃｏｒｐｏｒａｔｅｄ | Phase interpolator and method for implementing phase interpolator |
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Application publication date: 20130410 |