CN103035685A - Selective epitaxy outer base region bipolar transistor containing buried oxygen layer and preparation method thereof - Google Patents
Selective epitaxy outer base region bipolar transistor containing buried oxygen layer and preparation method thereof Download PDFInfo
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- CN103035685A CN103035685A CN2012105354569A CN201210535456A CN103035685A CN 103035685 A CN103035685 A CN 103035685A CN 2012105354569 A CN2012105354569 A CN 2012105354569A CN 201210535456 A CN201210535456 A CN 201210535456A CN 103035685 A CN103035685 A CN 103035685A
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Abstract
The invention discloses a selective epitaxy outer base region bipolar transistor containing a buried oxygen layer and a preparation method thereof and is designed to overcome the defect that BC junction capacity in the prior art is large. The selective epitaxy outer base region bipolar transistor containing the buried oxygen layer comprises a current collection region, an intrinsic base region, the buried oxygen layer, an emitting electrode, a side wall, a silicon layer and an outer base region. One part of the outer base region is arranged below the side wall. The outer base region generates stress on the base region. According to the selective epitaxy outer base region bipolar transistor, the buried oxygen layer is added to the outer base region, the BC junction capacity is lowered, and component performance is improved. The preparation method realizes the selective epitaxy outer base region bipolar transistor containing the buried oxygen layer, and is concise in step, low in cost, simple and easy to operate, and good in obtained structural performance.
Description
Technical field
The present invention relates to a kind of selective epitaxy outer base area bipolar transistor that comprises oxygen buried layer and preparation method thereof.
Background technology
It will be the trend of following wireless technology development that millimeter wave and THZ (Terahertz) use, such as millimetre-wave attenuator, THZ communication, THZ imaging etc.At present these are used main three or five family devices that rely on and finish, and it exists low integrated level, the shortcoming such as expensive, and along with the continuous progress of technology, SiGe device and technology will become the rival of three or five family devices.The germanium silicon technology is widely used in the various aspects such as communication, radar and high speed circuit at present.The commercial germanium silicon technology Ft of IBM (cut-off frequency) has reached 350GHz, and the SiGe device Fmax (peak frequency) of European IHP exploitation has reached 500GHz at normal temperatures.Millimeter wave and THZ for future use, and the performance of SiGe device still needs continuous lifting, and this just needs novel SiGe device structure.
Existing product reduces TED (Transient enhanceddiffusion by outer base area is embedded in the collector region, instantaneous enhancing diffusion) effect, but exist BC knot (base-collector junction) electric capacity problem bigger than normal, affected performance of devices.
Summary of the invention
In order to overcome above-mentioned defective, the invention provides a kind of BC junction capacitance less comprise selective epitaxy outer base area bipolar transistor of oxygen buried layer and preparation method thereof.
For achieving the above object, on the one hand, the invention provides a kind of selective epitaxy outer base area bipolar transistor that comprises oxygen buried layer, described transistor comprises the collector region of the first doping type, be positioned at intrinsic base region and oxygen buried layer on the described collector region, be positioned at the emitter on the described base, be positioned at the side wall of described emitter both sides, be positioned at the silicon layer of the second doping type on the described oxygen buried layer, and be positioned at the outer base area on the described silicon layer.
Particularly, the part of described outer base area is positioned at the below of described side wall.
Particularly, described outer base area produces stress in described base.
On the other hand, the invention provides a kind of selective epitaxy outer base area bipolar transistor tube preparation method that comprises oxygen buried layer, the comprising the steps: at least of described method
4.1 prepare the collector region of the first doping type; Inject formation at described collector region and annotate the oxygen layer, high temperature advances and forms oxygen buried layer;
4.2 the base at resulting structures preparation the second doping type;
4.3 deposit first medium layer on the base;
4.4 offer window at the first medium layer;
4.5 on resulting structures, prepare successively the first doping type polycrystal layer and second medium layer;
4.6 photoetching, the described second medium layer of etching and polycrystal layer form emitter, remove the exposed part of first medium layer;
4.7 deposit the 3rd dielectric layer forms sidewall structure by anisotropic etching in the side of gained emitter structure;
4.8 with the emitter of above-mentioned gained and sidewall structure as sheltering, capped base in the etching resulting structures, etch thicknesses is greater than the thickness of base; Etching stopping during apart from described oxygen buried layer 10nm to 100nm keeps the silicon layer on the described oxygen buried layer, described silicon layer is carried out the second doping type inject;
4.9 adopt in-situ doped selective epitaxial process to prepare the outer base area of the second doping type at resulting structures;
4.10 base region surface prepares the layer of metal silicide structural outside;
4.11 prepare contact hole at resulting structures, draw emitter electrode and base electrode.
Particularly, the material of preparation base is silicon, germanium silicon or carbon dope germanium silicon in the step 4.2.
Particularly, the first medium layer is compound medium layer in the step 4.3, and described compound medium layer comprises the silicon oxide layer that is deposited on base region surface and is deposited on the silicon nitride layer on silicon oxide layer surface.
Particularly, the polycrystal layer in the step 4.5 is polysilicon layer or polycrystalline germanium silicon layer; Dielectric layer is silica or silicon nitride.
Particularly, in the step 4.8 thickness of etching between 10nm to 2000nm; Carry out undercutting to the side wall below during etching base.
Particularly, the outer base area in the step 4.9 uses the preparation of selective epitaxy growing method, and the material of outer base area is silicon, or germanium silicon, or carbon dope germanium silicon; The doping content of impurity is at 1E19～1E21cm
-3
The selective epitaxy outer base area bipolar transistor that the present invention comprises oxygen buried layer adds oxygen buried layer under outer base area, reduced the BC junction capacitance, has improved device performance.
The present invention comprises the selective epitaxy outer base area bipolar transistor tube preparation method of oxygen buried layer and has realized that the present invention comprises the selective epitaxy outer base area bipolar transistor of oxygen buried layer, and step is terse, and cost is low, operates simple and easyly, and resulting structures is functional.
Description of drawings
Fig. 1～Fig. 8 is preferred embodiment of the present invention structural representation.
Embodiment
Below in conjunction with Figure of description and preferred embodiment the present invention is described in detail.
Preferred embodiment: the preparation method of the embedded extension outer base area of the present invention bipolar transistor comprises the steps: at least
As shown in Figure 1, the collector region 101 for preparing the first doping type.Inject formation at collector region 101 and annotate the oxygen layer, high temperature advances and forms oxygen buried layer 201.
As shown in Figure 2, epitaxial growth one deck impure base region 102 on collector region 101, the base is the second doping type.The material of base 102 is germanium silicon.Deposit first medium layer on base 102.The preferred structure of first medium layer is a compound medium layer, and this compound medium layer is successively silicon oxide layer 104 and silicon nitride layer 106 from top to bottom, and wherein, silica is etching stop layer.
As shown in Figure 3, photoetching, etch silicon nitride layer 106 form emitter-window, and then the selective corrosion silicon oxide layer 104, expose base 102 monocrystalline.Dry etching is used in selective corrosion.
As shown in Figure 4, deposit polycrystal layer 108 and second medium layer 110.Wherein, polycrystal layer 108 is polysilicon layers.Polycrystal layer 108 needs to mix, and doping way is dopant implant, and impurity adopts the first doping type.Dielectric layer 110 is silicon oxide layers.
As shown in Figure 5, form emitter by photoetching, etching second medium layer 110 and polycrystal layer 108.Remove the part that silicon oxide layer 104 and silicon nitride layer 106 expose, expose base 102 monocrystalline.
As shown in Figure 6, deposit the 3rd dielectric layer forms sidewall structure 113 by anisotropic etching in the side of gained emitter structure.
As shown in Figure 7, for sheltering, etching extension base 102 in distance oxygen buried layer 201 upper surface 20nm place etching stopping, keeps the silicon layer on the oxygen buried layer 201 to collector region 101, obtains etched area 115 with emitter structure.The silicon layer that keeps is carried out the second doping type to be injected.The main purpose that adopts this structure is to reduce simultaneously the BC junction capacitance in reduction TED effect.Etching preferably has undercutting to a certain degree, can further reduce outer base area resistance like this.
As shown in Figure 8, selective epitaxial one deck outer base area 120 is in-situ doped on the structure of etching gained.This epitaxial film materials is germanium silicon.Impurity is the second doping type.For reducing outer base area 120 resistance, doping content will be tried one's best high, generally should be at 1E19～1E21cm
-3For the NPN device, use boron to mix.
Base region surface prepares the layer of metal silicide structural outside.Then prepare contact hole at resulting structures, draw emitter electrode and base electrode.
Preferred embodiment two: the collector region 101 for preparing the first doping type.Inject formation at collector region 101 and annotate the oxygen layer, high temperature advances and forms oxygen buried layer 201.
As shown in Figure 2, epitaxial growth one deck impure base region 102 on collector region 101, the base is the second doping type.The material of base 102 is carbon dope germanium silicon.Deposit first medium layer on base 102.The preferred structure of first medium layer is a compound medium layer, and this compound medium layer is successively silicon oxide layer 104 and silicon nitride layer 106 from top to bottom, and wherein, silica is etching stop layer.
As shown in Figure 3, photoetching, etch silicon nitride layer 106 form emitter-window, and then the selective corrosion silicon oxide layer 104, expose base 102 monocrystalline.Wet etching is used in selective corrosion.
As shown in Figure 4, deposit polycrystal layer 108 and second medium layer 110.Wherein, polycrystal layer 108 is polycrystalline germanium silicon layers.Polycrystal layer 108 needs to mix, and doping way is in-situ doped, and impurity adopts the first doping type.Dielectric layer 110 is silicon nitride layers.
As shown in Figure 5, form emitter by photoetching, etching second medium layer 110 and polycrystal layer 108.Remove the part that silicon oxide layer 104 and silicon nitride layer 106 expose, expose base 102 monocrystalline.
As shown in Figure 6, deposit the 3rd dielectric layer forms sidewall structure 113 by anisotropic etching in the side of gained emitter structure.
As shown in Figure 7, for sheltering, etching extension base 102 in distance oxygen buried layer 201 upper surface 100nm place etching stopping, keeps the silicon layer on the oxygen buried layer 201 to collector region 101, obtains etched area 115 with emitter structure.The silicon layer that keeps is carried out the second doping type to be injected.The main purpose that adopts this scheme is to reduce simultaneously the BC junction capacitance in reduction TED effect.Etching preferably has undercutting to a certain degree, can further reduce outer base area resistance like this.
As shown in Figure 8, selective epitaxial one deck outer base area 120 is in-situ doped on the structure of etching gained.This epitaxial film materials is silicon.Impurity is the second doping type.For reducing outer base area 120 resistance, doping content will be tried one's best high, generally should be at 1E19～1E21cm
-3For the NPN device, dopant material is boron.
Base region surface prepares the layer of metal silicide structural outside.Then prepare contact hole at resulting structures, draw emitter electrode and base electrode.
More than; be preferred embodiment of the present invention only, but protection scope of the present invention is not limited to this, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range that claim was defined.
Claims (9)
1. selective epitaxy outer base area bipolar transistor that comprises oxygen buried layer, it is characterized in that: described transistor comprises the collector region of the first doping type, be positioned at intrinsic base region and oxygen buried layer on the described collector region, be positioned at the emitter on the described base, be positioned at the side wall of described emitter both sides, be positioned at the silicon layer of the second doping type on the described oxygen buried layer, and be positioned at the outer base area on the described silicon layer.
2. the selective epitaxy outer base area bipolar transistor that comprises oxygen buried layer according to claim 1 is characterized in that the part of described outer base area is positioned at the below of described side wall.
3. the selective epitaxy outer base area bipolar transistor that comprises oxygen buried layer according to claim 1 is characterized in that described outer base area produces stress in described base.
4. a selective epitaxy outer base area bipolar transistor tube preparation method that comprises oxygen buried layer is characterized in that, the comprising the steps: at least of described method
4.1 prepare the collector region of the first doping type; Inject formation at described collector region and annotate the oxygen layer, high temperature advances and forms oxygen buried layer;
4.2 the base at resulting structures preparation the second doping type;
4.3 deposit first medium layer on the base;
4.4 offer window at the first medium layer;
4.5 on resulting structures, prepare successively the first doping type polycrystal layer and second medium layer;
4.6 photoetching, the described second medium layer of etching and polycrystal layer form emitter, remove the exposed part of first medium layer;
4.7 deposit the 3rd dielectric layer forms sidewall structure by anisotropic etching in the side of gained emitter structure;
4.8 with the emitter of above-mentioned gained and sidewall structure as sheltering, capped base in the etching resulting structures, etch thicknesses is greater than the thickness of base; Etching stopping during apart from described oxygen buried layer 10nm to 100nm keeps the silicon layer on the described oxygen buried layer, described silicon layer is carried out the second doping type inject;
4.9 adopt in-situ doped selective epitaxial process to prepare the outer base area of the second doping type at resulting structures;
4.10 base region surface prepares the layer of metal silicide structural outside;
4.11 prepare contact hole at resulting structures, draw emitter electrode and base electrode.
5. the selective epitaxy outer base area bipolar transistor tube preparation method that comprises oxygen buried layer according to claim 4 is characterized in that, the material of preparation base is silicon, germanium silicon or carbon dope germanium silicon in the step 4.2.
6. the selective epitaxy outer base area bipolar transistor tube preparation method that comprises oxygen buried layer according to claim 4, it is characterized in that, the first medium layer is compound medium layer in the step 4.3, and described compound medium layer comprises the silicon oxide layer that is deposited on base region surface and is deposited on the silicon nitride layer on silicon oxide layer surface.
7. the selective epitaxy outer base area bipolar transistor tube preparation method that comprises oxygen buried layer according to claim 4 is characterized in that the polycrystal layer in the step 4.5 is polysilicon layer or polycrystalline germanium silicon layer; Dielectric layer is silica or silicon nitride.
8. the selective epitaxy outer base area bipolar transistor tube preparation method that comprises oxygen buried layer according to claim 4 is characterized in that the thickness of etching is between 10nm to 2000nm in the step 4.8; Carry out undercutting to the side wall below during etching base.
9. the selective epitaxy outer base area bipolar transistor tube preparation method that comprises oxygen buried layer according to claim 4, it is characterized in that the outer base area in the step 4.9 uses the preparation of selective epitaxy growing method, the material of outer base area is silicon, or germanium silicon, or carbon dope germanium silicon; The doping content of impurity is at 1E19～1E21cm
-3
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| CN101359682A (en) * | 2008-09-12 | 2009-02-04 | 清华大学 | Self-alignment elevated external base area or heterojunction bipolar transistor and manufacturing method thereof |
| CN101523579A (en) * | 2006-10-05 | 2009-09-02 | 国际商业机器公司 | Local collector implant structure for heterojunction bipolar transistors and method of forming the same |
| US20110309471A1 (en) * | 2010-06-17 | 2011-12-22 | International Business Machines Corporation | Transistor structure with a sidewall-defined intrinsic base to extrinsic base link-up region and method of forming the structure |
| CN102651390A (en) * | 2012-05-16 | 2012-08-29 | 清华大学 | Bipolar transistor with embedded epitaxial outer base region and fabrication method of bipolar transistor |
| CN102709318A (en) * | 2012-05-16 | 2012-10-03 | 清华大学 | Embedded epitaxial external base region bipolar transistor and preparation method thereof |
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- 2012-12-12 CN CN2012105354569A patent/CN103035685A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060113634A1 (en) * | 2003-11-17 | 2006-06-01 | Shahriar Ahmed | Bipolar junction transistor with improved extrinsic base region and method of fabrication |
| CN101523579A (en) * | 2006-10-05 | 2009-09-02 | 国际商业机器公司 | Local collector implant structure for heterojunction bipolar transistors and method of forming the same |
| CN101359682A (en) * | 2008-09-12 | 2009-02-04 | 清华大学 | Self-alignment elevated external base area or heterojunction bipolar transistor and manufacturing method thereof |
| US20110309471A1 (en) * | 2010-06-17 | 2011-12-22 | International Business Machines Corporation | Transistor structure with a sidewall-defined intrinsic base to extrinsic base link-up region and method of forming the structure |
| CN102651390A (en) * | 2012-05-16 | 2012-08-29 | 清华大学 | Bipolar transistor with embedded epitaxial outer base region and fabrication method of bipolar transistor |
| CN102709318A (en) * | 2012-05-16 | 2012-10-03 | 清华大学 | Embedded epitaxial external base region bipolar transistor and preparation method thereof |
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Application publication date: 20130410 |