CN103035684A - Gate structure and manufacturing method thereof - Google Patents
Gate structure and manufacturing method thereof Download PDFInfo
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- CN103035684A CN103035684A CN2012101637662A CN201210163766A CN103035684A CN 103035684 A CN103035684 A CN 103035684A CN 2012101637662 A CN2012101637662 A CN 2012101637662A CN 201210163766 A CN201210163766 A CN 201210163766A CN 103035684 A CN103035684 A CN 103035684A
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Abstract
The invention discloses a gate structure. The gate structure comprises gate oxide formed in a groove, a first layer of polysilicon or amorphous silicon which contains low-concentration phosphor or no phosphor and is on the gate oxide, and a second layer of polysilicon or amorphous silicon which contains high-concentration phosphor and is on the first layer of the polysilicon or amorphous silicon which contains the low-concentration phosphor or no phosphor, wherein the phosphor-doping concentration of the first layer of the polysilicon or amorphous silicon is 0 to 2E20atm/cm<3>, and the phosphor-doping concentration of the second layer of polysilicon is 1.0E20 to 10E20atm/cm<3>. The groove is filled with the second layer of layer of the polysilicon or amorphous silicon. The invention also discloses a manufacturing method of the gate structure. Electric leakage characteristic of the gate structure can be improved and the performance of the appliance can be improved.
Description
Technical field
The present invention relates to the semiconductor integrated circuit field, particularly relate to a kind of grid structure.The invention still further relates to the manufacture method of described grid structure.
Background technology
In present semiconductor technology method, a kind of like this process is arranged, on silicon chip, form first groove, then carry out oxidation, generate layer oxide film as gate oxidation films (following abbreviation " grid oxygen "), regrowth one deck is mixed highly doped polysilicon or the unformed silicon of phosphorus afterwards, fills up whole groove (referring to Fig. 1) with highly doped polysilicon or unformed silicon.After filling up, whole groove returns again quarter, to there be highly doped polysilicon or the unformed silicon at groove place all to carve, and the highly doped polysilicon that stays in groove or unformed silicon just are used as grid, and unformed silicon can become polysilicon through behind the follow-up high-temperature technology.The processing of above-mentioned grid oxygen technique is a kind of monofilm list concentration structure basically.
In order to improve the speed of device, just require to increase the resistance that the concentration of mixing phosphorus in polysilicon or the unformed silicon reduces polysilicon or unformed silicon, but surpass certain concentration when mixing phosphorus, and phosphorous doped polysilicon or unformed silicon are when surpassing certain thickness (because groove requires all to fill up), the surface configuration of returning after carving just has many depressions (referring to Fig. 2), and this depression can be brought the problem of two aspects:
If 1. occur in gate oxidation films near, gate oxidation films so herein will sustain damage at Hui Kezhong, and being recessed in the subsequent technique of polysilicon or unformed silicon also can be brought other problems herein, see through this place such as follow-up implantation affiliation, cause the variation of device performance large, technology stability is poor.
2. when depression occurs in the center of groove, make the original darker depression of ditch groove center become darker, when the grid contact hole drops in the groove, can bring the unstable of contact hole performance, even when generating metal film afterwards, form the cavity, affect performance of devices.
And, utilize monofilm grid structure fabrication device, when the doping content of this monofilm was high, through behind the subsequent technique, leaked electricity easily in the interface of this polysilicon gate-grid oxygen-silicon substrate, and the leakage current characteristic of grid oxygen can not meet the demands in the high performance device design.
In order to overcome the above problems, Chinese utility model patent ZL 02261131.2(Granted publication number: CN 2694476Y, Granted publication day: on April 20th, 2005) disclose a kind of multilayer film project organization, specifically after gate oxidation films is grown up, the one deck of growing up is successively mixed the low polysilicon of phosphorus concentration, one deck and is mixed the much higher crystal silicon of phosphorus concentration, one deck to mix phosphorus concentration low or do not mix the polysilicon of phosphorus.Ground floor is mixed the low polysilicon of phosphorus concentration in that go back to carve the rear surface more smooth, to guarantee near the gate oxidation films depression not occur after carving returning, grid is not sustained damage; The 3rd layer mix phosphorus concentration low or do not mix phosphorus polysilicon to return etching speed low, reduces back the rear cup depth of ditch groove center at quarter, make it when growing up metal film afterwards, not form the cavity.Mix phosphorus concentration and thickness by what adjust first, second layer polysilicon simultaneously, can guarantee to obtain the resistance that is equal to after carving returning.But this patent does not propose concrete research and solution in the electric leakage problem to this grid oxygen.
Chinese invention patent application CN101958342A(application number: 200910057613.8, Shen Qing Publication day: on January 26th, 2011), a kind of multilayer film project organization is disclosed, specifically after gate oxidation films is grown up, it is low or do not mix polysilicon or the unformed silicon of phosphorus that the one deck of growing up is successively mixed phosphorus concentration; One deck is mixed the much higher crystal silicon of phosphorus concentration or unformed silicon.This patent application is helpful to the electric leakage problem of grid oxygen, but in the scheme because the restriction of technique, particularly the unformed silicon of the first tunic deposit can be disclosed by high-temperature process (crystallization that forms certain size affects the effect that anti-carves) before etching is finished, to also not disclosing with the diffusion that better stops the phosphorus in the second layer by some oxides of deposit behind the first tunic.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of grid structure, can improve the leakage current characteristic of grid oxygen, improves performance of devices; The present invention also will provide a kind of manufacture method of described grid structure for this reason.
For solving the problems of the technologies described above, grid structure of the present invention comprises: the grid oxygen that forms in groove; It is low or do not mix polysilicon or the unformed silicon of phosphorus that ground floor on grid oxygen is mixed phosphorus concentration, and the phosphorus concentration of mixing of described ground floor polysilicon or unformed silicon is 0～2E20atm/cm
3The second layer on described ground floor polysilicon or unformed silicon is mixed the much higher crystal silicon of phosphorus concentration or unformed silicon, and this second layer polysilicon or unformed silicon fill up described groove; The phosphorus concentration of mixing of described second layer polysilicon or unformed silicon is 1.0E20～10E20atm/cm
3, preferred 2E20～5E20atm/cm
3
The manufacture method of described grid structure may further comprise the steps:
Step 1, finish etching groove and through after the surface treatment, utilize thermal oxidation to finish the deposit of gate oxidation films, form grid oxygen;
Step 2, carry out ground floor and mix the deposit that phosphorus is low or do not mix polysilicon or the unformed silicon of phosphorus, it is low or do not mix the polysilicon of phosphorus or the phosphorus concentration of mixing of unformed silicon is 0～2E20atm/cm that described ground floor is mixed phosphorus concentration
3
It is low or do not mix polysilicon or the unformed silicon of phosphorus that described grid structure comprises that also the 3rd layer of being positioned on the second layer mixed phosphorus concentration, and the phosphorus concentration of mixing of the 3rd layer of polysilicon or unformed silicon is 0～1E20atm/cm
3
To mix phosphorus concentration low or when not mixing the polysilicon of phosphorus or unformed silicon when comprising the 3rd layer, after carrying out the second layer and mixing the deposit of the much higher crystal silicon of phosphorus concentration or unformed silicon, carry out the 3rd layer and mix the deposit that phosphorus concentration is low or do not mix polysilicon or the unformed silicon of phosphorus, and then utilize dry etching that polysilicon or unformed silicon that described groove both end sides surface needs to remove are all carved, obtain filling up in the groove grid structure of polysilicon or unformed silicon.
The present invention is owing to changed the structure of present semiconductor device gate oxygen, and what directly contact with grid oxygen is to contain the minimum or plain polysilicon of phosphorus concentration or unformed silicon, mixes phosphorus concentration and is less than or equal to 2E20atm/cm
3, by process can so that the silicon that directly contact with grid oxygen to carve the rear surface more smooth returning, do not occur caving in after carving returning guaranteeing near the grid oxygen, minimizing is to the damage of grid oxygen.To contain the minimum or plain polysilicon of phosphorus concentration or unformed silicon owing to what directly contact with grid oxygen simultaneously, the effect that the second layer that also has inhibition to be located thereon is mixed the Impurity Diffusion in the much higher crystal silicon of phosphorus concentration, thereby improve the leakage current characteristic of grid oxygen, improve performance of devices.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 adopts one deck polysilicon or unformed silicon to fill up the schematic diagram of groove in the existing method;
Fig. 2 is by the schematic diagram behind unnecessary polysilicon or the unformed silicon among time removal at quarter Fig. 1;
Fig. 3 is the schematic diagram of embodiment one deposit two-layer polysilicon or unformed silicon on grid oxygen;
Fig. 4 is the schematic diagram after the polysilicon that will need among Fig. 3 to remove or unformed silicon are all carved;
Fig. 5 is the schematic diagram of embodiment two three layers of polysilicon of deposit or unformed silicon on grid oxygen;
Fig. 6 is the schematic diagram after the polysilicon that will need among Fig. 5 to remove or unformed silicon are all carved;
Fig. 7 is the schematic diagram of embodiment three deposit two-layer polysilicon or unformed silicon on grid oxygen;
Fig. 8 is by needing at least the part polysilicon of opening contact hole or the schematic diagram of unformed silicon among photoetching protection Fig. 7;
Fig. 9 is the schematic diagram after the polysilicon that will need among Fig. 7 to remove or unformed silicon are carved;
Figure 10 is grid oxygen leakage current characteristic curve chart.
Embodiment
Embodiment one
Shown in Fig. 3,4, described grid structure comprises: the grid oxygen 4 that forms in groove 3; It is low or do not mix polysilicon or the unformed silicon 50 of phosphorus that ground floor on grid oxygen 4 is mixed phosphorus concentration, and it is low or do not mix the polysilicon of phosphorus or the phosphorus concentration of mixing of unformed silicon 50 is 0～2E20atm/cm that described ground floor is mixed phosphorus concentration
3, when mixing phosphorus concentration for " 0 ", can not mix phosphorus; The thickness of ground floor polysilicon or unformed silicon 50 is 200 dusts～2500 dusts; Mix phosphorus concentration polysilicon or the second layer on the unformed silicon 50 low or that do not mix phosphorus at described ground floor and mix the much higher crystal silicon of phosphorus concentration or unformed silicon 51, the phosphorus concentration of mixing of described second layer polysilicon or unformed silicon 51 is 1.0E20～10E20atm/cm
3The thickness of second layer polysilicon or unformed silicon 51 is determined by the gash depth of device, groove 3 will be filled fully at least.
In above-mentioned grid structure, it is low or not mix polysilicon or unformed silicon 50 etch rate in dry etching of phosphorus relatively slow that ground floor is mixed phosphorus concentration, the rear surface is more smooth return carving, and can guarantee near the grid oxygen depression not occur after carving or depression is very little returning, and reduces the damage to grid oxygen.To mix phosphorus concentration low or do not mix the polysilicon of phosphorus or unformed silicon 50 also has the effect that the second layer on it is mixed the Impurity Diffusion in the much higher crystal silicon of phosphorus concentration or the unformed silicon 51 that suppresses for this ground floor simultaneously, thereby improve the interface state between polysilicon gate-grid oxygen-silicon substrate, improve the leakage current characteristic of grid oxygen, improve performance of devices.The second layer mixes the much higher crystal silicon of phosphorus concentration or unformed silicon 51 is used for obtaining low gate resistance, to satisfy the performance of devices requirement.
Its processing step of the manufacture method of above-mentioned grid structure comprises:
Step 1, in conjunction with shown in Figure 3, finish groove 3 etchings in the N-type epitaxial loayer on silicon substrate (N+ silicon substrate), and through after the surface treatment, utilize thermal oxidation to finish first the deposit of gate oxidation films 4.
Step 2, finish ground floor and mix the deposit that phosphorus concentration is low or do not mix polysilicon or the unformed silicon 50 of phosphorus.
In the manufacture method of above grid structure, behind polysilicon or unformed silicon deposit, the technique of etching can not have before finishing temperature to surpass thermal process more than 550 ℃.
Implement two
Shown in Fig. 5,6, the difference of present embodiment and embodiment one is, after the second layer is mixed the much higher crystal silicon of phosphorus concentration or 51 deposits of unformed silicon (fill up groove or groove fills up in large section), it is low or do not mix the polysilicon of phosphorus or the phosphorus concentration of mixing of 52, the three layers of polysilicon of unformed silicon or unformed silicon 52 is 0～1E20atm/cm that phosphorus concentration is mixed in the 3rd layer of deposit thereon
3The thickness of the 3rd layer of polysilicon or unformed silicon 52 designs according to technological requirement, but generally can obtain positive effect at 1000 dust to 5000 dusts.Identical with embodiment one afterwards, the polysilicon or the unformed silicon that utilize dry etching that the needs of silicon chip surface are removed are all carved, and obtain filling up in the groove grid structure of polysilicon or unformed silicon.At this moment the depression of groove was effectively reduced after etching was finished.When adopting three-decker, time etching speed of the 3rd layer of polysilicon or unformed silicon is low, can reduce back the cup depth of ditch groove center after carving, and obtains back carving the little grid structure of rear surface depression, makes it not form when growing up metal film afterwards the cavity.
Implement three
Shown in Fig. 7-9; the difference of present embodiment and embodiment one is; after the second layer is mixed the much higher crystal silicon of phosphorus concentration or 51 deposits of unformed silicon (filling up groove); before the etching of step 4; coating photoresist 6; to need on second layer polysilicon or unformed silicon 51, protect (referring to Fig. 8) by part polysilicon or the unformed silicon 51 of opening contact hole at least by photoetching; the polysilicon or the unformed silicon that utilize afterwards dry etching that the needs of silicon face are removed; and photoresist 6 all carves (referring to Fig. 9); even the groove central concave was larger after at this moment etching was finished; because polysilicon or unformed silicon upper surface in the groove do not have contact hole, just very little on the impact of device.
Photoresist 6 also can replace with other that form by chemical wet etching silicon (polysilicon or unformed silicon) is had the film of selecting ratio in the present embodiment, such as silica, and silicon nitride, silicon oxynitride or their combination.
Embodiment four
The difference of present embodiment and above-mentioned three embodiment is, after ground floor polysilicon or 50 deposits of unformed silicon, before second layer polysilicon or 51 deposits of unformed silicon, add the very thin silicon oxide film of one deck, its thickness is 10～100 dusts, can be used for the diffusion of the phosphorus of minimizing second layer polysilicon or unformed silicon 51 middle and high concentrations, stop it to be diffused near the performance of devices that affects of grid oxygen.
As shown in figure 10,1 is the grid oxygen leakage current characteristic curve of grid structure of the present invention among the figure, and 2 is the grid oxygen leakage current characteristic curve of single-layer membrane structure, and visible the present invention has improved the leakage current characteristic of grid oxygen.
Manufacture method one preferred embodiment of the grid structure of described multilayer film, groove 3 degree of depth are 1.0～2.0 μ m, and groove 3 width are 0.8～1.3 μ m.At the upper growth N-type epitaxial loayer of N+ silicon substrate (silicon substrate), (also will carry out the grid oxygen characteristic of a sacrificial oxide layer to obtain when needing) carries out oxidation after utilizing deielectric-coating or photoresist to do mask to finish the etching of groove, generate layer oxide film as grid oxygen, then enter the depositing technics of doped polycrystalline silicon:
Film forming scheme: low-pressure chemical vapor phase deposition;
Chemical equation SiH4+PH3 → Si+P+3H2;
Growth pressure 1.85Torr, 520 °～540 ° C of temperature;
Generate not phosphorous doped polysilicon of ground floor, thickness 700～1000 dusts;
Generate the second layer and mix the much higher crystal silicon of phosphorus concentration, it mixes phosphorus concentration is 3E20atm/cm3, thickness 6500～7500 dusts.
The present invention adopts multi-layer film structure to come filling groove, is used as the grid of metal-oxide film-semiconductor field effect transistor (MOSFET) and igbt (IGBT) device etc.In this multilayer film grid structure, owing to adopt the combination of the film of different levels of doping, in guaranteeing the groove that need can obtain under the condition of polycrystalline resistor, what need can also obtain returns surface roughness after carving.
Below through the specific embodiment and the embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.In the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (11)
1. a grid structure comprises: the grid oxygen that forms in groove; It is characterized in that: also being included in ground floor on the grid oxygen, to mix phosphorus concentration low or do not mix polysilicon or the unformed silicon of phosphorus, and it is low or do not mix the polysilicon of phosphorus or the phosphorus concentration of mixing of unformed silicon is 0～2E20atm/cm that described ground floor is mixed phosphorus concentration
3The second layer on described ground floor polysilicon or unformed silicon is mixed the much higher crystal silicon of phosphorus concentration or unformed silicon, and this second layer polysilicon or unformed silicon fill up described groove; The phosphorus concentration of mixing of described second layer polysilicon or unformed silicon is 1.0E20～10E20atm/cm
3
2. grid structure according to claim 1, it is characterized in that: it is low or do not mix polysilicon or the unformed silicon of phosphorus to comprise that also the 3rd layer of being positioned on second layer polysilicon or the unformed silicon mixed phosphorus concentration, and the phosphorus concentration of mixing of the 3rd layer of polysilicon or unformed silicon is 0～1E20atm/cm
3
3. grid structure according to claim 2, it is characterized in that: the thickness of described the 3rd layer of polysilicon or unformed silicon is 1000 dust to 5000 dusts.
4. arbitrary described grid structure according to claim 1-3, it is characterized in that: the phosphorus concentration of mixing of described second layer polysilicon or unformed silicon is 2E20～5E20atm/cm
3
5. arbitrary described grid structure according to claim 1-3, it is characterized in that: the thickness of described ground floor polysilicon or unformed silicon is 200～2500 dusts, and the thickness of described second layer polysilicon or unformed silicon is more than or equal to 2 times of the thickness of ground floor polysilicon or unformed silicon.
6. arbitrary described grid structure is characterized in that: also be included on described ground floor polysilicon or the unformed silicon, and the thickness that is positioned under described second layer polysilicon or the unformed silicon is the silicon oxide film of 10～100 dusts according to claim 1-3.
7. manufacture method of grid structure as claimed in claim 1 may further comprise the steps:
Step 1, finish etching groove and through after the surface treatment, utilize thermal oxidation to finish the deposit of gate oxidation films, form grid oxygen; It is characterized in that, also comprise:
Step 2, carry out ground floor and mix the deposit that phosphorus concentration is low or do not mix polysilicon or the unformed silicon of phosphorus, the phosphorus concentration of mixing of this ground floor polysilicon or unformed silicon is 0～2E20atm/cm
3
Step 3, carry out the deposit that the second layer is mixed the much higher crystal silicon of phosphorus concentration or unformed silicon, the phosphorus concentration of mixing of described second layer polysilicon or unformed silicon is 1.0E20～10E20atm/cm
3, second layer polysilicon or unformed silicon deposit relief polysilicon or unformed silicon fill up described groove;
Step 4, the polysilicon or the unformed silicon that utilize dry etching that groove two side ends surface need to be removed are all carved, and obtain filling up in the groove grid structure of polysilicon or unformed silicon.
8. method as claimed in claim 7 is characterized in that: after step 3 is finished, before step 4 is implemented, also comprise and carry out the 3rd layer to mix phosphorus concentration low or do not mix the step of the deposit of the polysilicon of phosphorus or unformed silicon.
9. method as claimed in claim 7; it is characterized in that: after step 3 is finished; before step 4 is implemented; also comprise the coating photoresist; by photoetching protection at least need to be on second layer polysilicon or unformed silicon part polysilicon or the unformed silicon of opening contact hole; utilize afterwards dry etching will need polysilicon or the unformed silicon of removing, and photoresist is all carved.
10. such as the arbitrary described method of claim 7-9, it is characterized in that: after step 1 is implemented, before step 2 is implemented, be included in also that deposition thickness is the step of the silicon oxide film of 10～100 dusts on described ground floor polysilicon or the unformed silicon.
11. method as claimed in claim 7 is characterized in that: behind second layer polysilicon or unformed silicon deposit, the step 4 dry etching forbids that temperature surpasses the thermal process more than 550 ℃ before finishing.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104241339A (en) * | 2014-10-11 | 2014-12-24 | 丽晶美能（北京）电子技术有限公司 | Semiconductor device structure and production method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060046364A1 (en) * | 2004-08-26 | 2006-03-02 | Mosel Vitelic, Inc. | Method for forming a gate structure through an amorphous silicon layer and applications thereof |
| CN101958342A (en) * | 2009-07-20 | 2011-01-26 | 上海华虹Nec电子有限公司 | Gate structure and manufacturing method thereof |
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- 2012-05-23 CN CN2012101637662A patent/CN103035684A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060046364A1 (en) * | 2004-08-26 | 2006-03-02 | Mosel Vitelic, Inc. | Method for forming a gate structure through an amorphous silicon layer and applications thereof |
| CN101958342A (en) * | 2009-07-20 | 2011-01-26 | 上海华虹Nec电子有限公司 | Gate structure and manufacturing method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104241339A (en) * | 2014-10-11 | 2014-12-24 | 丽晶美能（北京）电子技术有限公司 | Semiconductor device structure and production method thereof |
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