CN103035564A - Semiconductor device and production method thereof - Google Patents
Semiconductor device and production method thereof Download PDFInfo
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- CN103035564A CN103035564A CN201110294600XA CN201110294600A CN103035564A CN 103035564 A CN103035564 A CN 103035564A CN 201110294600X A CN201110294600X A CN 201110294600XA CN 201110294600 A CN201110294600 A CN 201110294600A CN 103035564 A CN103035564 A CN 103035564A
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Abstract
Disclosed are a semiconductor device and a production method thereof. The method comprises steps of providing a substrate, forming a dielectric layer on the substrate, forming a metal interconnection line in the dielectric layer, forming a first barrier layer on the metal interconnection line, siliconizing the surface of the first barrier layer to form a first high silicon barrier layer, forming a second barrier layer on the first high silicon barrier layer, and siliconizing the surface of the second barrier layer to form a second high silicon barrier layer. Correspondingly, the invention also provides the semiconductor device. The semiconductor device comprises the substrate, the dielectric layer on the substrate, the metal interconnection line formed in the dielectric layer, the first barrier layer, the first high silicon barrier layer, the second barrier layer and the second high silicon barrier layer, wherein the first barrier layer, the first high silicon barrier layer, the second barrier layer and the second high silicon barrier layer are formed on the metal interconnection line sequentially. By the aid of the method and the device, the Proportion Integration Differentiation (PID) problem is solved.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of semiconductor device and manufacture method thereof.
Background technology
Along with the development of semiconductor technology, integrated circuit is towards the future development of high integration.The requirement of high integration makes the live width of semiconductor device more and more less, and the reducing of live width had higher requirement to the formation technique of integrated circuit.
Semiconductor device generally includes multiple layer metal layer and multilayer dielectricity layer, is formed with the interconnection line that is communicated with described metal level in the described dielectric layer.
For the interconnection line demand after satisfying element and dwindling, the usually a kind of method of employing of very large scale integration technology institute that is designed to of two-layer and two-layer above multiple layer metal interconnection line.The process that semiconductor is made is normally at processing line leading portion (front end of line, FEOL) form MOS transistor, and the dielectric layer between the orlop in MOS transistor and the interconnection layer, form the design of described multiple layer metal interconnection line more than two-layer and two-layer at processing line back segment (back end of line, BEOL).
A kind of method that forms metal interconnecting layer in semiconductor device for example in being the Chinese patent of CN1270371C, notification number is disclosed.
Referring to figs. 1 to Fig. 2, show the schematic diagram of semiconductor device one embodiment of prior art BEOL manufacture method formation.
At first, by cmp (Chemical Mechanical Polishing, CMP) planarization the first metal layer (not shown).
As shown in Figure 1, form successively barrier layer 10, low K dielectric layer 11 on the first metal layer after finishing the CMP processing, wherein barrier layer 10 is used for preventing the diffusion of metal layer material, described low K dielectric layer 11 also is used for making mutually insulated between the first metal layer and the second metal level to be formed, particularly, the material on described barrier layer 10 comprises the carborundum (Nitrogen Doped Silicon Carbon, NDC) of nitrating.
As shown in Figure 2, in low K dielectric layer 11, form groove 12 by method for plasma etching, in described etching process with described barrier layer 10 as etching stopping layer, in described groove 12, fill metal material more afterwards, to form the second metal level.
Yet in the plasma etching process, often be attended by the bombardment of high-octane particle and photon, these radiation have comprised ion, electronics, ultraviolet ray and faint X ray, when high energy particle strikes barrier layer 10, meeting is 10 generation charge accumulateds on the barrier layer, and then cause easily static collapse phenomenon, be commonly referred to plasma damage (plasma induce damage, PID).
Summary of the invention
The technical problem that the present invention solves provides a kind of semiconductor device and manufacture method thereof that reduces plasma damage.
In order to address the above problem, the invention provides a kind of manufacture method of semiconductor device, described manufacture method comprises: substrate is provided, forms dielectric layer at substrate, form metal interconnecting wires in dielectric layer; Form the first barrier layer at described metal interconnecting wires; Silicidation is carried out on surface to described the first barrier layer, forms the first Silicon-rich barrier layer; Form the second barrier layer on described the first Silicon-rich barrier layer; Silicidation is carried out on surface to described the second barrier layer, forms the second Silicon-rich barrier layer.
Alternatively, described the first barrier layer is not identical with the dielectric constant on the second barrier layer.
Alternatively, described the first barrier layer is identical with the dielectric constant on the second barrier layer.
Alternatively, the dielectric constant on described the first barrier layer is greater than the dielectric constant on described the second barrier layer.
Alternatively, the material on described the first barrier layer is silicon nitride, and the material on the second barrier layer is the carborundum of nitrating.
Alternatively, the step on described metal interconnecting wires formation the first barrier layer comprises that the method by plasma activated chemical vapour deposition forms described silicon nitride.
Alternatively, described method by the plasma activated chemical vapour deposition step that forms described silicon nitride comprises: the power of the radiofrequency signal that loads in the described plasma activated chemical vapour deposition process is less than or equal to 50W.
Alternatively, the thickness on described the first barrier layer exists
Scope in.
Alternatively, silicidation is carried out on described surface to described the first barrier layer, and the step that forms the first Silicon-rich barrier layer comprises by the method for plasma activated chemical vapour deposition carries out described silicidation.
Alternatively, described method by the plasma activated chemical vapour deposition step of carrying out described silicidation comprises: pass into siliceous reacting gas to plasma CVD device.
Alternatively, the step that described method by plasma activated chemical vapour deposition is carried out described silicidation comprises: the radiofrequency signal power that loads in the described plasma activated chemical vapour deposition process is in the scope of 50～500W, the reacting gas that passes into to plasma CVD device comprises silane, pass into the flow of silane in the scope of 100～1000sccm, the air pressure of plasma CVD device is in the scope of 2～7torr.
Alternatively, the thickness on described the first Silicon-rich barrier layer exists
Scope in.
Alternatively, the material on described the second barrier layer comprises the carborundum of nitrating, and the described step that forms the second barrier layer on described the first Silicon-rich barrier layer comprises that the method by chemical vapour deposition (CVD) forms described the second barrier layer.
Alternatively, the thickness on described the second barrier layer exists
Scope in.
Alternatively, silicidation is carried out on the surface on described the second barrier layer, the step that forms the second Silicon-rich barrier layer comprises by the method for plasma activated chemical vapour deposition carries out described silicidation.
Alternatively, described method by the plasma activated chemical vapour deposition step of carrying out described silicidation comprises: pass into siliceous reacting gas to plasma CVD device.
Alternatively, the step that described method by plasma activated chemical vapour deposition is carried out described silicidation comprises: the radiofrequency signal power that loads in the described plasma activated chemical vapour deposition process is in the scope of 50～500W, the reacting gas that passes into to plasma CVD device comprises silane, pass into the flow of silane in the scope of 100～1000sccm, the air pressure of plasma CVD device is in the scope of 2～7torr.
Alternatively, the thickness on described the second Silicon-rich barrier layer exists
Scope in.
Correspondingly, the present invention also provides a kind of semiconductor device, comprising: substrate, be positioned at the dielectric layer on the substrate, and be formed at the metal interconnecting wires in the dielectric layer; Be positioned at successively the first barrier layer, the first Silicon-rich barrier layer, the second barrier layer, the second Silicon-rich barrier layer on the metal interconnecting wires.
Alternatively, described the first barrier layer is silicon nitride.
Alternatively, the thickness on described the first barrier layer exists
Scope in.
Alternatively, the thickness on described the first Silicon-rich barrier layer exists
Scope in.
Alternatively, the material on described the second barrier layer is the carborundum of nitrating.
Alternatively, the thickness on described the second barrier layer exists
Scope in.
Alternatively, the thickness on described the second Silicon-rich barrier layer exists
Scope in.
Compared with prior art, the present invention has the following advantages:
1. silicone content is higher in the first Silicon-rich barrier layer, the second Silicon-rich barrier layer, and conductive effect is good, can make the electrostatic charge homogenizing, thereby reduces static collapse phenomenon; In addition, the energy of radiation can partly be absorbed by silicon materials in the plasma etching process, the electric charge that can reduce like this on the first barrier layer, the second barrier layer accumulates, and then reduce the PID problem.
2. in the possibility, the first barrier layer is different with the dielectric constant on the second barrier layer, by changing the thickness on the first barrier layer and the second barrier layer, changes the dielectric constant of multilayer barrier layer structure, thereby improves the scope of application of multilayer barrier layer structure.
3. in the possibility, the material on the first barrier layer is silicon nitride, the material on the second barrier layer is the carborundum of nitrating, because the dielectric constant of silicon nitride is greater than the dielectric constant of the carborundum of nitrating, compare with the barrier layer of the carbofrax material that only has nitrating like this, as long as select the less silicon nitride of thickness just can realize identical dielectric constant, thereby can reduce thickness.
Description of drawings
Fig. 1 to Fig. 2 is the side schematic view of semiconductor device one embodiment that forms of the manufacture method of prior art semiconductor device;
Fig. 3 is the schematic flow sheet of manufacture method one execution mode of semiconductor device of the present invention;
Fig. 4 to Fig. 8 is the side schematic view of semiconductor device one embodiment that forms of the manufacture method of semiconductor device of the present invention.
Embodiment
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization in the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public implementation.
Secondly, the present invention utilizes schematic diagram to be described in detail, and when the embodiment of the invention was described in detail in detail, for ease of explanation, described schematic diagram was example, and it should not limit the scope of protection of the invention at this.
In order to solve the problem of prior art, the invention provides a kind of manufacture method of semiconductor device.With reference to figure 3, show the schematic flow sheet of method, semi-conductor device manufacturing method one execution mode of the present invention, described manufacture method comprises:
Step S1 provides substrate, forms dielectric layer at substrate, forms metal interconnecting wires in dielectric layer;
Step S2 forms the first barrier layer at described metal interconnecting wires;
Step S3 carries out silicidation to the surface on described the first barrier layer, forms the first Silicon-rich barrier layer;
Step S4 forms the second barrier layer on described the first Silicon-rich barrier layer;
Step S5 carries out silicidation to the surface on described the second barrier layer, forms the second Silicon-rich barrier layer.
Below in conjunction with the drawings and specific embodiments technical scheme of the present invention is described further.
Show the side schematic view of semiconductor device one embodiment that method, semi-conductor device manufacturing method of the present invention forms with reference to figure 4 to Fig. 8, present embodiment is take BEOL as example, but the present invention is not restricted to this, can also be other process sections.
As shown in Figure 4, provide substrate 100, the material of described substrate 100 can be monocrystalline silicon or single-crystal silicon Germanium, perhaps monocrystalline carbon doped silicon; Perhaps can also comprise other material, the present invention does not limit this.
In addition, be formed with the device architecture (not shown) in the described substrate 100, described device architecture can be the device architecture that forms in the semiconductor FEOL, such as MOS transistor etc.
Form dielectric layer 101 at substrate 100, described dielectric layer 101 is used for insulation, and in the present embodiment, described dielectric layer 101 can be low K dielectric layer (the dielectric coefficient scope is 3.9～2.8), and the material of described low K dielectric layer is SiO
2, among SiOF, SiCOH, SiO, SiCO, the SiCON one or more.
Described dielectric layer 101 can also be ultralow K dielectric layer (the dielectric coefficient scope is 2.5～2.8), and described ultralow K dielectric material is carbonado (Black Diamond, BD) etc.
Described dielectric layer 101 can also be other materials, but the present invention is not restricted to this.
In described dielectric layer 101, form groove, and in described groove, fill metal material, form metal interconnecting wires 102.
As shown in Figure 5, on described dielectric layer 101 and metal interconnecting wires 102 formation the first barrier layer 103, follow-up on 103 surperficial the first Silicon-rich barrier layers that form, described the first barrier layer, on the second barrier layer of the first barrier layer 103 formation, in the second Silicon-rich barrier layer of described the second barrier layer surface formation composition multilayer barrier layer structure.
Be arranged in described multilayer barrier layer structural top the second Silicon-rich barrier layer, be positioned at described multilayer barrier layer structure middle part the content of the first Silicon-rich barrier layer silicon higher, on the one hand, because silicon is that semi-conducting material can conduct electricity, when in follow-up plasma etching, in described multilayer barrier layer structure, forming the electrostatic charge accumulation, described the first Silicon-rich barrier layer, the second Silicon-rich barrier layer can make the electrostatic charge homogenizing, thereby reduce the occurrence probability of static collapse phenomenon; In addition, the energy of radiation can partly be absorbed by silicon materials in the plasma etching process, the electric charge that can reduce like this on the first barrier layer, the second barrier layer accumulates, and then reduce the PID problem.
In the present embodiment, the material on described the first barrier layer 103 is silicon nitride, and the dielectric constant of silicon nitride is larger, and good insulating, compactness height can play the effect of well barrier metal diffusion.
In the present embodiment, the method by plasma activated chemical vapour deposition forms described silicon nitride.
In the present embodiment, the thickness on described the first barrier layer 103 exists
Scope in.
Need to prove, also can form plasma in plasma activated chemical vapour deposition, high-octane plasma also forms accumulation of static electricity on the surface on the first barrier layer 103 easily.Therefore, preferably, in the plasma activated chemical vapour deposition process, adopt lower powered radiofrequency signal.The power of the radiofrequency signal that loads in the plasma activated chemical vapour deposition process particularly, is less than or equal to 50W.
As shown in Figure 6, after forming the first barrier layer 103, silicidation is carried out on the first barrier layer 103, herein, the implication of described silicidation is to improve the content of silicon in 103 materials of the first barrier layer.Particularly, form described the first barrier layer 103 by plasma activated chemical vapour deposition after, increase the concentration of reacting gas siliceous in the plasma CVD device, to increase the content of silicon, form the first Silicon-rich barrier layer 104.
In the present embodiment, the material on described the first barrier layer 103 is silicon nitride.After the deposition of finishing the first barrier layer 103, in the reaction chamber of plasma activated chemical vapour deposition, pass into silane, the flow of silane is in the scope of 100～1000sccm, make the interior air pressure of reaction chamber in the scope of 2～7torr, the radiofrequency signal power that loads in the described plasma activated chemical vapour deposition process is in the scope of 50～500W.
Form like this first Silicon-rich barrier layer 104 on the surface on the first barrier layer 103, in the present embodiment, the thickness on described the first Silicon-rich barrier layer 104 exists
Scope in.
After the deposition of finishing the first barrier layer 103, need not to change reaction chamber, realize in position silicidation, simplified processing step.
As shown in Figure 7, form the second barrier layer 105 on described the first Silicon-rich barrier layer 104, in the present embodiment, the material on described the second barrier layer 105 is the carborundum of nitrating.
Particularly, can form by the method for chemical vapour deposition (CVD) the carborundum of described nitrating.Concrete process conditions are same as the prior art, do not repeat them here.
The thickness on described the second barrier layer 105 exists
Scope in.
The dielectric constant of the carborundum of nitrating can change by the thickness that changes the first barrier layer 103 and the second barrier layer 105 dielectric constant of multilayer barrier layer structure less than the dielectric constant of silicon nitride, thereby improves the scope of application of multilayer barrier layer structure.
In addition, the dielectric constant of silicon nitride is compared with the barrier layer of the carbofrax material that only has nitrating like this greater than the dielectric constant of the carborundum of nitrating, as long as select the less silicon nitride of thickness just can realize identical dielectric constant.Thereby can reduce the thickness of multilayer barrier layer structure.
As shown in Figure 8, silicidation is carried out on the surface on described the second barrier layer 105, herein, the implication of described silicidation is to improve the content of silicon in 105 materials of the second barrier layer.Particularly, form described the second barrier layer 105 by plasma activated chemical vapour deposition after, increase the concentration of reacting gas siliceous in the plasma CVD device, to increase the content of silicon, form the second Silicon-rich barrier layer 106.
In the present embodiment, the material on described the second barrier layer 105 is the carborundum of nitrating.After the deposition of finishing the second barrier layer 105, in the reaction chamber of plasma activated chemical vapour deposition, pass into silane, the flow of silane is in the scope of 100～1000sccm, make the interior air pressure of reaction chamber in the scope of 2～7torr, the radiofrequency signal power that loads in the described plasma activated chemical vapour deposition process is in the scope of 50～500W.
Form the second Silicon-rich barrier layer 106 on 105 surfaces, the second barrier layer like this, in the present embodiment, the thickness on described the secondth Silicon-rich barrier layer 106 exists
Scope in.
Like this, after the deposition of finishing the second barrier layer 105, need not to change reaction chamber, realize in position silicidation, simplified processing step.
So far finished the manufacturing process of multilayer barrier layer structure, the follow-up processing step that forms dielectric layer, is arranged in the metal interconnecting wires etc. of dielectric layer that also is included on the multilayer barrier layer structure, the using plasma etching method forms groove in dielectric layer usually in the process that forms metal interconnecting wires.
In the plasma etching process, high energy particle strikes the multilayer barrier layer, owing to be positioned at the second Silicon-rich barrier layer 106 of described multilayer barrier layer structural top, the content of the first Silicon-rich barrier layer 104 silicon that is arranged in described multilayer barrier layer structure middle part is higher, on the one hand, because silicon is that semi-conducting material can conduct electricity, when in follow-up plasma etching, in described multilayer barrier layer structure, forming the electrostatic charge accumulation, described the first Silicon-rich barrier layer 106, the second Silicon-rich barrier layer 106 can make the electrostatic charge homogenizing, thereby reduces the occurrence probability of static collapse phenomenon; In addition, the energy of radiation can partly be absorbed by silicon materials in the plasma etching process, the electric charge that can reduce like this on the first barrier layer 103, the second barrier layer 105 accumulates, and then reduce the PID problem.
Need to prove, in above-described embodiment take the first barrier layer as silicon nitride, the second barrier layer is that the carborundum of nitrating is example, but the present invention is not restricted to this, can also be that the first barrier layer is the carborundum of nitrating, the second barrier layer is silicon nitride, and those skilled in the art can correspondingly revise, be out of shape and replace according to above-described embodiment.
Need to prove that also in above-described embodiment, the material on described the first barrier layer and the second barrier layer is not identical, in other embodiments, described the first barrier layer can also be identical with ground, the second barrier layer material, and for example, the first barrier layer and the second barrier layer are the carborundum of nitrating.
The present invention also provides a kind of semiconductor device, please continue with reference to figure 8, shows the schematic diagram of semiconductor device one embodiment of the present invention.Present embodiment is still take BEOL as example, but the present invention is not restricted to this.
Described semiconductor device comprises: substrate 100, be positioned at the dielectric layer 101 on the substrate 100, and be formed at the metal interconnecting wires 102 in the dielectric layer 101; Be positioned at successively the first barrier layer 103, the first Silicon-rich barrier layer 104, the second barrier layer 105, the second Silicon-rich barrier layer 106 on the metal interconnecting wires 102.Wherein,
The material of described substrate 100 can be monocrystalline silicon or single-crystal silicon Germanium, perhaps monocrystalline carbon doped silicon.Be formed with the device architecture (not shown) in the described substrate 100, described device architecture can be MOS transistor etc.
Described the first barrier layer 103 is silicon nitride, and the thickness on described the first barrier layer 103 exists
Scope in.
Described the first Silicon-rich barrier layer 104 is the higher silicon nitride of silicone content, and the thickness on described the first Silicon-rich barrier layer 104 exists
Scope in.
The material on described the second barrier layer 105 is the carborundum of nitrating, and the thickness on described the second barrier layer 105 exists
Scope in.
Described the second Silicon-rich barrier layer 106 is the carborundum of the higher nitrating of silicone content, and the thickness on described the second Silicon-rich barrier layer 106 exists
Scope in.
Need to prove, above-described embodiment all describes as an example of BEOL example, but the present invention is not restricted to this, can also be FEOL in other embodiments, also can the using plasma etch process when in FEOL, forming the metal plug draw described each utmost point of metal-oxide-semiconductor, described plasma etch process also causes the PID problem easily, can be before carrying out plasma etch process, form multilayer barrier layer structure, to reduce the PID problem.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (25)
1. the manufacture method of a semiconductor device is characterized in that, comprising:
Substrate is provided, forms dielectric layer at substrate, in dielectric layer, form metal interconnecting wires;
Form the first barrier layer at described metal interconnecting wires;
Silicidation is carried out on surface to described the first barrier layer, forms the first Silicon-rich barrier layer;
Form the second barrier layer on described the first Silicon-rich barrier layer;
Silicidation is carried out on surface to described the second barrier layer, forms the second Silicon-rich barrier layer.
2. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, described the first barrier layer is not identical with the dielectric constant on the second barrier layer.
3. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, described the first barrier layer is identical with the dielectric constant on the second barrier layer.
4. the manufacture method of semiconductor device as claimed in claim 2 is characterized in that, the dielectric constant on described the first barrier layer is greater than the dielectric constant on described the second barrier layer.
5. the manufacture method of semiconductor device as claimed in claim 4 is characterized in that, the material on described the first barrier layer is silicon nitride, and the material on the second barrier layer is the carborundum of nitrating.
6. the manufacture method of semiconductor device as claimed in claim 5 is characterized in that, the step that forms the first barrier layer at described metal interconnecting wires comprises: the method by plasma activated chemical vapour deposition forms described silicon nitride.
7. the manufacture method of semiconductor device as claimed in claim 6, it is characterized in that the step that described method by plasma activated chemical vapour deposition forms described silicon nitride comprises: the power of the radiofrequency signal that loads in the described plasma activated chemical vapour deposition process is less than or equal to 50W.
8. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the thickness on described the first barrier layer exists
Scope in.
9. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, silicidation is carried out on described surface to described the first barrier layer, and the step that forms the first Silicon-rich barrier layer comprises: the method by plasma activated chemical vapour deposition is carried out described silicidation.
10. the manufacture method of semiconductor device as claimed in claim 9, it is characterized in that the step that described method by plasma activated chemical vapour deposition is carried out described silicidation comprises: pass into siliceous reacting gas to plasma CVD device.
11. the manufacture method of semiconductor device as claimed in claim 10, it is characterized in that, the step that described method by plasma activated chemical vapour deposition is carried out described silicidation comprises: the radiofrequency signal power that loads in the described plasma activated chemical vapour deposition process is in the scope of 50～500W, the reacting gas that passes into to plasma CVD device comprises silane, pass into the flow of silane in the scope of 100～1000sccm, the air pressure of plasma CVD device is in the scope of 2～7torr.
12. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the thickness on described the first Silicon-rich barrier layer exists
Scope in.
13. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, the material on described the second barrier layer comprises the carborundum of nitrating, and the described step that forms the second barrier layer on described the first Silicon-rich barrier layer comprises: the method by chemical vapour deposition (CVD) forms described the second barrier layer.
14. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the thickness on described the second barrier layer exists
Scope in.
15. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, silicidation is carried out on surface to described the second barrier layer, and the step that forms the second Silicon-rich barrier layer comprises: the method by plasma activated chemical vapour deposition is carried out described silicidation.
16. the manufacture method of semiconductor device as claimed in claim 15, it is characterized in that the step that described method by plasma activated chemical vapour deposition is carried out described silicidation comprises: pass into siliceous reacting gas to plasma CVD device.
17. the manufacture method of semiconductor device as claimed in claim 16, it is characterized in that, the step that described method by plasma activated chemical vapour deposition is carried out described silicidation comprises: the radiofrequency signal power that loads in the described plasma activated chemical vapour deposition process is in the scope of 50～500W, the reacting gas that passes into to plasma CVD device comprises silane, pass into the flow of silane in the scope of 100～1000sccm, the air pressure of plasma CVD device is in the scope of 2～7torr.
18. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the thickness on described the second Silicon-rich barrier layer exists
Scope in.
19. a semiconductor device is characterized in that, comprising:
Substrate is positioned at the dielectric layer on the substrate, is formed at the metal interconnecting wires in the dielectric layer;
Be positioned at successively the first barrier layer, the first Silicon-rich barrier layer, the second barrier layer, the second Silicon-rich barrier layer on the metal interconnecting wires.
20. semiconductor device as claimed in claim 19 is characterized in that, described the first barrier layer is silicon nitride.
21. semiconductor device as claimed in claim 19 is characterized in that, the thickness on described the first barrier layer exists
Scope in.
22. semiconductor device as claimed in claim 19 is characterized in that, the thickness on described the first Silicon-rich barrier layer exists
Scope in.
23. semiconductor device as claimed in claim 19 is characterized in that, the material on described the second barrier layer is the carborundum of nitrating.
24. semiconductor device as claimed in claim 19 is characterized in that, the thickness on described the second barrier layer exists
Scope in.
25. semiconductor device as claimed in claim 19 is characterized in that, the thickness on described the second Silicon-rich barrier layer exists
Scope in.
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| CN104752400A (en) * | 2013-12-31 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Interconnection dielectric layer, manufacturing method thereof and semiconductor device thereof |
| CN104752400B (en) * | 2013-12-31 | 2019-06-04 | 中芯国际集成电路制造(上海)有限公司 | Connected medium layer, its production method and the semiconductor devices including it |
| CN109166821A (en) * | 2018-08-28 | 2019-01-08 | 武汉新芯集成电路制造有限公司 | The forming method on barrier layer, the forming method of three-dimensional integrated device and wafer |
| CN109166821B (en) * | 2018-08-28 | 2020-02-21 | 武汉新芯集成电路制造有限公司 | Forming method of barrier layer, forming method of three-dimensional integrated device and wafer |
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| CN103035564B (en) | 2015-03-11 |
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