CN103022350A - Memory resistor and production method thereof - Google Patents
Memory resistor and production method thereof Download PDFInfo
- Publication number
- CN103022350A CN103022350A CN2012105871673A CN201210587167A CN103022350A CN 103022350 A CN103022350 A CN 103022350A CN 2012105871673 A CN2012105871673 A CN 2012105871673A CN 201210587167 A CN201210587167 A CN 201210587167A CN 103022350 A CN103022350 A CN 103022350A
- Authority
- CN
- China
- Prior art keywords
- layer
- separator
- resistance unit
- preparation
- prepare
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention discloses a memory resistor. The memory resistor comprises a substrate layer. Multiple isolating layers are arranged above the substrate layer. A memory resistance unit is arranged between each two adjacent isolating layers. Each memory resistance unit comprises two mobile ion barrier layers and a planar electrode layer between the mobile ion barrier layers. The memory resistor further comprises a top electrode etching groove formed by etching from the topmost isolating layer to the bottommost isolating layer. The surface of the top electrode etching groove and the surface of the topmost isolating layer are covered with an electrolyte layer. A top electrode is arranged in the top electrode etching groove. The memory resistor further comprises a plurality of bottom electrodes formed by etching from the electrolyte layer covering the surface of the topmost isolating layer to the planar electrode layers of the memory resistance units. The invention further provides a production method of the memory resistor. The process of the three-dimensional memory resistor in the vertical structure is simplified, and the technology of mobile metal ion barrier layers solves the problem of mobile ion pollution.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of memristor spare of three-dimensional structure.
Background technology
Memristor (Memristor) is the 4th kind of basic circuit element that is independent of outside resistance, electric capacity and the inductance, utilizes its unique resistance memory function, can realize simultaneously multi-system computing and multidigit memory function in the individual devices unit.1971, professor Cai Shaotang of Berkeley predicted the existence except memristor in theory.2008, the HP Lab researcher utilized the TiO2 oxide material to prepare the memristor antetype device.Memristor spare shows the non-linear current voltage characteristic, possesses the resistance memory function, has very large application potential at aspects such as high density storage, reconfigurable logic circuit and neuron chips.Utilize the non-linear electrology characteristic of memristor spare, can realize two even more resistance state in memristor, the conversion between the different resistance states can realize by device being applied external bias.Can obtain a plurality of Resistance states by apply suitable bias voltage in the resistive process, namely memory cell can realize the storage of a plurality of information.
Show at present the material of recalling the resistance characteristic and mainly contain two classes, a class is oxide material TiO2, TaOx etc., and the resistive mechanism of these materials is relevant with the distribution character of oxygen room in oxide material; Another kind of is solid electrolyte material such as GeTe etc., and the resistive mechanism of these materials is closely related with the redox effect of metal ion in solid electrolyte.
The structure of memristor spare is the metal/change resistance layer of plane/metal sandwich structure normally.Utilize the memory technology of three-dimensional structure, can significantly improve the storage density of memory, improve the integration density of integrated circuit, therefore be subject to researcher's attention.Owing in the device of three-dimensional structure, usually comprise multi-layer film structure, and for the memristor spare based on solid dielectric, movably the diffusion of metal ion between thin layer will affect the performance of memristor.
Summary of the invention
The technical problem that (one) will solve
The technical problem to be solved in the present invention is: the three-dimensional structure process complexity that faces based on the memristor of solid electrolyte material and the problem of movable metal ion pollution.
(2) technical scheme
For addressing the above problem, one aspect of the present invention provides a kind of memristor spare, described memristor spare comprises substrate layer, on the described substrate layer multi-layer isolation layer is arranged, comprise between described every two-layer separator that one deck recalls the resistance unit, describedly recall the resistance unit and comprise two-layer mobile ion barrier layer and middle plane electrode layer; Described memristor spare also comprises the top electrode etching groove that is etched to the orlop separator from the separator of the superiors; The surface coverage of described top electrode etching groove and the superiors' separator has dielectric substrate; Be provided with top electrode in the described top electrode etching groove; Described memristor spare comprises that also the dielectric substrate that covers from the superiors' insulation surface respectively is etched to the plane electrode layer of respectively recalling the resistance unit and a plurality of hearth electrodes that form.
Preferably, the number of plies of described separator is three layers, i.e. the first separator, and the second separator and the 3rd separator, the described number of plies of recalling the resistance unit is two-layer, namely first recalls resistance unit and second and recalls the resistance unit.
Preferably, described substrate layer is Si or Si/SiO
2Layer, described Si/SiO
2Layer refers to cover one deck SiO2 film at the Si layer, and described separator is Si
3N
4Layer, described mobile ion barrier layer is TaN layer or TiN layer, described plane electrode layer is made by the reaction electrode material, for example Ag layer or Cu layer, described dielectric substrate is GeTe layer or GeSe layer, described top electrode is Pd electrode or Pt electrode.
Preferably, described separator is 100nm, and described mobile ion barrier layer is 20nm, and described plane electrode layer is 20nm.
The present invention has proposed a kind of preparation method of memristor spare on the other hand, may further comprise the steps S1-S12:
S1: at first prepare substrate layer;
S2: at substrate layer preparation the first separator;
S3: the lower floor mobile ion barrier layer of recalling the resistance unit in the first separator preparation first;
S4: the plane electrode layer of recalling the resistance unit in first lower floor's mobile ion barrier layer preparation first of recalling the resistance unit;
S5: the mobile ion barrier layer, upper strata of recalling the resistance unit in the first plane electrode layer preparation first of recalling the resistance unit;
S6: prepare the second separator on the first mobile ion barrier layer, upper strata of recalling the resistance unit;
S7: one or many repeating step S3-S6, prepare other one or more layers recall the resistance unit and on separator;
S8: utilize photoetching and etching technics, be etched to undermost separator from the separator of the superiors, form the top electrode etching groove;
S9: at the top electrode etching groove that forms and the surface coverage dielectric substrate of the superiors' separator;
S10: preparation vertical electrode layer in the top electrode etching groove;
S11: because step S10 is when preparation vertical electrode layer, also be capped the vertical electrode layer material on the superiors' separator outside the top electrode etching groove, utilize the vertical electrode layer material on the electrochemical polish CMP technique removal the superiors separator, only stay the vertical top electrode material in the top electrode etching groove, form the top electrode with vertical stratification;
S12: one or many utilizes photoetching and etching technics, and the dielectric substrate that covers from the superiors' insulation surface respectively is etched to the plane electrode layer of respectively recalling the resistance unit, forms one or more hearth electrodes.
Preferably, described step S2, S6, S7 utilize the standby separator of plasma reinforced chemical vapour deposition PECVD legal system; Described step S3, S5, S7 utilize reactive sputtering to prepare the mobile ion barrier layer; Described step S4, S7 utilize evaporation to prepare the plane electrode layer; Described step S10 utilizes sputtering method to prepare the vertical electrode layer.
Preferably, described step S1 selects Si/SiO
2The preparation substrate layer; Described step S2, S6, S7 utilize Si
3N
4The preparation separator; Described step S3, S5, S7 utilize TaN to prepare the mobile ion barrier layer; Described step S4, S7 utilize Ag or Cu to prepare the plane electrode layer; Described step S9 utilizes GeTe or GeSe to prepare dielectric substrate; Described step S10 utilizes Pd or Pt to prepare the vertical electrode layer.
Preferably, the separation layer thickness of described step S2, S6, S7 preparation is 100nm, and the mobile ion barrier layer thickness of described step S3, S5, S7 preparation is 20nm, and the plane electrode layer thickness of described step S4, S7 preparation is 20nm.
Preferably, described step S7 repeats a step S3-S6, obtains second and recalls resistance unit and the 3rd separator.
(3) beneficial effect
The present invention is directed to the problem that process complexity and mobile ion based on the three-dimensional memristor spare of solid electrolyte material pollute, a kind of memristor spare of vertical stratification has been proposed, simplified the technique of three-dimensional memristor spare, adopt simultaneously movable metal ion barrier technology, effectively solve the mobile ion pollution problem.
Description of drawings
Fig. 1 is the structural representation of the memristor spare of the embodiment of the invention;
Fig. 2 is the preparation flow artwork of the memristor spare of the embodiment of the invention.
Embodiment
That the present invention is described in detail is as follows below in conjunction with drawings and Examples.
The three-dimensional memristor spare based on the vertical stratification of solid electrolyte material that the present invention proposes, the array that utilizes this vertical storage structure easily to realize three-dimensional memristor spare is integrated, increases simultaneously the mobile ion barrier layer to reduce movable metal ion to the impact of memristor spare characteristic.
The memristor spare that the embodiment of one aspect of the present invention provides comprises substrate layer, and the multi-layer isolation layer on the substrate layer comprises between described every two-layer separator that one deck recalls the resistance unit, describedly recalls the resistance unit and comprises two-layer mobile ion barrier layer and middle plane electrode layer; Described memristor spare also comprises the top electrode etching groove that is etched to the orlop separator from the separator of the superiors; The surface coverage of described top electrode etching groove and the superiors' separator has dielectric substrate; Be provided with top electrode in the described top electrode etching groove; Described memristor spare comprises that also the dielectric substrate that covers from the superiors' insulation surface respectively is etched to the plane electrode layer of respectively recalling the resistance unit and a plurality of hearth electrodes that form.
In one embodiment of the invention, the number of plies of described separator is three layers, namely comprises the first separator, the second separator and the 3rd separator, described recall the resistance unit the number of plies be two-layer, namely first recall the resistance unit and second recall the resistance unit.
In one embodiment of the invention, described substrate layer is Si or Si/SiO
2Layer, described separator is the Si of 100nm
3N
4Layer, described mobile ion barrier layer is the TaN layer of 20nm, and the Ag layer that described plane electrode layer is 20nm, described dielectric substrate are the GeTe layer, and described top electrode is the Pd electrode.
The preparation method of the memristor spare that the present invention proposes on the other hand comprises step S1-S12:
S1: at first prepare substrate layer;
S2: at substrate layer preparation the first separator;
S3: the lower floor mobile ion barrier layer of recalling the resistance unit in the first separator preparation first;
S4: the plane electrode layer of recalling the resistance unit in first lower floor's mobile ion barrier layer preparation first of recalling the resistance unit;
S5: the mobile ion barrier layer, upper strata of recalling the resistance unit in the first plane electrode layer preparation first of recalling the resistance unit;
S6: prepare the second separator on the first mobile ion barrier layer, upper strata of recalling the resistance unit;
S7: one or many repeating step S3-S6, prepare other one or more layers recall the resistance unit and on separator;
S8: utilize photoetching and etching technics, be etched to undermost separator from the separator of the superiors, form the top electrode etching groove;
S9: at the top electrode etching groove that forms and the surface coverage dielectric substrate of the superiors' separator;
S10: preparation vertical electrode layer in the top electrode etching groove;
S11: utilize CMP technique to remove vertical electrode layer material on the superiors' separator, form the top electrode with vertical stratification, namely perpendicular to the top electrode of substrate layer and plane electrode layer;
S12: one or many utilizes photoetching and etching technics, and the dielectric substrate that covers from the superiors' insulation surface respectively is etched to the plane electrode layer of respectively recalling the resistance unit, forms one or more hearth electrodes.
Described step S2, S6, S7 can utilize the standby separator of plasma reinforced chemical vapour deposition PECVD legal system; Described step S3, S5, S7 can utilize reactive sputtering to prepare the mobile ion barrier layer; Described step S4, S7 can utilize evaporation to prepare the plane electrode layer; Described step S10 can utilize sputtering method to prepare the vertical electrode layer.
In one embodiment of the invention, described step S1 selects Si/SiO
2The preparation substrate layer; Described step S2, S6, S7 utilize Si
3N
4The preparation separator; Described step S3, S5, S7 utilize TaN to prepare the mobile ion barrier layer; Described step S4, S7 utilize Ag to prepare the plane electrode layer; Described step S9 utilizes GeTe to prepare dielectric substrate; Described step S10 utilizes Pd to prepare the vertical electrode layer.
Gather in one embodiment of the present of invention, the separation layer thickness of described step S2, S6, S7 preparation is 100nm, and the mobile ion barrier layer thickness of described step S3, S5, S7 preparation is 20nm, and the plane electrode layer thickness of described step S4, S7 preparation is 20nm.
In one embodiment of the invention, described step S7 repeats a step S3-S6, obtains second and recalls resistance unit and the 3rd separator.
The concrete structure of the memristor spare of one embodiment of the present of invention as shown in Figure 1, described memristor spare comprises substrate layer 1, the multi-layer isolation layer on the substrate layer, i.e. the first separator 2, the second separators 6 and the 3rd separator 10.Comprise between described every two-layer separator that one deck recalls the resistance unit, namely first recalls resistance unit 15 and second and recalls resistance unit 16.Described first recalls resistance unit 15 comprises lower floor mobile ion barrier layer 3, plane electrode layer 4 and mobile ion barrier layer, upper strata 5.Described second recalls resistance unit 16 comprises lower floor mobile ion barrier layer 7, plane electrode layer 8 and mobile ion barrier layer, upper strata 9.Described memristor spare also comprises the top electrode etching groove that is etched to the first separator 2 from the 3rd separator 10, and the surface coverage of described top electrode etching groove and the 3rd separator 10 has dielectric substrate 11.Be provided with top electrode 12 in the described top electrode etching groove.Described memristor spare comprises that also being etched to first from the dielectric substrate 11 of the 3rd separator 10 surface coverage recalls the plane electrode layer 4 of resistance unit 15 and the first hearth electrode 14 of forming and be etched to second and recall the plane electrode layer 8 of resistance unit 16 and the second hearth electrode 13 of forming.
The preparation flow technique of this memristor spare specifically comprises the steps: as shown in Figure 2
S1: select Si or Si/SiO
21(is not shown for the preparation substrate layer);
S2: utilize standby the first separator 2 of plasma reinforced chemical vapour deposition PECVD legal system at substrate layer 1, described the first separator 2 is the Si of 100nm for thickness
3N
4
S3: utilize reactive sputtering to prepare first at the first separator 2 and recall the lower floor mobile ion barrier layer 3 that hinders unit 15, described lower floor mobile ion barrier layer 3 is the TaN of 20nm for thickness;
S4: utilize evaporation to prepare first on lower floor mobile ion barrier layer 3 and recall the plane electrode layer 4 that hinders unit 15, described plane electrode layer 4 is the Ag of 20nm for thickness;
S5: utilize reactive sputtering to prepare first at plane electrode layer 4 and recall the mobile ion barrier layer, upper strata 5 that hinders unit 15, mobile ion barrier layer 5, described upper strata is the TaN of 20nm for thickness;
S6: utilize standby the second separator 6 of plasma reinforced chemical vapour deposition PECVD legal system on mobile ion barrier layer, upper strata 5, described the second separator 6 is the Si of 100nm for thickness
3N
4
S7: repeating step S3-S6, prepare respectively second and recall lower floor mobile ion barrier layer 7, plane electrode layer 8 and the mobile ion barrier layer, upper strata 9 that hinders unit 16, and the 3rd separator 10;
S8: utilize photoetching and etching technics, be etched to the upper surface of the first separator 2 from the 3rd separator 10, forming width is the top electrode etching groove of 20 μ m;
S9: utilize ald (ALD) method at the dielectric substrate 11 of the surface coverage 10nm of the top electrode etching groove that forms and the 3rd separator 10;
S10: preparation vertical electrode layer Pd in the top electrode etching groove;
S11: utilize the vertical electrode layer material on the CMP technique removal the superiors separator, form the top electrode 12 with vertical stratification, i.e. top electrode Pd;
S12: utilize photoetching and etching technics twice, the dielectric substrate 11 that covers from the 3rd insulation surface respectively is etched to plane electrode layer 4 to form width is the first hearth electrode 14 of 20 μ m and is etched to plane electrode layer 8 to form width be the second hearth electrode 13 of 20 μ m.
Above execution mode only is used for explanation the present invention; and be not limitation of the present invention; the those of ordinary skill in relevant technologies field; in the situation that do not break away from the spirit and scope of the present invention; can also make a variety of changes and modification; therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (9)
1. a memristor spare is characterized in that, comprises substrate layer, on the described substrate layer multi-layer isolation layer is arranged, and comprises between described every two-layer separator that one deck recalls the resistance unit, describedly recalls the resistance unit and comprises two-layer mobile ion barrier layer and middle plane electrode layer; Described memristor spare also comprises the top electrode etching groove that is etched to the orlop separator from the separator of the superiors; The surface coverage of described top electrode etching groove and the superiors' separator has dielectric substrate; Be provided with top electrode in the described top electrode etching groove; Described memristor spare comprises that also the dielectric substrate that covers from the superiors' insulation surface respectively is etched to the plane electrode layer of respectively recalling the resistance unit and a plurality of hearth electrodes that form.
2. memristor spare as claimed in claim 1 is characterized in that, the number of plies of described separator is three layers, i.e. the first separator, and the second separator and the 3rd separator, the described number of plies of recalling the resistance unit is two-layer, namely first recalls resistance unit and second and recalls the resistance unit.
3. memristor spare as claimed in claim 1 is characterized in that, described substrate layer is Si or Si/SiO
2Layer, described separator is Si
3N
4Layer, described mobile ion barrier layer is TaN layer or TiN layer, and described plane electrode layer is Ag layer or Cu layer, and described dielectric substrate is GeTe layer or GeSe layer, and described top electrode is Pd electrode or Pt electrode.
4. memristor spare as claimed in claim 1 is characterized in that, described separator is 100nm, and described mobile ion barrier layer is 20nm, and described plane electrode layer is 20nm.
5. the preparation method of a memristor spare is characterized in that, may further comprise the steps:
S1: at first prepare substrate layer;
S2: at substrate layer preparation the first separator;
S3: the lower floor mobile ion barrier layer of recalling the resistance unit in the first separator preparation first;
S4: the plane electrode layer of recalling the resistance unit in first lower floor's mobile ion barrier layer preparation first of recalling the resistance unit;
S5: the mobile ion barrier layer, upper strata of recalling the resistance unit in the first plane electrode layer preparation first of recalling the resistance unit;
S6: prepare the second separator on the first mobile ion barrier layer, upper strata of recalling the resistance unit;
S7: one or many repeating step S3-S6, prepare other one or more layers recall the resistance unit and on separator;
S8: utilize photoetching and etching technics, be etched to undermost separator from the separator of the superiors, form the top electrode etching groove;
S9: cover dielectric substrate at the top electrode etching groove that forms and the superiors' insulation surface;
S10: preparation vertical electrode layer in the top electrode etching groove;
S11: utilize CMP technique to form top electrode;
S12: one or many utilizes photoetching and etching technics, and the dielectric substrate that covers from the superiors' insulation surface respectively is etched to the plane electrode layer of respectively recalling the resistance unit, forms one or more hearth electrodes.
6. the preparation method of memristor spare as claimed in claim 5 is characterized in that, described step S2, S6, S7 utilize the standby separator of plasma reinforced chemical vapour deposition PECVD legal system; Described step S3, S5, S7 utilize reactive sputtering to prepare the mobile ion barrier layer; Described step S4, S7 utilize evaporation to prepare the plane electrode layer; Described step S10 utilizes sputtering method to prepare the vertical electrode layer.
7. the preparation method of memristor spare as claimed in claim 5 is characterized in that, described step S1 selects Si/SiO
2The preparation substrate layer; Described step S2, S6, S7 utilize Si
3N
4The preparation separator; Described step S3, S5, S7 utilize TaN or TiN to prepare the mobile ion barrier layer; Described step S4, S7 utilize Ag or Cu to prepare the plane electrode layer; Described step S9 utilizes GeTe or GeSe to prepare dielectric substrate; Described step S10 utilizes Pd or Pt to prepare the vertical electrode layer.
8. the preparation method of memristor spare as claimed in claim 5, it is characterized in that, the separation layer thickness of described step S2, S6, S7 preparation is 100nm, the mobile ion barrier layer thickness of described step S3, S5, S7 preparation is 20nm, and the plane electrode layer thickness of described step S4, S7 preparation is 20nm.
9. such as the preparation method of the arbitrary described memristor spare of claim 5-8, it is characterized in that, described step S7 repeats a step S3-S6, obtains second and recalls resistance unit and the 3rd separator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210587167.3A CN103022350B (en) | 2012-12-28 | 2012-12-28 | Memory resistor and production method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210587167.3A CN103022350B (en) | 2012-12-28 | 2012-12-28 | Memory resistor and production method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103022350A true CN103022350A (en) | 2013-04-03 |
| CN103022350B CN103022350B (en) | 2015-01-07 |
Family
ID=47970694
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210587167.3A Active CN103022350B (en) | 2012-12-28 | 2012-12-28 | Memory resistor and production method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103022350B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104659208A (en) * | 2015-02-05 | 2015-05-27 | 中国科学院微电子研究所 | Non-volatile resistance random access memory and preparation method thereof |
| CN104979472A (en) * | 2014-04-11 | 2015-10-14 | 中国科学院宁波材料技术与工程研究所 | Organic polymer memristor structure unit |
| CN108063185A (en) * | 2017-12-28 | 2018-05-22 | 电子科技大学 | A kind of monocrystal thin films memristor crossed array preparation method of three-dimensional stacking structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101847647A (en) * | 2009-02-27 | 2010-09-29 | 夏普株式会社 | Nonvolatile semiconductor memory device and manufacturing method for same |
| CN101976676A (en) * | 2010-09-13 | 2011-02-16 | 北京大学 | Three-dimensional nonvolatile memory array and preparation method thereof |
| US20120313066A1 (en) * | 2011-06-07 | 2012-12-13 | Park Chan-Jin | Nonvolatile memory devices, nonvolatile memory cells and methods of manufacturing nonvolatile memory devices |
-
2012
- 2012-12-28 CN CN201210587167.3A patent/CN103022350B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101847647A (en) * | 2009-02-27 | 2010-09-29 | 夏普株式会社 | Nonvolatile semiconductor memory device and manufacturing method for same |
| CN101976676A (en) * | 2010-09-13 | 2011-02-16 | 北京大学 | Three-dimensional nonvolatile memory array and preparation method thereof |
| US20120313066A1 (en) * | 2011-06-07 | 2012-12-13 | Park Chan-Jin | Nonvolatile memory devices, nonvolatile memory cells and methods of manufacturing nonvolatile memory devices |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104979472A (en) * | 2014-04-11 | 2015-10-14 | 中国科学院宁波材料技术与工程研究所 | Organic polymer memristor structure unit |
| WO2015154695A1 (en) * | 2014-04-11 | 2015-10-15 | 中国科学院宁波材料技术与工程研究所 | Organic macromolecule resistance memory structure unit |
| CN104979472B (en) * | 2014-04-11 | 2017-07-28 | 中国科学院宁波材料技术与工程研究所 | A kind of organic polymer memristor construction unit |
| CN104659208A (en) * | 2015-02-05 | 2015-05-27 | 中国科学院微电子研究所 | Non-volatile resistance random access memory and preparation method thereof |
| CN108063185A (en) * | 2017-12-28 | 2018-05-22 | 电子科技大学 | A kind of monocrystal thin films memristor crossed array preparation method of three-dimensional stacking structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103022350B (en) | 2015-01-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10069067B2 (en) | Memory arrays and methods of forming memory cells | |
| JP5559549B2 (en) | Resistive memory device and manufacturing method thereof | |
| US9159768B2 (en) | Semiconductor device and electronic device including the same | |
| CN101976676A (en) | Three-dimensional nonvolatile memory array and preparation method thereof | |
| US9178143B2 (en) | Resistive memory structure | |
| CN102473707A (en) | Nonvolatile memory cell, nonvolatile memory cell array, and method for manufacturing the nonvolatile memory cell array | |
| WO2008062688A1 (en) | Nonvolatile semiconductor storage device and method for manufacturing the same | |
| KR20120021539A (en) | Nonvolatile memory element and memory device including the same | |
| WO2008047711A1 (en) | Non-volatile storage element array, and its manufacturing method | |
| KR20130120696A (en) | Resistance variable memory device and method for fabricating the same | |
| CN103117359A (en) | High-reliability nonvolatile memory and preparation method thereof | |
| CN102683584A (en) | Metal oxide resistance memory integrating a standard complementary metal oxide semiconductor (CMOS) process and preparation method thereof | |
| US20140077149A1 (en) | Resistance memory cell, resistance memory array and method of forming the same | |
| US10497750B2 (en) | Electronic memory using memristors and crossbars activating a plurality of memristors in series | |
| CN103022350B (en) | Memory resistor and production method thereof | |
| KR20120007618A (en) | Semiconductor device and method for fabrication the same | |
| KR20130076449A (en) | Method for fabricating resistance variable memory device | |
| CN102969328B (en) | Resistance variant memory crossover array structure and preparation method thereof | |
| US9035275B2 (en) | Three dimensional memory array adjacent to trench sidewalls | |
| CN112701222B (en) | Resistive random access memory and preparation method thereof | |
| US20210202580A1 (en) | Nonvolatile semiconductor memory device and fabrication method of the nonvolatile semiconductor memory device | |
| TWI463641B (en) | Ultra-high density resistive memory structure and its manufacturing method | |
| US20210020696A1 (en) | Structure of memory device and method for fabricating memory device | |
| CN103137625A (en) | Three-dimensional laminated memorizer and manufacturing method thereof | |
| KR20140065942A (en) | Resistance variable memory device and method for fabricating the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |