CN103021939A - Array substrate, manufacture method of array substrate and display device - Google Patents
Array substrate, manufacture method of array substrate and display device Download PDFInfo
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- CN103021939A CN103021939A CN2012105077424A CN201210507742A CN103021939A CN 103021939 A CN103021939 A CN 103021939A CN 2012105077424 A CN2012105077424 A CN 2012105077424A CN 201210507742 A CN201210507742 A CN 201210507742A CN 103021939 A CN103021939 A CN 103021939A
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Abstract
An embodiment of the invention provides an array substrate, a manufacture method of the array substrate and a display device and relates to the technical field of displaying. Times of figure composition technologies can be decreased in the array substrate manufacture process, and production cost of products can be effectively reduced. The manufacture method comprises the steps of forming a thin film transistor (TFT) and forming a first transparent electrode. The step of forming the first transparent electrode includes the steps of forming a metal oxide film, forming a barrier layer film and forming an etching barrier layer film. A figure of the metal oxide film and a figure of the etching barrier layer film are formed through one-time figure composition technologies. Metallization processing is performed in a figure region of a metal oxide film to form the first transparent electrode. The manufacture method is used for manufacture of the display device.
Description
Technical field
The present invention relates to the Display Technique field, relate in particular to a kind of array base palte and manufacture method thereof, display unit.
Background technology
Along with the development of TFT-LCD (Thin Film Transistor Liquid Crystal Display, Thin Film Transistor-LCD) Display Technique, increasing new technology constantly is suggested and uses.TFT-LCD based on ADS (ADvanced Super Dimension Switch, AD-SDS are called for short ADS, a senior super dimension switch technology) pattern relies on the characteristics such as its low-power consumption, wide visual angle, has obtained more and more people's concern.
The ADS technology mainly is that the electric field that the electric field that produces by gap electrode edge in the same plane and gap electrode layer and plate electrode interlayer produce forms multi-dimensional electric field, make in the liquid crystal cell between gap electrode, all aligned liquid-crystal molecules can both produce rotation directly over the electrode, thereby improved the liquid crystal operating efficiency and increased light transmission efficiency.Adopt the TFT-LCD product of ADS technology not only to increase at picture quality, and have high-resolution, high permeability, wide visual angle, high aperture, low aberration, without advantages such as water of compaction ripples.
For ADS type TFT-LCD, public electrode need to be produced on the array base palte, and this just needs extra increase once to form the composition technique of public electrode in the array base palte manufacturing process of ADS type TFT-LCD.Therefore usually need in the prior art to make ADS type TFT-LCD array base paltes by 7 composition techniques, and comprise respectively film forming, exposure, development, etching in the composition technique each time and the technique such as peel off.The number of times of composition technique too much will directly cause the cost of display unit product to rise, and the number of times that therefore how can further reduce composition technique also just becomes the problem of people's growing interest.
Summary of the invention
Embodiments of the invention provide a kind of array base palte and manufacture method thereof, display unit, can reduce the number of times of composition technique in the manufacture process of array base palte, effectively reduce the production cost of product.
For achieving the above object, embodiments of the invention adopt following technical scheme:
The one side of the embodiment of the invention provides a kind of manufacturing method of array base plate, is included in the step that forms thin-film transistor TFT and the first transparency electrode on the transparency carrier, and the step that forms described the first transparency electrode comprises:
Form metal-oxide film and etching barrier layer film;
Form the figure of described metal-oxide film and described etching barrier layer by composition technique;
Carry out metalized to form the first transparency electrode in the graphics field of described metal-oxide film.
The embodiment of the invention provides a kind of array base palte on the other hand, comprises thin-film transistor TFT and the first transparency electrode, also comprises:
Be formed at successively metal-oxide film and the etching barrier layer film on array base palte surface;
The figure of described metal-oxide film and the figure of described etching barrier layer form by a composition technique;
The graphics field of the described metal-oxide film by metalized comprises described the first transparency electrode.
The another aspect of the embodiment of the invention provides a kind of display unit, and described display unit comprises aforesaid array base palte.
The array base palte that the embodiment of the invention provides and manufacture method, display unit, adopt a composition technique to form the figure of metal-oxide film and the figure of etching barrier layer, and carry out metalized to form the first transparency electrode in the graphics field of metal-oxide film.So, can in a composition technique, form respectively the figure of metal-oxide film, figure and first transparency electrode of etching barrier layer, compared with prior art, composition technique access times in the array base palte manufacturing process can be reduced to 5 times, thereby simplified the production stage of product, significantly reduced the production cost of product.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The schematic flow sheet of a kind of manufacturing method of array base plate that Fig. 1 provides for the embodiment of the invention;
The schematic flow sheet of another manufacturing method of array base plate that Fig. 2 provides for the embodiment of the invention;
Fig. 3 is the structural representation that forms the grid metal level on the transparency carrier;
Fig. 4 is the structural representation that forms metal-oxide film and etching barrier layer film on the array base palte shown in Figure 3;
Fig. 5 is the schematic diagram that array base palte shown in Figure 4 is formed with photoresist;
Fig. 6 is the structural representation after array base palte shown in Figure 5 carries out etching;
Fig. 7 is the structural representation after array base palte shown in Figure 6 carries out ashing;
Fig. 8 is the structural representation after array base palte shown in Figure 7 carries out metalized;
Fig. 9 is the structural representation that metal level is leaked in the formation source on the array base palte shown in Figure 8;
The structural representation of a kind of array base palte that Figure 10 provides for the embodiment of the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
The manufacturing method of array base plate that the embodiment of the invention provides is included in the step that forms thin-film transistor TFT and the first transparency electrode on the transparency carrier, and as shown in Figure 1, the step that forms the first transparency electrode comprises:
S101, formation metal-oxide film and etching barrier layer film.
Wherein, metal-oxide film can adopt the transparent metal oxide material that is characteristic of semiconductor to be made, and for example, metal-oxide film can comprise: at least a among InGaZnO, InGaO, ITZO, the AlZnO.
S102, the figure that passes through a composition technique formation metal-oxide film and the figure of etching barrier layer.
Concrete, on the substrate that is formed with successively metal-oxide film and etching barrier layer film, can form by a composition technique figure of this metal-oxide film and etching barrier layer, the figure of this etching barrier layer is positioned at the metal-oxide film patterned surface, and covers the channel region of TFT.
S103, carry out metalized to form the first transparency electrode in the graphics field of this metal-oxide film.
Concrete, can carry out metalized to the metal-oxide film that exposes, form the metal-oxide film with conductor characteristics, the part metals sull that does not carry out metalized under the etching barrier layer forms semiconductor active layer.
Wherein, metal-oxide film through metalized comprises that this leakage connecting electrode and the first transparency electrode are structure as a whole for the source connecting electrode that is electrically connected with the source electrode of TFT, for the leakage connecting electrode and the first transparency electrode that are electrically connected with the drain electrode of TFT.
The manufacturing method of array base plate that the embodiment of the invention provides adopts a composition technique to form the figure of metal-oxide film and the figure of etching barrier layer, and carries out metalized to form the first transparency electrode in the graphics field of metal-oxide film.So, can in a composition technique, form respectively the figure of metal-oxide film, figure and first transparency electrode of etching barrier layer, compared with prior art, composition technique access times in the array base palte manufacturing process can be reduced to 5 times, thereby simplified the production stage of product, significantly reduced the production cost of product.
Further, the manufacturing method of array base plate that the embodiment of the invention provides as shown in Figure 2, specifically comprises:
S201, form grid line, gate electrode and public electrode wire at transparency carrier.
In the middle of the actual production process of array base palte, transparency carrier specifically can be that the transparent material that adopts glass or transparent resin etc. to have certain robustness is made.Need to adopt a composition technique to form grid line, gate electrode and the isostructural figure of public electrode wire at transparency carrier.
For example, can adopt plasma reinforced chemical vapour deposition (PECVD), magnetron sputtering, thermal evaporation or other film build method, form metal level at transparency carrier.Wherein, this metal level can be the single thin film that the metals such as molybdenum, aluminium, aluminium rubidium alloy, tungsten, chromium, copper form, and also can be the plural layers that above metallic multilayer forms.Surface at this metal level is formed with photoresist, carry out exposure imaging so that photoresist produces pattern by the mask plate with specific pattern, peel off the metal level that does not cover the photoresist place, as shown in Figure 3, finally form the pattern of grid line (not shown among Fig. 3), gate electrode 111 and public electrode wire 112 on the surface of transparency carrier 10.
S202, form gate insulation layer at transparency carrier, grid line, gate electrode and public electrode wire.
As shown in Figure 4, Fig. 4 is the hierarchical structure schematic diagram in TFT zone, as seen, in this zone, is formed with the gate insulation layer 12 of thickness homogeneous at the transparency carrier 10 that is formed with gate electrode 111.
S203, on the substrate that is formed with successively metal-oxide film and etching barrier layer film, form the figure of this metal-oxide film and this etching barrier layer by composition technique, the figure of this etching barrier layer is positioned at the metal-oxide film patterned surface, and covers the channel region of TFT.
Concrete, equally as shown in Figure 4, on the substrate that is formed with gate insulation layer 12, also be formed with successively metal-oxide film 13 and etching barrier layer film 14.Wherein, metal-oxide film can adopt the transparent metal oxide material that is characteristic of semiconductor to be made, and for example, metal-oxide film can comprise: at least a among InGaZnO, InGaO, ITZO, the AlZnO.Etching barrier layer film 14 can be the materials such as fine and close silicon nitride, silica, silicon oxynitride.
Adopt composition technique to process to a kind of like this substrate of structure, at first, as shown in Figure 5, be formed with photoresist 50 on the surface of etching barrier layer film 14, obtain as shown in Figure 5 photoresist shape by exposure imaging.Wherein, the thickness that this photoresist 50 is located in TFT raceway groove corresponding region can guarantee so that greater than all the other zones the TFT channel region has still etching barrier layer after a composition, prevents from producing between the electrode short circuit.In addition, photoresist 50 covers the subregion of etching barrier layer film 14, and this zone is source-drain electrode and the first transparency electrode region of TFT.
The substrate that is formed with photoresist 50 is carried out etching, as shown in Figure 6, can etch away metal-oxide film 13 and etching barrier layer film 14 by etching technics, until expose gate insulation layer 12, only keep part metals sull 13 and the etching barrier layer film 14 of photoresist 50 overlay areas.
Further, adopt cineration technics to process aforesaid substrate.Processing by cineration technics, the thickness of photoresist 50 reduces integral body, the etching barrier layer film 14 that will expose etches away, the final substrate that forms as shown in Figure 7, expose outside metal-oxide film 13, as seen, disposed most of photoresist by ashing, the photoresist that has only kept original thickness major part namely covers the photoresist of TFT channel region.
S204, the metal-oxide film that exposes is carried out metalized, form the metal-oxide film with conductor characteristics, the part metals sull that does not carry out metalized under the etching barrier layer forms semiconductor active layer.
Concrete, as shown in Figure 8, can carry out metalized to the metal-oxide film 13 that exposes by plasma process or annealing process etc.This step can realize by following three kinds of modes.
Mode one: the substrate that will have structure shown in Figure 7 places vacuum chamber to be heated to uniform temperature, and keeps cooling off in air behind the certain hour.Preferably, this uniform temperature value can be 200～300 ℃, and the certain hour of maintenance can be 20～40 minutes.
Mode two: the substrate that will have structure shown in Figure 7 places reducing atmosphere to heat-treat at 200～400 ℃.
Mode three: the substrate that will have structure shown in Figure 7 places vacuum chamber, the method that using plasma is processed, and general power is 1500～2500W, pressure is 1000～2000mtorr, and hydrogen (H is arranged
2) plasma and oxygen (O
2) two kinds of methods of plasma treatment, when using hydrogen gas plasma or oxygen gas plasma to process, the gas flow of hydrogen or oxygen is generally 5000～15000sccm.
By above-mentioned three kinds of modes, the carrier concentration of the metal-oxide film 13 that is metallized processing is improved, present conductor characteristics, thereby can replace existing pixel electrode material.And that etching barrier layer does not carry out the carrier concentration of metal-oxide film of metalized for 14 times is lower, presents characteristic of semiconductor, is semiconductor active layer 134.
Wherein, metal-oxide film 13 through metalized specifically can comprise for the source connecting electrode 131 that is electrically connected with the source electrode of TFT, for the leakage connecting electrode 132 and the first transparency electrode 133 that are electrically connected with the drain electrode of TFT, leaks connecting electrode 132 and the first transparency electrode 133 and is structure as a whole.
S205, form the drain electrode of source electrode and the TFT of data wire, TFT at the substrate that is formed with etching barrier layer and the first transparency electrode.
Concrete, as shown in Figure 9, be formed with the source electrode 151 that is arranged in the TFT on the source connecting electrode 131, the drain electrode 152 that is positioned at the TFT on the leakage connecting electrode 132 and the data wire (Fig. 9 is not shown) that is electrically connected with the source electrode 151 of TFT on the substrate.
Further, the array base palte of structure is further processed to being formed with as shown in Figure 9 can to adopt composition technique.For example, cineration technics can be passed through so that the source electrode 151 of TFT reduces with the thickness of the drain electrode 152 of TFT is whole, until the source electrode 151 of TFT is identical with the thickness that loses barrier layer 14 with the thickness of the drain electrode 152 of TFT.So, the drain electrode 152 of having eliminated the source electrode 151 of TFT, TFT on the array base palte is poor with the section on erosion barrier layer 14, has increased the planarization of rete, has further improved the quality of display unit product.
S206, form the passivation layer that contains via hole at the substrate of the drain electrode of the source electrode that is formed with data wire, TFT and TFT, this via hole runs through passivation layer and gate insulation layer, exposes public electrode wire.
S207, form the second transparency electrode at passivation layer, this second transparency electrode is electrically connected with public electrode wire by via hole.
Need to prove, in embodiments of the present invention, the first transparency electrode can be pixel electrode, and the second transparency electrode can be public electrode.
Concrete, the source of TFT, drain electrode, data wire, passivation layer and the second transparency electrode can form by three composition techniques respectively.
Adopt existing film build method such as the methods such as magnetron sputtering or thermal evaporation to form metallic film at substrate, and form the source electrode 151 of the TFT be electrically connected with source connecting electrode 131 and the drain electrode 152 of the TFT that is electrically connected with leakage connecting electrode 132 and the pattern of data wire by composition technique.Wherein, the metallic film of formation source, drain electrode and data wire can be the single thin film that the metals such as molybdenum, aluminium, aluminium rubidium alloy, tungsten, chromium, copper form, and also can be the plural layers that above metallic multilayer forms.
Then, prepare insulation film by methods such as chemical vapour deposition (CVD) or thermal evaporations again on substrate and form passivation layer 16, be formed with via hole A by composition technique on this passivation layer, the second transparency electrode 17 can be electrically connected with public electrode wire 112 by via hole A.Wherein, this insulation film can adopt the single thin film of silicon nitride, silica or silicon oxynitride, also can adopt the plural layers of the multilayer formation of above-mentioned material.
At last, form transparent conductive film by methods such as magnetron sputtering or thermal evaporations, and form the second transparency electrode 17 of strip by composition technique, the final array base palte that forms as shown in figure 10.Wherein, can form multi-dimensional electric field between the first transparency electrode 133 and the second transparency electrode 17.The material of the second transparency electrode 17 can be the transparent conductive materials such as ITO, ZnO, InGaZnO, InZnO, InGaO.
The manufacturing method of array base plate that the embodiment of the invention provides adopts a composition technique to form the figure of metal-oxide film and the figure of etching barrier layer, and carries out metalized to form the first transparency electrode in the graphics field of metal-oxide film.So, can in a composition technique, form respectively the figure of metal-oxide film, figure and first transparency electrode of etching barrier layer, compared with prior art, composition technique access times in the array base palte manufacturing process can be reduced to 5 times, thereby simplified the production stage of product, significantly reduced the production cost of product.
The array base palte that the embodiment of the invention provides as shown in figure 10, comprises thin-film transistor TFT and the first transparency electrode 133, also comprises:
Be formed at successively metal-oxide film 13 and the etching barrier layer film 14 on array base palte surface.
Wherein, the figure of the figure of metal-oxide film 13 and etching barrier layer 14 forms by a composition technique.
The graphics field of the metal-oxide film 13 by metalized comprises the first transparency electrode 133.
The array base palte that this array base palte can make for the manufacture method of the array base palte that adopts above-mentioned each embodiment explanation.
This array base palte specifically comprises TFT, the first transparency electrode 133 and the second transparency electrode 17.Wherein, source connecting electrode 131, leakage connecting electrode 132, the first transparency electrode 133 and semiconductor active layer 134 are all formed by a composition technique by same burning film, wherein, the first transparency electrode 133 is obtained by metalized by metal-oxide film, and semiconductor active layer 134 is formed by the metal-oxide film that is not metallized processing.
Need to prove, be the explanation of carrying out as example take the array base palte that the different layer of pixel electrode and public electrode arranges among above-mentioned each embodiment.Be understandable that, when pixel electrode and public electrode are arranged on the array base palte with layer among the above embodiment, also can form by composition technique, metalized etc. the pattern of active layer, pixel electrode and public electrode at the layer of metal sull.Therefore, the array base palte that the embodiment of the invention provides also goes for the tft array substrate of IPS (In-Plane Switching, plane internal switch) type and AD-SDS type by suitable distortion.
The array base palte that the embodiment of the invention provides adopts a composition technique to form the figure of metal-oxide film and the figure of etching barrier layer, and carries out metalized to form the first transparency electrode in the graphics field of metal-oxide film.So, can in a composition technique, form respectively the figure of metal-oxide film, figure and first transparency electrode of etching barrier layer, compared with prior art, composition technique access times in the array base palte manufacturing process can be reduced to 5 times, thereby simplified the production stage of product, significantly reduced the production cost of product.
Further, as shown in figure 10, the figure of etching barrier layer 14 can be positioned at metal-oxide film 13 patterned surfaces, and covers the channel region of TFT.
The graphics field of the metal-oxide film 13 by metalized can also comprise:
Semiconductor active layer 134, this semiconductor active layer 134 can be positioned at etching barrier layer 14 times.
And for the source connecting electrode 131 that is electrically connected with the source electrode 151 of TFT, for the leakage connecting electrode 132 and the first transparency electrode 133 that are electrically connected with the drain electrode 152 of TFT, this leakage connecting electrode 132 and the first transparency electrode 133 can be structure as a whole.
Further, array base palte can also comprise:
Grid line between transparency carrier 10 and metal-oxide film 13 (not shown among Figure 10), gate electrode 111 and public electrode wire 112.
Array base palte can also comprise:
Be arranged in the data wire (Figure 10 is not shown) on the surface of etching barrier layer 14 and the first transparency electrode 133, the source electrode 151 of TFT and the drain electrode 152 of TFT.
Be positioned at the passivation layer that contains via hole A 16 on surface of the drain electrode 152 of the source electrode 151 of data wire, TFT and TFT, this via hole A runs through passivation layer 16 and gate insulation layer 12, exposes public electrode wire 112.
Be positioned at the second transparency electrode 17 of passivation layer surface 16, this second transparency electrode 17 is electrically connected with public electrode wire 112 by via hole A.
In embodiments of the present invention, the first transparency electrode 133 can be pixel electrode, and the second transparency electrode 17 can be public electrode.
Wherein, metal-oxide film 13 can adopt the transparent metal oxide material that is characteristic of semiconductor, for example, can comprise: at least a among InGaZnO, InGaO, ITZO, the AlZnO.
The display unit that the embodiment of the invention provides comprises aforesaid array base palte.
This array base palte specifically comprises TFT, the first transparency electrode and the second transparency electrode.Wherein, source connecting electrode, leakage connecting electrode, the first transparency electrode and semiconductor active layer are all formed by a composition technique by same burning film, wherein, the first transparency electrode is obtained by metalized by metal-oxide film, and semiconductor active layer is formed by the metal-oxide film that is not metallized processing.
Need to prove display unit provided by the present invention can for: liquid crystal panel, Electronic Paper, oled panel, LCD TV, liquid crystal display, DPF, mobile phone, panel computer etc. have product or the parts of any Presentation Function.
The display unit that the embodiment of the invention provides, comprise array base palte, this array base palte adopts a composition technique to form the figure of metal-oxide film and the figure of etching barrier layer, and carries out metalized to form the first transparency electrode in the graphics field of metal-oxide film.So, can in a composition technique, form respectively the figure of metal-oxide film, figure and first transparency electrode of etching barrier layer, compared with prior art, composition technique access times in the array base palte manufacturing process can be reduced to 5 times, thereby simplified the production stage of product, significantly reduced the production cost of product.
The above; be the specific embodiment of the present invention only, but protection scope of the present invention is not limited to this, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.
Claims (18)
1. a manufacturing method of array base plate is included in the step that forms thin-film transistor TFT and the first transparency electrode on the transparency carrier, it is characterized in that, the step that forms described the first transparency electrode comprises:
Form metal-oxide film and etching barrier layer film;
Form the figure of described metal-oxide film and the figure of described etching barrier layer by a composition technique;
Carry out metalized to form the first transparency electrode in the graphics field of described metal-oxide film.
2. method according to claim 1 is characterized in that, the described figure that forms described metal-oxide film and described etching barrier layer by composition technique comprises:
On the substrate that is formed with successively described metal-oxide film and described etching barrier layer film, form the figure of described metal-oxide film and described etching barrier layer by composition technique, the figure of described etching barrier layer is positioned at described metal-oxide film patterned surface, and covers the channel region of described TFT.
3. method according to claim 1 is characterized in that, described graphics field at described metal-oxide film is carried out metalized and comprised to form the first transparency electrode:
The metal-oxide film that exposes is carried out metalized, form the metal-oxide film with conductor characteristics, the described metal-oxide film of part that does not carry out described metalized under the described etching barrier layer forms semiconductor active layer;
Wherein, described metal-oxide film through described metalized comprises that described leakage connecting electrode and described the first transparency electrode are structure as a whole for the source connecting electrode that is electrically connected with the source electrode of described TFT, for the leakage connecting electrode and the first transparency electrode that are electrically connected with the drain electrode of described TFT.
4. method according to claim 3 is characterized in that, describedly the metal-oxide film that exposes is carried out metalized comprises:
The array base palte that will have the metal-oxide film that exposes places vacuum chamber to be heated to preset temperature, and keeps cooling off in air behind the Preset Time, and wherein, described preset temperature is 200～300 ℃, and described Preset Time is 20～40 minutes; Or,
The array base palte that will have the metal-oxide film that exposes places reducing atmosphere to heat-treat at 200～400 ℃; Or,
The array base palte that will have the metal-oxide film that exposes places vacuum chamber, adopts hydrogen gas plasma or oxygen gas plasma to process, and power is 1500～2500W, and pressure is 1000～2000mtorr, and gas flow is 5000～15000sccm.
5. method according to claim 1 is characterized in that, before the step that forms described the first transparency electrode, described method also comprises:
Form grid line, gate electrode and public electrode wire at described transparency carrier;
Form gate insulation layer at described transparency carrier, described grid line, described gate electrode and described public electrode wire.
6. method according to claim 5 is characterized in that, after the step that forms described the first transparency electrode, described method also comprises:
Form the drain electrode of source electrode and the described TFT of data wire, described TFT at the substrate that is formed with described etching barrier layer and described the first transparency electrode;
Substrate in the drain electrode of the source electrode that is formed with described data wire, described TFT and described TFT forms the passivation layer that contains via hole, and described via hole runs through described passivation layer and described gate insulation layer, exposes public electrode wire;
Form the second transparency electrode at described passivation layer, described the second transparency electrode is electrically connected with described public electrode wire by described via hole.
7. method according to claim 6 is characterized in that, after the substrate that is formed with described etching barrier layer and described the first transparency electrode formed the drain electrode of the source electrode of data wire, described TFT and described TFT, described method also comprised:
By the source electrode of the described TFT of composition PROCESS FOR TREATMENT and the drain electrode of described TFT, so that the drain electrode of the source electrode of described TFT and described TFT is identical with the thickness of described etching barrier layer.
8. according to claim 1 to 7 arbitrary described methods, it is characterized in that, described the first transparency electrode is pixel electrode, and described the second transparency electrode is public electrode.
9. according to claim 1 to 7 arbitrary described methods, it is characterized in that, described graphics field at described metal-oxide film is carried out metalized and is comprised to form the first transparency electrode:
The first transparency electrode is processed to form by plasma process or annealing process in graphics field at described metal-oxide film.
10. according to claim 1 to 7 arbitrary described methods, it is characterized in that, described metal-oxide film adopts the transparent metal oxide material that is characteristic of semiconductor, comprising: at least a among InGaZnO, InGaO, ITZO, the AlZnO.
11. an array base palte comprises thin-film transistor TFT and the first transparency electrode, it is characterized in that, also comprises:
Be formed at successively metal-oxide film and the etching barrier layer film on array base palte surface;
The figure of described metal-oxide film and the figure of described etching barrier layer form by a composition technique;
The graphics field of the described metal-oxide film by metalized comprises described the first transparency electrode.
12. array base palte according to claim 11 is characterized in that,
The figure of described etching barrier layer is positioned at described metal-oxide film patterned surface, and covers the channel region of TFT.
13. array base palte according to claim 11 is characterized in that, the graphics field of described described metal-oxide film by metalized also comprises:
Semiconductor active layer, described semiconductor active layer are positioned under the described etching barrier layer;
For the source connecting electrode that is electrically connected with the source electrode of described TFT, for the leakage connecting electrode and the first transparency electrode that are electrically connected with the drain electrode of described TFT, described leakage connecting electrode and described the first transparency electrode are structure as a whole.
14. array base palte according to claim 11 is characterized in that, described array base palte also comprises:
Grid line, gate electrode and public electrode wire between described transparency carrier and described metal-oxide film;
Gate insulation layer between described grid line, described gate electrode and described public electrode wire and described metal-oxide film.
15. array base palte according to claim 14 is characterized in that, described array base palte also comprises:
Be positioned at the source electrode of the data wire on the surface of described etching barrier layer and described the first transparency electrode, described TFT and the drain electrode of described TFT;
Be positioned at the passivation layer that contains via hole on surface of the drain electrode of the source electrode of described data wire, described TFT and described TFT, described via hole runs through described passivation layer and described gate insulation layer, exposes public electrode wire;
Be positioned at the second transparency electrode of described passivation layer surface, described the second transparency electrode is electrically connected with described public electrode wire by described via hole.
16. to 15 arbitrary described array base paltes, it is characterized in that according to claim 11, described the first transparency electrode is pixel electrode, described the second transparency electrode is public electrode.
17. to 15 arbitrary described array base paltes, it is characterized in that according to claim 11, described metal-oxide film adopts the transparent metal oxide material that is characteristic of semiconductor, comprising: at least a among InGaZnO, InGaO, ITZO, the AlZnO.
18. a display unit is characterized in that, described display unit comprises such as the arbitrary described array base palte of claim 11 to 17.
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