CN103019955B - The EMS memory management process of PCR-based AM main memory application - Google Patents
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Abstract
The present invention provides the EMS memory management process that a kind of PCR-based AM main memory is applied, it is applied in the system built by CPU, internal memory and external memory, this EMS memory management process is: using the DRAM cache buffer memory as PCRAM main memory, the idle page in DRAM cache is replaced PCRAM main memory in loop equilibrium mode by system; When CPU performs the operation writing data, CPU detects in DRAM cache whether there is the data page to write, exist and then write data into DRAM cache, the data page otherwise will write carries out write operation after being read into DRAM cache by PCRAM main memory again, it is achieved that demand to the required erasable number of times of PCRAM main memory and the performance such as writing rate, fatigue properties during CPU write operation; When CPU performs the operation reading data, first CPU accesses DRAM cache, and when not reading, in DRAM cache, the data page to access, CPU accesses PCRAM main memory and is read out, realize CPU and can directly read the data in DRAM cache and PCRAM main memory, be greatly saved workload during system read operation.
Description
Technical field
The present invention relates to a kind of memory management technology, particularly relate to the EMS memory management process of a kind of PCR-based AM main memory application.
Background technology
Internal memory (Memory) is one of parts important in computer, and it is to carry out, with CPU (central processing unit), the bridge linked up. In computer, the operation of all programs all carries out in internal memory, and therefore the performance of internal memory is very big on the impact of computer. Internal memory is also referred to as built-in storage, and its effect is operational data for temporarily depositing in CPU and the data with the external memory storage exchange such as hard disk. Thus, the important hardware device of computer products, its software system realizes various function and all be unable to do without internally to deposit and be written and read. The big management of internal memory is operated by system and realizes by current industry, and therefore software system uses and will depend on operating system during internal memory. The big management of internal memory can be divided into dynamically management and static management two kinds by operating system.
The storage device of computer system is divided into the data that built-in storage and external memory, program and program to access all to must be installed into internal memory could running. Main memory is the hardcore of computer system, is another critical function of operating system to the management of memorizer.
Program address of correspondence after compiling is virtual address (32 4G), and it is physical memory address that physical address (is probably 1G). Need to carry out the mapping of virtual address and physical address when program is loaded into internal memory from hard disk, because our physical address does not have 4G, many programs not having to run will be paged out, management between them is then managed by MMU (MemoryManagementUnit, i.e. memory management unit). Only small at our internal memory at first, the generally only capacity of several million, if ceaselessly exchanging between hard disk and internal memory and just consuming substantial amounts of resource, and the reading speed of hard disk is very slow, so just have devised Swap subregion (exchange area), although it divides out from hard disk, but its form is close with internal memory.So can be put in Swap subregion less than the program run in internal memory, the speed general's increase so changing to and swapping out.
Exchange partition is used when physical memory (RAM) is filled. If system needs more memory source, and physical memory fills with, and in internal memory, sluggish page will be moved to swapace. Offer help although swapace can be the machine with a small amount of internal memory, but this method should not be taken as being the replacement to internal memory. Swapace is positioned on hard disk drive, and it is slower than entering physical memory.
Exchange (Swapping) technology is when multiple programs concurrently perform, it is possible to temporary transient inexecutable program being delivered in external memory, loading new program thus obtaining free memory space, or reads in the program being saved in external memory to be in ready state. Cross-over unit is the address space of whole process. Switching technology is usually used in multiprogrammed system or small-sized time-sharing system, with partition type storage management with the use of also referred to as " exchange " or " roll into/roll out ". One of its advantage is to increase the program number concurrently run, and provides the user with suitable response time; Another significant advantage of switching technology is not affect program structure compared with soverlay technique. Switching technology itself there is also deficiency, for instance: the control changed to and swap out is increased processor expense; The whole address space of program is all exchanged, it does not have consider the statistical property that in execution process, address accesses.
In the environment that current mobile computing becomes increasingly popular, the memory technology in past has seemed unable to do what one wishes, is especially difficult to meet that electronic product is less to storage volume, the requirement of system power dissipation. Development along with quasiconductor and storage chip technology, novel non-volatile computer memory technology combine the good characteristic of the memorizer such as DRAM, SRAM and FLASH of main flow on current semiconductor memory market, but also there is micro superior performance, non-volatile, zero access, have extended cycle life, data stability is strong, the many advantages such as low in energy consumption, it is believed that be the best solution of non-volatile memory technology of future generation.
Refer to Fig. 1 a and Fig. 1 c, three kinds of hardware structure schematic diagrams of PCRAM main memory application in display prior art, including CPU11, high-speed cache (i.e. module CACHE in diagram) 12, internal memory 13, external memory (i.e. module SSD/HARDDISK in diagram) 14, the memory capacity of above-mentioned three kinds of hardware structures reduces successively, and every bit memory cost is incremented by successively, memorizer storage speed increases successively, memorizer storage time decreased. But in actual application, still suffer from problems with:
Hardware structure in PCRAM application as shown in Figure 1a, use PCRAM to substitute traditional DRAM and expand memory size PCRAM, but be currently based on the erasable number of times of PCRAM and write the limitation of the performance such as data speed, resisting fatigue and far do not reach CPU to the required speed of data access and number of times.
For another example the hardware structure of the PCRAM application shown in Fig. 1 b and Fig. 1 c, both is based on the buffer memory effect of DRAM and applies, not only namely storage system is made up of buffer memory and internal memory, has the high speed of DRAM but also has the mass-storage system of PCRAM. Wherein, access is left in DRAM than data more frequently by the hardware structure shown in Fig. 1 b, access data infrequently and leave PCRAM in; Using the DRAM L2 cache as PCRAM in hardware structure shown in Fig. 1 c, balance the demand between writing rate between PCRAM and CPU, erasable number of times and fatigue properties.But, above two scheme is disadvantageous in that, if CPU has only to the low volume data read in PCRAM buffer memory in some data page, and is still read in DRAM for CPU access, workload when now considerably increasing read operation and system power dissipation.
Thus, how the memory management technology that a kind of PCR-based AM main memory is applied is provided, to solve above-mentioned problems of the prior art and deficiency, has become as the problem that practitioner in the art competitively studies.
Summary of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide the EMS memory management process of a kind of PCR-based AM main memory application, improve the purpose to the required erasable number of times of PCRAM main memory and the performance such as writing rate and reduction fatigability when write operation in order to realize CPU.
Another object of the present invention is to the internal storage management system and the method that provide a kind of PCR-based AM main memory to apply, in order to when CPU read operation, the data in DRAM and PCRAM can be directly read based on the random characteristic CPU that reads, and then the purpose of workload when realizing being greatly saved system read operation.
For achieving the above object and other relevant purposes, the present invention provides the EMS memory management process that a kind of PCR-based AM main memory is applied, it is applied in by CPU, described internal memory is managed operation when described CPU performs read/write operation in the system that internal memory and external memory build, described internal memory includes DRAM cache and PCRAM main memory, it is characterized in that, described EMS memory management process includes: the step of data page displacement, system is using the described DRAM cache buffer memory as PCRAM main memory, when described DRAM cache insufficient space, idle data page in described DRAM cache is replaced to described PCRAM main memory by system in loop equilibrium mode, when the data page displaced reads in described DRAM main memory again, shared by this data page, the memory space of described PCRAM main memory is automatically releasable, write the step of data, when described CPU performs the operation writing data, described CPU detects in described DRAM cache whether there is the data page to write, if existing, then write data into described DRAM cache, if it is not, the data page then will write carries out write operation after being read into described DRAM cache by described PCRAM main memory again, reading the step of data, when described CPU performs the operation reading data, first described CPU accesses described DRAM cache, and when not reading the data page being intended to read in described DRAM cache, described CPU accesses described PCRAM main memory and is read out.
In the EMS memory management process of the present invention, when idle data page in described DRAM cache is replaced to described PCRAM main memory by system, the page displaced is deposited successively by described PCRAM core address order, described CPU once deposits before judging described PCRAM main memory whether the position of replaced idle data page has reached the maximum address of described PCRAM main memory, if it is not, be then judged to previous cycle, if, then judge that previous cycle terminates, and enters subsequent cycle.
Specifically, in described previous cycle, comprise the following steps: 1) described CPU idle block address region from the address growing direction described PCRAM main memory of scanning; 2) described idle data page is stored in the first free block address area scanned; 3) to data page one enumerator of distribution that should leave unused in described DRAM cache, and it is marked in the bit position of its bitmap, and this enumerator is initialized as 1; 4) enumerator of assignment all in the bitmap of described DRAM cache is added 1;5) page more than a preset value N in the enumerator of those assignment is searched; 6) by being mapped to previous cycle with the described idle data page exceeding the page setting value N corresponding, to be again read in described DRAM cache, and the counter O reset that the idle data page that this is again read in described DRAM cache is corresponding.
In described subsequent cycle, comprising the following steps: 1) described CPU starts to scan idle block address region from the lowest address of described PCRAM main memory; 2) described idle data page is stored in the first free block address area scanned; 3) to data page one enumerator of distribution that should leave unused in described DRAM cache, and it is marked in the bit position of its bitmap, and this enumerator is initialized as 1; 4) enumerator of assignment all in the bitmap of described DRAM cache is added 1; 5) page more than a preset value N in the enumerator of those assignment is searched; 6) by being mapped to previous cycle with the described idle data page exceeding the page setting value N corresponding, to be again read in described DRAM cache, and the counter O reset that the idle data page that this is again read in described DRAM cache is corresponding.
When described CPU performs the operation writing data, described CPU first determines whether whether there is the data page to write in described DRAM cache, if, then to write data in described DRAM cache, if not, then system is dished out page fault, and goes to described PCRAM main memory, is read in described DRAM cache by the described data page being intended to write so that write data by described PCRAM main memory.
In the EMS memory management process of the present invention, when described CPU performs the operation reading data, described CPU first determines whether whether there is the data page to read in described DRAM cache, if, then read from described DRAM cache, if it is not, then read from described PCRAM main memory.
In the EMS memory management process of the present invention, described system also includes the high-speed cache being connected between described CPU and internal memory.
As mentioned above, the EMS memory management process of the PCR-based AM main memory application of the present invention, using the DRAM buffer memory as PCRAM, during write operation, CPU calls the page data in DRAM, it is achieved that demand to the required erasable number of times of PCRAM and the performance such as writing rate, fatigability during CPU write operation; During read operation, based on reading characteristic at random, CPU can directly read the data in DRAM and PCRAM, is greatly saved workload during system read operation. And the main memory effect of PCR-based AM of the present invention not only can realize the fast write operation to internal storage data but also can realize the random reading of data in PCRAM main memory, being greatly saved the energy that read operation consumes, the database application based on mass data read operation is had more obvious advantage by the present invention especially.
Accompanying drawing explanation
Three kinds of hardware structure schematic diagrams of application that Fig. 1 a and Fig. 1 c is shown as in prior art PCRAM main memory.
Fig. 2 is shown as applying the system principle diagram of EMS memory management process of the present invention.
Fig. 3 is shown as in EMS memory management process of the present invention CPU and reads the flow chart of data.
Fig. 4 is shown as in EMS memory management process of the present invention the flow chart of CPU write data.
Fig. 5 is shown as the flow chart that in EMS memory management process of the present invention, loop equilibrium mode is replaced.
Detailed description of the invention
Below by way of specific instantiation, embodiments of the present invention being described, those skilled in the art can be understood other advantages and effect of the present invention easily by content disclosed in the present specification.The present invention can also be carried out by additionally different detailed description of the invention or apply, and the every details in this specification based on different viewpoints and application, can also carry out various modification or change under the spirit without departing substantially from the present invention.
Refer to Fig. 2 to Fig. 5, it should be noted that, the diagram provided in the present embodiment only illustrates the basic conception of the present invention in a schematic way, then assembly that in graphic, only display is relevant with the present invention but not component count when implementing according to reality, shape and size drafting, during its actual enforcement, the kenel of each assembly, quantity and ratio can be a kind of random change, and its assembly layout kenel is likely to increasingly complex.
As shown in the figure, the present invention provides the EMS memory management process that a kind of PCR-based AM main memory is applied, it is applied in the system built by CPU21, high-speed cache (CACHE) 22, internal memory 23 and external memory 24 (such as SSD or Harddisk), in order to described internal memory 23 is managed operation when described CPU21 performs read/write operation, described internal memory 23 includes DRAM cache 231 and PCRAM main memory 232.
When described CPU21 performs the operation reading data, first described CPU21 accesses described DRAM cache 231, and when not reading the data page being intended to read in described DRAM cache 231, described CPU21 accesses described PCRAM main memory 232 and is read out.
Refer to the CPU shown in Fig. 3 and perform to read the flow chart of data, step S20, described CPU21 are first carried out and perform to read the operation of data, then perform step S21.
In the step s 21, described CPU21 first determines whether whether there is, in described DRAM cache 231, the data page to read, and if so, then goes to step S22, if it is not, then then perform step S23.
In step S22, CPU21 reads from described DRAM cache 231.
In step S23, CPU21 reads from described PCRAM main memory 232.
In the step writing data of the EMS memory management process of the present invention, when described CPU21 performs the operation writing data, described CPU21 detects in described DRAM cache 231 whether there is the data page to write, if existing, then write data into described DRAM231 buffer memory, if it is not, the data page then will write carries out write operation after being read into described DRAM cache by described PCRAM main memory again. Refer to the CPU shown in Fig. 4 and perform to write the flow chart of data, step S10, described CPU21 are first carried out and perform to write the operation of data, then perform step S11.
In step s 11, described CPU21 judges whether there is, in described DRAM cache 231, the data page to write, and if so, then goes to step S15, if it is not, then then perform step S12.
In step s 12, system is dished out page fault, then performs step S13.
In step s 13, described CPU21 goes to described PCRAM main memory 232, then performs step S14.
In step S14, the described data page being intended to write is read in described DRAM cache 231 by described CPU21 by described PCRAM main memory 232.
In step S15, described CPU21 is to write data in described DRAM cache 231.
It should be noted that
In the step of the data page displacement of the EMS memory management process of the present invention, the step of data page displacement, system is using the described DRAM cache 231 buffer memory as PCRAM232 main memory, when described DRAM cache 231 insufficient space, idle data page (namely temporarily not accessing or access times less data page) in described DRAM cache 231 is replaced to described PCRAM232 main memory by system in loop equilibrium mode, when the data page displaced reads in described DRAM main memory 232 again, shared by this data page, the memory space of described PCRAM main memory 232 is automatically releasable, in other words, when CPU21 finds that the memory space in described DRAM cache 231 is when deficiency, need data page idle in DRAM cache 231 to replace in PCRAM main memory 232 in the way of loop equilibrium, in the present embodiment, the described flow process replaced in the way of loop equilibrium is in as shown in Figure 5:
Step S30 is first carried out, and the displacement order of described data page, when the CPU21 memory space found in DRAM cache 231 performs step S31 when deficiency.
In step S31, the idle data page that system is concluded and labelling needs are replaced PCRAM main memory 232 from DRAM cache 231, then perform step S32.
In step s 32, when idle data page in described DRAM cache 231 is replaced to described PCRAM main memory 232 by system, the page displaced is deposited successively by described PCRAM main memory 232 sequence of addresses, described CPU21 once deposits before judging described PCRAM main memory 232 whether the position of replaced idle data page has reached the maximum address of described PCRAM main memory 232, if, then judge that previous cycle terminates, and enters subsequent cycle, namely perform step S330; If it is not, be then judged to previous cycle, namely perform step S340.
In step S330, namely in described subsequent cycle, described CPU21 starts to scan idle block address region from the lowest address of described PCRAM main memory 232; Then step S331 is performed.
In step S331, described idle data page is stored in the first free block address area scanned; Then step S332 is performed.
In step S332, to data page one enumerator of distribution that should leave unused in described DRAM cache 231, and it is marked in the bit position of its bitmap, and this enumerator is initialized as 1; Then step S333 is performed.
In step S333, the enumerator of all assignment in the bitmap of described DRAM cache 231 is added 1; Then step S334 is performed.
In step S334, search the page more than a preset value N in the enumerator of those assignment; Then step S335 is performed.
In step S335, previous cycle will be mapped to the described idle data page exceeding the page setting value N corresponding, to be again read in described DRAM cache 231, and the counter O reset that the idle data page that is again read in described DRAM cache 231 by this is corresponding, and, when a certain enumerator is value arrival preset value N, the corresponding data page displaced will be re-mapped to previous cycle: the corresponding data page displaced is read in DRAM by system again, is then stored in PCRAM main memory 232 according still further to the process of general page frame replacement.
In step S340, namely in described previous cycle, described CPU21 scans idle block address region described PCRAM main memory 232 from address growing direction; Then step S341 is performed.
In step S341, described idle data page is stored in the first free block address area scanned; Then step S342 is performed.
In step S342, to data page one enumerator of distribution that should leave unused in described DRAM cache 231, and it is marked in the bit position of its bitmap, and this enumerator is initialized as 1; Then step S343 is performed.
In step S343, the enumerator of all assignment in the bitmap of described DRAM cache 231 is added 1; Then step S344 is performed.
In step S344, search the page more than a preset value N in the enumerator of those assignment; Then step S345 is performed.
In step S345, previous cycle will be mapped to the described idle data page exceeding the page setting value N corresponding, to be again read in described DRAM cache 231, and the counter O reset that the idle data page that is again read in described DRAM cache 231 by this is corresponding, and, when a certain enumerator is value arrival preset value N, the corresponding data page displaced will be re-mapped to previous cycle: the corresponding data page displaced is read in DRAM by system again, is then stored in PCRAM main memory 232 according still further to the process of general page frame replacement.
In sum, the EMS memory management process of the PCR-based AM main memory application of the present invention, using the DRAM buffer memory as PCRAM, during write operation, CPU calls the page data in DRAM, it is achieved that demand to the required erasable number of times of PCRAM and the performance such as writing rate, fatigability during CPU write operation; During read operation, based on reading characteristic at random, CPU can directly read the data in DRAM and PCRAM, is greatly saved workload during system read operation. And the main memory effect of PCR-based AM of the present invention not only can realize the fast write operation to internal storage data but also can realize the random reading of data in PCRAM main memory, being greatly saved the energy that read operation consumes, the database application based on mass data read operation is had more obvious advantage by the present invention especially. So, the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
Above-described embodiment is illustrative principles of the invention and effect thereof only, not for the restriction present invention. Above-described embodiment all under the spirit and category of the present invention, can be modified or change by any those skilled in the art. Therefore, art has usually intellectual such as modifying without departing from all equivalences completed under disclosed spirit and technological thought or change, must be contained by the claim of the present invention.
Claims (6)
1. the EMS memory management process of a PCR-based AM main memory application, it is applied in the system built by CPU, internal memory and external memory described internal memory is managed operation when described CPU performs read/write operation, described internal memory includes DRAM cache and PCRAM main memory, it is characterized in that, described EMS memory management process includes:
The step of data page displacement, system is using the described DRAM cache buffer memory as PCRAM main memory, when described DRAM cache insufficient space, idle data page in described DRAM cache is replaced to described PCRAM main memory by system in loop equilibrium mode, when the data page displaced reads in described DRAM main memory again, shared by this data page, the memory space of described PCRAM main memory is automatically releasable;
Write the step of data, when described CPU performs the operation writing data, described CPU detects in described DRAM cache whether there is the data page to write, if existing, then write data into described DRAM cache, if it is not, the data page then will write carries out write operation after being read into described DRAM cache by described PCRAM main memory again;
Reading the step of data, when described CPU performs the operation reading data, first described CPU accesses described DRAM cache, and when not reading the data page being intended to read in described DRAM cache, described CPU accesses described PCRAM main memory and is read out;
Wherein, when idle data page in described DRAM cache is replaced to described PCRAM main memory by system, the page displaced is deposited successively by described PCRAM core address order, described CPU once deposits before judging described PCRAM main memory whether the position of replaced idle data page has reached the maximum address of described PCRAM main memory, if it is not, be then judged to previous cycle, if, then judge that previous cycle terminates, and enters subsequent cycle.
2. the EMS memory management process of PCR-based AM main memory according to claim 1 application, it is characterised in that: in described previous cycle, comprise the following steps:
1) described CPU scans idle block address region described PCRAM main memory from address growing direction;
2) described idle data page is stored in the first free block address area scanned;
3) to data page one enumerator of distribution that should leave unused in described DRAM cache, and it is marked in the bit position of its bitmap, and this enumerator is initialized as 1;
4) enumerator of assignment all in the bitmap of described DRAM cache is added 1;
5) page more than a preset value N in the enumerator of those assignment is searched;
6) the idle data page corresponding with the described page exceeding preset value N is mapped to previous cycle, to be again read in described DRAM cache, and the counter O reset that the idle data page that this is again read in described DRAM cache is corresponding.
3. the EMS memory management process of PCR-based AM main memory according to claim 1 application, it is characterised in that: in described subsequent cycle, comprise the following steps:
1) described CPU starts to scan idle block address region from the lowest address of described PCRAM main memory;
2) described idle data page is stored in the first free block address area scanned;
3) to data page one enumerator of distribution that should leave unused in described DRAM cache, and it is marked in the bit position of its bitmap, and this enumerator is initialized as 1;
4) enumerator of assignment all in the bitmap of described DRAM cache is added 1;
5) page more than a preset value N in the enumerator of those assignment is searched;
6) the idle data page corresponding with the described page exceeding preset value N is mapped to previous cycle, to be again read in described DRAM cache, and the counter O reset that the idle data page that this is again read in described DRAM cache is corresponding.
4. the EMS memory management process of the PCR-based AM main memory application according to claim 1,2 or 3, it is characterized in that: when described CPU performs the operation writing data, described CPU first determines whether whether there is the data page to write in described DRAM cache, if, then to write data in described DRAM cache, if it is not, then system is dished out page fault, and go to described PCRAM main memory, the described data page to write is read in described DRAM cache so that write data by described PCRAM main memory.
5. the EMS memory management process of PCR-based AM main memory according to claim 1 application, it is characterized in that: when described CPU performs the operation reading data, described CPU first determines whether whether there is the data page to read in described DRAM cache, if, then read from described DRAM cache, if it is not, then read from described PCRAM main memory.
6. the EMS memory management process of PCR-based AM main memory according to claim 1 application, it is characterised in that: described system also includes the high-speed cache being connected between described CPU and internal memory.
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| CN104252421A (en) * | 2013-06-25 | 2014-12-31 | 华为技术有限公司 | Caching method and caching device |
| CN104424124B (en) * | 2013-09-10 | 2018-07-06 | 联想(北京)有限公司 | Memory device, electronic equipment and the method for controlling memory device |
| CN105279113B (en) * | 2014-07-03 | 2018-01-30 | 中国科学院声学研究所 | Reduce the methods, devices and systems that DRAM Cache missings access |
| CN105808452B (en) * | 2014-12-29 | 2019-04-26 | 北京兆易创新科技股份有限公司 | The data progression process method and system of micro-control unit MCU |
| CN104899154B (en) * | 2015-06-10 | 2017-08-29 | 山东大学 | The page management method hosted is mixed based on embedded system |
| US10268382B2 (en) * | 2015-06-18 | 2019-04-23 | Mediatek Inc. | Processor memory architecture |
| CN109508301B (en) * | 2017-09-14 | 2021-10-29 | 中国移动通信集团重庆有限公司 | Terminal, application data processing method, data processing device and storage medium |
| CN109240612A (en) * | 2018-08-29 | 2019-01-18 | 郑州云海信息技术有限公司 | A kind of method that magnanimity metadata cache accelerates |
| CN111210858B (en) * | 2019-12-24 | 2021-11-09 | 山东大学 | Method and system for relieving write interference of phase change memory |
| CN112486792A (en) * | 2020-12-21 | 2021-03-12 | 北京安兔兔科技有限公司 | Operation performance testing method and device, electronic equipment and storage medium |
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