CN103019955A - Memory management method based on application of PCRAM (phase change random access memory) main memory - Google Patents
Memory management method based on application of PCRAM (phase change random access memory) main memory Download PDFInfo
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Abstract
The invention provides a memory management method based on application of a PCRAM (phase change random access memory) main memory. The memory management method is applied in a system constructed by a CPU (central processing unit), an internal memory and an external memory, and comprises the following steps that a DRAM (dynamic random access memory) cache is taken as a cache of the PCRAM main memory, and idle pages in the DRAM cache are substituted into the PCRAM main memory in a circulation and balance manner by a system; when the operation of writing data is implemented by the CPU, the CPU detects whether a to-be-written data page exists in the DRAM cache, if yes, data is written into the DRAM cache, otherwise the to-be-written data page is read into the DRAM cache by the PCRAM main memory to carry out the operation of writing, and the requirements on needed erasing and writing times, a writing speed, fatigue performance and the like of the PCRAM main memory are realized when the operation of CPU writing is carried out; and when the operation of reading is implemented by the CPU, the CPU firstly accesses the DRAM cache, when a to-be-accessed data page is not read in the DRAM, the CPU accesses the PCRAM main memory for reading, so that the direct reading of data in the DRAM cache and the PCRAM main memory by the CPU can be realized, and the workload during the operation of a system is greatly saved.
Description
Technical field
The present invention relates to a kind of memory management technology, particularly relate to the EMS memory management process that a kind of PCR-based AM main memory is used.
Background technology
Internal memory (Memory) is one of parts important in the computing machine, and it is the bridge of linking up with CPU (central processing unit).The operation of all programs is all carried out in internal memory in the computing machine, so the performance of internal memory is very large on the impact of computing machine.Internal memory is also referred to as internal storage, its effect be for the operational data of temporarily depositing CPU and with the data of the external memory storage such as hard disk exchange.Thereby, the important hardware device of computer products, its software systems realize that various functions all be unable to do without and internally deposit into row read-write.At present industry realizes by operating system internal memory bassoon reason, so software systems all will depend on operating system when using internal memory.Operating system can be divided into two kinds of dynamic management and static managements to internal memory bassoon reason.
The memory device of computer system is divided into internal storage and external storage, and the data that program and program will be accessed all must could be moved by graftabl.Main memory is the kernal hardware of computer system, is another critical function of operating system to the management of storer.
Program corresponding address after compiling is virtual address (32 4G), and physical address (may be 1G) is the physical memory address.When program is loaded into the mapping that needs to carry out virtual address and physical address the internal memory from hard disk, because our physical address does not have 4G, many do not have the program of operation to be swapped out, management between them then is to manage by MMU (Memory Management Unit, i.e. memory management unit).Our internal memory is very little at first, usually only has several million capacity, if ceaselessly transposing has just consumed a large amount of resources between hard disk and internal memory, and the reading speed of hard disk is very slow, so just designed Swap subregion (exchange area), although it is divided out from hard disk, its form is to approach with internal memory.So the program of not moving in internal memory can be put in the Swap subregion, change to like this and the speed that swaps out will increase.
Exchange partition is used when being filled at physical memory (RAM).If system needs more memory source, and physical memory has been full of, sluggish page or leaf will be moved to swapace in the internal memory.Although swapace can be for offering help with the machine of a small amount of internal memory, it is replacement to internal memory that this method should not be taken as.Swapace is positioned on the hard disk drive, and it is slower than entering physical memory.
Exchange (Swapping) technology can be delivered to temporary transient inexecutable program in the external memory when concurrent executions of a plurality of programs, thus acquisition free memory space load new program, or read in and be kept in the external memory and be in the program of ready state.Cross-over unit is the address space of whole process.Switching technology is usually used in multiprogrammed system or the small-sized time-sharing system, is used in conjunction with the partition type storage administration and is called " exchange " or " rolling into/roll out ".One of its advantage is the program number that increases concurrent running, and provides the suitable response time to the user; Comparing another significant advantage of switching technology with soverlay technique is not affect program structure.Switching technology itself also exists deficiency, for example: the control that changes to and swap out is increased the processor expense; The whole address space of program is all exchanged, and does not consider the statistical property of address access in the implementation.
In the environment that current mobile computing is popularized day by day, it is unable to do what one wishes that the memory technology in past has seemed, is difficult to especially satisfy that electronic product is less to storage volume, the requirement of system power dissipation.Development along with semiconductor and storage chip technology, the good characteristic of the storeies such as the DRAM, the SRAM that combine main flow on the present semiconductor memory market of novel non-volatile computer memory technology and FLASH, but also have micro superior performance, non-volatile, zero access, have extended cycle life, data stability is strong, the many advantages such as low in energy consumption, is considered to the best solution of non-volatile memory technology of future generation.
See also Fig. 1 a and Fig. 1 c, show three kinds of hardware structure schematic diagram that the PCRAM main memory is used in the prior art, comprise CPU11, high-speed cache (i.e. module CACHE in the diagram) 12, internal memory 13, external memory (i.e. module SSD/HARD DISK in the diagram) 14, the memory capacity of above-mentioned three kinds of hardware structures reduces successively, and every bit memory cost increases progressively successively, memory stores speed increases successively, the memory stores time decreased.But in the application of reality, still there is following problem:
Be the hardware structure that PCRAM as shown in Figure 1a uses, use PCRAM to substitute traditional DRAM and enlarge memory size PCRAM, but the erasable number of times of PCR-based AM and the limitation of writing the performances such as data speed, antifatigue far do not reach CPU data are accessed required speed and number of times at present.
The for another example hardware structure used of the PCRAM shown in Fig. 1 b and Fig. 1 c, the two buffer memory that all is based on DRAM are used for application, and namely storage system is made of buffer memory and internal memory, namely have the high speed of DRAM that the mass-storage system of PCRAM is arranged again.Wherein, will access in the hardware structure shown in Fig. 1 b than deposit data more frequently in DRAM, access not frequently deposit data at PCRAM; In the hardware structure shown in Fig. 1 c with the L2 cache of DRAM as PCRAM, balance the demand between writing rate, erasable number of times and fatigue properties between PCRAM and the CPU.But the weak point of above-mentioned two schemes is, if when CPU only need to read in the PCRAM buffer memory low volume data in some data page, and still it read in DRAM for the CPU access, workload and system power dissipation when greatly increased read operation this moment.
Thereby the memory management technology that how to provide a kind of PCR-based AM main memory to use to solve above-mentioned problems of the prior art and deficiency, has become the problem that the practitioner in the art competitively studies.
Summary of the invention
The shortcoming of prior art in view of the above, the EMS memory management process that the object of the present invention is to provide a kind of PCR-based AM main memory to use improves the purpose to the required erasable number of times of PCRAM main memory and the performances such as writing rate and reduction fatigability when the write operation in order to realize CPU.
Another object of the present invention is to provide a kind of internal storage management system and method for PCR-based AM main memory application, in order to when the CPU read operation, can directly read data in DRAM and the PCRAM based on reading at random characteristic CPU, and then the purpose of the workload when having realized greatly saving system's read operation.
Reach for achieving the above object other relevant purposes, the invention provides the EMS memory management process that a kind of PCR-based AM main memory is used, be applied in by CPU, in the system that internal memory and external memory make up when described CPU carries out read/write operation, described internal memory is managed operation, described internal memory comprises DRAM buffer memory and PCRAM main memory, it is characterized in that, described EMS memory management process comprises: the step of data page displacement, system is with the buffer memory of described DRAM buffer memory as the PCRAM main memory, when described DRAM inadequate buffer space, system replaces the idle data page in the described DRAM buffer memory to described PCRAM main memory in the loop equilibrium mode, when the data page that displaces read in described DRAM main memory again, the storage space of the shared described PCRAM main memory of this data page discharged automatically; Write the step of data, when the operation of data is write in described CPU execution, described CPU detects in the described DRAM buffer memory whether have the data page that will write, if exist, then data are write described DRAM buffer memory, if not, the data page that then will write carries out write operation after being read into described DRAM buffer memory by described PCRAM main memory again; The step of read data, when described CPU carried out the operation of read data, described CPU at first accessed described DRAM buffer memory, and when not reading the data page of wanting to read in described DRAM buffer memory, described CPU accesses described PCRAM main memory and reads.
In EMS memory management process of the present invention, when system replaces the idle data page in the described DRAM buffer memory to described PCRAM main memory, deposit successively the page or leaf that displaces by described PCRAM core address order, described CPU judges whether the position of once depositing replaced idle data page before the described PCRAM main memory has reached the maximum address of described PCRAM main memory, if not, then be judged to be current circulation, if, judge that then current circulation finishes, and enters next circulation.
Particularly, in described current circulation, may further comprise the steps: 1) described CPU scans idle block address zone the described PCRAM main memory from the address growing direction; 2) described idle data page is stored in the first free block address area that scans; 3) in described DRAM buffer memory, the data page that should leave unused is distributed a counter, and give mark in the bit position of its bitmap, and this counter is initialized as 1; 4) counter with all assignment in the bitmap of described DRAM buffer memory adds 1; 5) search the page that surpasses a preset value N in the counter of those assignment; 6) the idle data page corresponding with the described page that surpasses the value of establishing N is mapped to current circulation, again being read in the described DRAM buffer memory, and this will be read into counter O reset corresponding to idle data page in the described DRAM buffer memory again.
In described next circulation, may further comprise the steps: 1) described CPU begins to scan idle block address zone from the lowest address of described PCRAM main memory; 2) described idle data page is stored in the first free block address area that scans; 3) in described DRAM buffer memory, the data page that should leave unused is distributed a counter, and give mark in the bit position of its bitmap, and this counter is initialized as 1; 4) counter with all assignment in the bitmap of described DRAM buffer memory adds 1; 5) search the page that surpasses a preset value N in the counter of those assignment; 6) the idle data page corresponding with the described page that surpasses the value of establishing N is mapped to current circulation, again being read in the described DRAM buffer memory, and this will be read into counter O reset corresponding to idle data page in the described DRAM buffer memory again.
When the operation of data is write in described CPU execution, described CPU at first judges in the described DRAM buffer memory whether have the data page that will write, if, data writing in the described DRAM buffer memory then, if not, system's page fault of dishing out then, and go to described PCRAM main memory, the described data page of wanting to write is read in the described DRAM buffer memory so that data writing by described PCRAM main memory.
In EMS memory management process of the present invention, when described CPU carried out the operation of read data, described CPU at first judged in the described DRAM buffer memory whether have the data page that will read, if, then from described DRAM buffer memory, read, if not, then from described PCRAM main memory, read.
In EMS memory management process of the present invention, described system also comprises the high-speed cache that is connected between described CPU and the internal memory.
As mentioned above, the EMS memory management process that PCR-based AM main memory of the present invention is used is with the buffer memory of DRAM as PCRAM, during write operation, CPU calls the page data in the DRAM, when having realized the CPU write operation to the demand of the performances such as the required erasable number of times of PCRAM and writing rate, fatigability; During read operation, based on reading at random characteristic, CPU can directly read the data in DRAM and the PCRAM, the workload when greatly having saved system's read operation.And the main memory effect that the present invention is based on PCRAM not only can realize the quick write operation of internal storage data but also can realize reading at random data in the PCRAM main memory, greatly save the energy that read operation consumes, the present invention has more obvious advantage to the database application based on the mass data read operation especially.
Description of drawings
Fig. 1 a and Fig. 1 c are shown as three kinds of hardware structure schematic diagram that the PCRAM main memory is used in the prior art.
Fig. 2 is shown as the system principle diagram of using EMS memory management process of the present invention.
Fig. 3 is shown as the process flow diagram of CPU read data in the EMS memory management process of the present invention.
Fig. 4 is shown as the process flow diagram that CPU in the EMS memory management process of the present invention writes data.
Fig. 5 is shown as the process flow diagram that the loop equilibrium mode is replaced in the EMS memory management process of the present invention.
Embodiment
Below by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by content disclosed in the present specification.The present invention can also be implemented or be used by other different embodiment, and the every details in this instructions also can be based on different viewpoints and application, carries out various modifications or change under the spirit of the present invention not deviating from.
See also Fig. 2 to Fig. 5, need to prove, the diagram that provides in the present embodiment only illustrates basic conception of the present invention in a schematic way, satisfy only show in graphic with the present invention in relevant assembly but not component count, shape and size drafting when implementing according to reality, kenel, quantity and the ratio of each assembly can be a kind of random change during its actual enforcement, and its assembly layout kenel also may be more complicated.
As shown in the figure, the invention provides the EMS memory management process that a kind of PCR-based AM main memory is used, be applied in the system that is made up by CPU21, high-speed cache (CACHE) 22, internal memory 23 and external memory 24 (for example being SSD or Hard disk), in order to when described CPU21 carries out read/write operation described internal memory 23 is managed operation, described internal memory 23 comprises DRAM buffer memory 231 and PCRAM main memory 232.
When described CPU21 carried out the operation of read data, described CPU21 at first accessed described DRAM buffer memory 231, and when not reading the data page of wanting to read in described DRAM buffer memory 231, described CPU21 accesses described PCRAM main memory 232 and reads.
See also the process flow diagram that CPU shown in Figure 3 carries out read data, execution in step S20 at first, described CPU21 carries out the operation of read data, then execution in step S21.
In step S21, described CPU21 at first judges in the described DRAM buffer memory 231 whether have the data page that will read, if, then go to step S22, if not, then follow execution in step S23.
In step S22, CPU21 reads from described DRAM buffer memory 231.
In step S23, CPU21 reads from described PCRAM main memory 232.
In the step of writing data of EMS memory management process of the present invention, when the operation of data is write in described CPU21 execution, described CPU21 detects in the described DRAM buffer memory 231 whether have the data page that will write, if exist, then data are write described DRAM231 buffer memory, if not, the data page that then will write carries out write operation after being read into described DRAM buffer memory by described PCRAM main memory again.See also CPU shown in Figure 4 and carry out the process flow diagram of writing data, execution in step S10 at first, described CPU21 carries out the operation of writing data, then execution in step S11.
In step S11, described CPU21 judges in the described DRAM buffer memory 231 whether have the data page that will write, if, then go to step S15, if not, then follow execution in step S12.
In step S12, system's page fault of dishing out, then execution in step S13.
In step S13, described CPU21 goes to described PCRAM main memory 232, then execution in step S14.
In step S14, described CPU21 reads in the described data page of wanting to write in the described DRAM buffer memory 231 by described PCRAM main memory 232.
In step S15, described CPU21 data writing in the described DRAM buffer memory 231.
Need to prove,
In the step that the data page of EMS memory management process of the present invention is replaced, the step of data page displacement, system is with the buffer memory of described DRAM buffer memory 231 as the PCRAM232 main memory, when described DRAM buffer memory 231 insufficient space, system replaces the idle data page in the described DRAM buffer memory 231 (namely temporarily do not access or data page that access times are less) to described PCRAM232 main memory in the loop equilibrium mode, when the data page that displaces reads in described DRAM main memory 232 again, the storage space of the shared described PCRAM main memory 232 of this data page discharges automatically, in other words, when CPU21 finds that storage space in the described DRAM buffer memory 231 is in deficiency, idle data page in the DRAM buffer memory 231 need to be replaced in the PCRAM main memory 232 in the mode of loop equilibrium, in the present embodiment, described flow process of replacing in the mode of loop equilibrium is as shown in Figure 5:
Execution in step S30 at first, described data page displacement order, execution in step S31 when CPU21 finds that storage space in the DRAM buffer memory 231 is in deficiency.
In step S31, system concludes and the mark idle data page need to be from DRAM buffer memory 231 displacement to PCRAM main memory 232, then execution in step S32.
In step S32, when system replaces the idle data page in the described DRAM buffer memory 231 to described PCRAM main memory 232, deposit successively the page or leaf that displaces by described PCRAM main memory 232 sequence of addresses, described CPU21 judges whether the position of once depositing replaced idle data page before the described PCRAM main memory 232 has reached the maximum address of described PCRAM main memory 232, if, judge that then current circulation finishes, and enters next circulation, i.e. execution in step S330; If not, then be judged to be current circulation, i.e. execution in step S340.
In step S330, namely in described next circulation, described CPU21 begins to scan idle block address zone from the lowest address of described PCRAM main memory 232; Follow execution in step S331.
In step S331, described idle data page is stored in the first free block address area that scans; Follow execution in step S332.
In step S332, in described DRAM buffer memory 231, the data page that should leave unused is distributed a counter, and give mark in the bit position of its bitmap, and this counter is initialized as 1; Follow execution in step S333.
In step S333, the counter of all assignment in the bitmap of described DRAM buffer memory 231 is added 1; Follow execution in step S334.
In step S334, search the page that surpasses a preset value N in the counter of those assignment; Follow execution in step S335.
In step S335, to be mapped to current circulation with the described idle data page corresponding above the page of the value of establishing N, again to be read in the described DRAM buffer memory 231, and this is read into counter O reset corresponding to idle data page in the described DRAM buffer memory 231 again, and, when a certain counter is value arrival preset value N, the corresponding data page that displaces will be re-mapped to current circulation with it: DRAM is read in again with the data page that displaces corresponding with it in system, and then is stored in the PCRAM main memory 232 according to the process of general page frame replacement.
In step S340, namely in described current circulation, described CPU21 scans idle block address zone the described PCRAM main memory 232 from the address growing direction; Follow execution in step S341.
In step S341, described idle data page is stored in the first free block address area that scans; Follow execution in step S342.
In step S342, in described DRAM buffer memory 231, the data page that should leave unused is distributed a counter, and give mark in the bit position of its bitmap, and this counter is initialized as 1; Follow execution in step S343.
In step S343, the counter of all assignment in the bitmap of described DRAM buffer memory 231 is added 1; Follow execution in step S344.
In step S344, search the page that surpasses a preset value N in the counter of those assignment; Follow execution in step S345.
In step S345, to be mapped to current circulation with the described idle data page corresponding above the page of the value of establishing N, again to be read in the described DRAM buffer memory 231, and this is read into counter O reset corresponding to idle data page in the described DRAM buffer memory 231 again, and, when a certain counter is value arrival preset value N, the corresponding data page that displaces will be re-mapped to current circulation with it: DRAM is read in again with the data page that displaces corresponding with it in system, and then is stored in the PCRAM main memory 232 according to the process of general page frame replacement.
In sum, the EMS memory management process that PCR-based AM main memory of the present invention is used is with the buffer memory of DRAM as PCRAM, during write operation, CPU calls the page data in the DRAM, when having realized the CPU write operation to the demand of the performances such as the required erasable number of times of PCRAM and writing rate, fatigability; During read operation, based on reading at random characteristic, CPU can directly read the data in DRAM and the PCRAM, the workload when greatly having saved system's read operation.And the main memory effect that the present invention is based on PCRAM not only can realize the quick write operation of internal storage data but also can realize reading at random data in the PCRAM main memory, greatly save the energy that read operation consumes, the present invention has more obvious advantage to the database application based on the mass data read operation especially.So the present invention has effectively overcome various shortcoming of the prior art and the tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not is used for restriction the present invention.Any person skilled in the art scholar all can be under spirit of the present invention and category, and above-described embodiment is modified or changed.Therefore, have in the technical field under such as and know that usually the knowledgeable modifies or changes not breaking away from all equivalences of finishing under disclosed spirit and the technological thought, must be contained by claim of the present invention.
Claims (7)
1. the EMS memory management process used of a PCR-based AM main memory, be applied in the system that is made up by CPU, internal memory and external memory when described CPU carries out read/write operation, described internal memory is managed operation, described internal memory comprises DRAM buffer memory and PCRAM main memory, it is characterized in that, described EMS memory management process comprises:
The step of data page displacement, system is with the buffer memory of described DRAM buffer memory as the PCRAM main memory, when described DRAM inadequate buffer space, system replaces the idle data page in the described DRAM buffer memory to described PCRAM main memory in the loop equilibrium mode, when the data page that displaces read in described DRAM main memory again, the storage space of the shared described PCRAM main memory of this data page discharged automatically;
Write the step of data, when the operation of data is write in described CPU execution, described CPU detects in the described DRAM buffer memory whether have the data page that will write, if exist, then data are write described DRAM buffer memory, if not, the data page that then will write carries out write operation after being read into described DRAM buffer memory by described PCRAM main memory again;
The step of read data, when described CPU carried out the operation of read data, described CPU at first accessed described DRAM buffer memory, and when not reading the data page of wanting to read in described DRAM buffer memory, described CPU accesses described PCRAM main memory and reads.
2. the EMS memory management process used of PCR-based AM main memory according to claim 1, it is characterized in that: when system replaces the idle data page in the described DRAM buffer memory to described PCRAM main memory, deposit successively the page or leaf that displaces by described PCRAM core address order, described CPU judges whether the position of once depositing replaced idle data page before the described PCRAM main memory has reached the maximum address of described PCRAM main memory, if not, then be judged to be current circulation, if, judge that then current circulation finishes, and enters next circulation.
3. the EMS memory management process used of PCR-based AM main memory according to claim 2 is characterized in that: in described current circulation, may further comprise the steps:
1) described CPU scans idle block address zone the described PCRAM main memory from the address growing direction;
2) described idle data page is stored in the first free block address area that scans;
3) in described DRAM buffer memory, the data page that should leave unused is distributed a counter, and give mark in the bit position of its bitmap, and this counter is initialized as 1;
4) counter with all assignment in the bitmap of described DRAM buffer memory adds 1;
5) search the page that surpasses a preset value N in the counter of those assignment;
6) the idle data page corresponding with the described page that surpasses the value of establishing N is mapped to current circulation, again being read in the described DRAM buffer memory, and this will be read into counter O reset corresponding to idle data page in the described DRAM buffer memory again.
4. the EMS memory management process used of PCR-based AM main memory according to claim 2 is characterized in that: in described next circulation, may further comprise the steps:
1) described CPU begins to scan idle block address zone from the lowest address of described PCRAM main memory;
2) described idle data page is stored in the first free block address area that scans;
3) in described DRAM buffer memory, the data page that should leave unused is distributed a counter, and give mark in the bit position of its bitmap, and this counter is initialized as 1;
4) counter with all assignment in the bitmap of described DRAM buffer memory adds 1;
5) search the page that surpasses a preset value N in the counter of those assignment;
6) the idle data page corresponding with the described page that surpasses the value of establishing N is mapped to current circulation, again being read in the described DRAM buffer memory, and this will be read into counter O reset corresponding to idle data page in the described DRAM buffer memory again.
5. according to claim 1, the EMS memory management process of 2,3 or 4 described PCR-based AM main memories application, it is characterized in that: when the operation of data is write in described CPU execution, described CPU at first judges in the described DRAM buffer memory whether have the data page that will write, if, data writing in the described DRAM buffer memory then, if not, system's page fault of dishing out then, and go to described PCRAM main memory, the described data page of wanting to write is read in the described DRAM buffer memory so that data writing by described PCRAM main memory.
6. the EMS memory management process used of PCR-based AM main memory according to claim 1, it is characterized in that: when described CPU carries out the operation of read data, described CPU at first judges in the described DRAM buffer memory whether have the data page that will read, if, then from described DRAM buffer memory, read, if not, then from described PCRAM main memory, read.
7. the EMS memory management process used of PCR-based AM main memory according to claim 1, it is characterized in that: described system also comprises the high-speed cache that is connected between described CPU and the internal memory.
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| CN104252421A (en) * | 2013-06-25 | 2014-12-31 | 华为技术有限公司 | Caching method and caching device |
| CN104424124A (en) * | 2013-09-10 | 2015-03-18 | 联想(北京)有限公司 | Memory device, electronic equipment and method for controlling memory device |
| CN104424124B (en) * | 2013-09-10 | 2018-07-06 | 联想(北京)有限公司 | Memory device, electronic equipment and the method for controlling memory device |
| CN105279113B (en) * | 2014-07-03 | 2018-01-30 | 中国科学院声学研究所 | Reduce the methods, devices and systems that DRAM Cache missings access |
| CN105279113A (en) * | 2014-07-03 | 2016-01-27 | 中国科学院声学研究所 | Method, apparatus and system for reducing access to DRAM Cache in missing condition |
| CN105808452A (en) * | 2014-12-29 | 2016-07-27 | 北京兆易创新科技股份有限公司 | Data stage treatment method and system of MCU (Microprogrammed Control Unit) |
| CN105808452B (en) * | 2014-12-29 | 2019-04-26 | 北京兆易创新科技股份有限公司 | The data progression process method and system of micro-control unit MCU |
| CN104899154B (en) * | 2015-06-10 | 2017-08-29 | 山东大学 | The page management method hosted is mixed based on embedded system |
| CN104899154A (en) * | 2015-06-10 | 2015-09-09 | 山东大学 | Page management method based on embedded system mixed main memory |
| CN106257400A (en) * | 2015-06-18 | 2016-12-28 | 联发科技股份有限公司 | The method that processing equipment, calculating system and processing equipment access main storage |
| US10268382B2 (en) | 2015-06-18 | 2019-04-23 | Mediatek Inc. | Processor memory architecture |
| CN106257400B (en) * | 2015-06-18 | 2019-05-10 | 联发科技股份有限公司 | The method of processing equipment, computing system and processing equipment access main memory |
| CN109508301A (en) * | 2017-09-14 | 2019-03-22 | 中国移动通信集团重庆有限公司 | Terminal, using the processing method of data, data processing equipment and storage medium |
| CN109508301B (en) * | 2017-09-14 | 2021-10-29 | 中国移动通信集团重庆有限公司 | Terminal, application data processing method, data processing device and storage medium |
| CN109240612A (en) * | 2018-08-29 | 2019-01-18 | 郑州云海信息技术有限公司 | A kind of method that magnanimity metadata cache accelerates |
| CN111210858A (en) * | 2019-12-24 | 2020-05-29 | 山东大学 | Method and system for relieving write interference of phase change memory |
| CN111210858B (en) * | 2019-12-24 | 2021-11-09 | 山东大学 | Method and system for relieving write interference of phase change memory |
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