CN103019863A - Crisis emergency processing multi-core micro controller arbitration framework and working mode thereof - Google Patents
Crisis emergency processing multi-core micro controller arbitration framework and working mode thereof Download PDFInfo
- Publication number
- CN103019863A CN103019863A CN201210572843XA CN201210572843A CN103019863A CN 103019863 A CN103019863 A CN 103019863A CN 201210572843X A CN201210572843X A CN 201210572843XA CN 201210572843 A CN201210572843 A CN 201210572843A CN 103019863 A CN103019863 A CN 103019863A
- Authority
- CN
- China
- Prior art keywords
- core
- microcontroller
- data
- core microcontroller
- described multi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Hardware Redundancy (AREA)
Abstract
The invention discloses a crisis emergency processing multi-core micro controller arbitration framework, which comprises a multi-core micro controller, a non-volatile memory, a non-volatile register file unit, a volatile common storage unit, an input and output interface control unit and an arbitration logic unit, wherein the multi-core micro controller is used for realizing processing of data in the micro controller; the non-volatile memory and the non-volatile register file unit are used for storing or restoring the data of the multi-core micro controller and the data of a register; the volatile common storage unit is used for storing the data of the multi-core micro controller; the input and output interface control unit is used for controlling input and output of the multi-core micro controller; and the arbitration logic unit is used for arbitrating cores of the multi-core micro controller. With the adoption of the crisis emergency processing multi-core micro controller arbitration framework, the improvement of the system performance is not limited, when a crisis occurs, odd number of cores are kept in the multiple cores, so that the crisis is commonly processed by the odd number of cores through arbitration coordination. The invention also provides a working mode of the crisis emergency processing multi-core micro controller arbitration framework.
Description
Technical field
The present invention relates to a kind of integrated circuit, especially relate to a kind of emergency response and process multi-core microcontroller arbitration framework and mode of operation thereof.
Background technology
Polycaryon processor is that the core with a plurality of identical functions is integrated in the same chip, and whole chip externally provides service, output performance as a unified structure.Polycaryon processor is at first processed core by integrated a plurality of single-threaded processing cores or integrated a plurality of while multithreading, so that the Thread Count that whole processor can be carried out simultaneously or number of tasks are the several times of uniprocessor, this has greatly promoted the parallel performance of processor.Secondly, a plurality of nuclears are integrated in the sheet, have greatly shortened internuclear interconnection line, and internuclear communication delay step-down has improved communication efficiency, and data transfer bandwidth also is improved.Moreover, the effective shared resource of coenocytism, the utilization factor of Resources on Chip is improved, and power consumption is also along with the minimizing of device has obtained reduction.At last, coenocytism is simple, is easy to optimal design, and extendability is strong.These advantages have finally promoted the development of multinuclear and have replaced gradually uniprocessor to become main flow.In fields such as PC, server, smart mobile phones, the application of general polycaryon processor is very general.
But in the microcontroller field, the application of multi-core processor just just begins.In the very high applied environment of some reliability requirements, often adopt the lower but very reliable core microcontroller of Performance Ratio.In order to improve the reliability of computing, often same task computing odd number time (such as three times), and then arbitrate.Although can improve like this reliability of microcontroller, the cost of system is also cheap, greatly reduces the performance of system, and if this microcontroller problem has appearred for itself, will cause the paralysis of system.In order to accelerate the arithmetic speed of system, also can in system, use odd number (such as three) core microcontroller, as shown in Figure 1.Each core has independently storer, comprises program storage and data storage, and register file.Four cores also have the larger shared storage of storage space of sharing, and control with the input/output interface of outside other peripheral hardware communications.Three core microcontrollers of the prior art are processed simultaneously same task and then are arbitrated, and the performance of system increases exponentially like this, and the cost of simultaneity factor also can increase substantially.But in a single day this system has one to go wrong, and can't realize arbitration.Described front two kinds of systems still often really need the moment of high reliability all for the high reliability of microcontroller designs, i.e. the crisis moment, the probability of generation very low (for example far away＜1%).For the low-down crisis of probability of happening reliability constantly, make whole system be in all the time the state of coping with various crises.This method by the worst case design system has greatly limited the lifting of system performance.
Summary of the invention
The present invention has overcome the defective of prior art high reliability many-core systems for the restriction of performance boost, has proposed a kind of emergency response and has processed multi-core microcontroller arbitration framework and disposal route thereof.The present invention selects the multi-core processing unit of even number core, and each core is worked separately under normal mode of operation, not the lifting of restriction system system energy.When crisis occurs, keep the odd number core in a plurality of cores, by the coordination co-treatment crisis of stamping-out logical block.In the even number core of the present invention, can coordinate work between each core by arbitration logic unit even core is made mistakes still, make whole system keep the high reliability operation.
The present invention proposes a kind of emergency response and process multi-core microcontroller arbitration framework, comprising:
The multi-core microcontroller, it is the processing unit that forms based on the core of reduced instruction set computer or sophisticated vocabulary of even number for quantity, realizes processing the data in the microcontroller;
Each core separate connection in the non-volatility memorizer, itself and described multi-core microcontroller is used for preserving or recovering the data of described each core of multi-core microcontroller;
Each core separate connection in the non-volatile register file cell, itself and described multi-core microcontroller is used for preserving or recovering the data of described each core of multi-core microcontroller;
The volatility common memory, it is connected with described multi-core microcontroller, is used for storing the public data of described multi-core microcontroller;
The IO interface control module, it is connected with described multi-core microcontroller and volatility common memory, is used for controlling the input and output of described multi-core microcontroller;
Arbitration logic unit, it is connected with described multi-core microcontroller, is used for the multi-core deal with data of described multi-core microcontroller is arbitrated.
Wherein, described nonvolatile storage location comprises program storage and data-carrier store.
Wherein, described non-volatility memorizer and non-volatile register file all are nonvolatile memory and non-volatile register files of position level, its each bit had both had the common storage unit of common storer or register file function, had again nonvolatile memory cell.
Wherein, the data in institute's rheme level nonvolatile memory and the non-volatile register file in the common storage unit can deposit corresponding nonvolatile memory cell in, and the data in the nonvolatile memory cell also can return in the corresponding usually storage unit.
The invention allows for a kind of emergency response and process the mode of operation of multi-core microcontroller arbitration framework, comprising:
Normal mode of operation, described multi-core microcontroller are at full speed concurrent working state, and each core in the described multi-core microcontroller is processed respectively different tasks;
Crisis mode of operation, when described multi-core microcontroller detects crisis, described multi-core microcontroller cuts out the odd number core according to performance or the predefined rule of processing core, other last odd number core of described multi-core microcontroller is processed a task simultaneously, and by described arbitration logic unit result is arbitrated;
Recovery mode of operation, after handling described crisis, described multi-core microcontroller returns to described full speed concurrent working state.
Wherein, described crisis mode of operation comprises:
Data are preserved step, and when described multi-core microcontroller detected crisis, described multi-core microcontroller was saved in the data of common storage unit in described non-volatility memorizer and the non-volatile register file in the corresponding nonvolatile memory cell;
Dynamic adjustment step, described multi-core microcontroller detects described core, if the situation of damage or performance reduction appears in core wherein, closes described core by described arbitration logic unit; If the situation that damage or performance reduce all appears in core, described multi-core microcontroller cuts out the odd number core by arbitration logic unit according to predefined rule;
The Iogic judge step; Remaining other odd number core of described multi-core microcontroller same task of co-treatment under the coordination of described arbitration logic unit, and by described arbitration logic unit result is arbitrated.
Wherein, described recovery mode of operation comprises:
The data recovering step, the core of described multi-core microcontroller is sent data recovery control signal the data in the nonvolatile memory cell in described non-volatility memorizer and the non-volatile register file is returned in the corresponding common storage unit, and memory data and the register data of each core are restored in the described multi-core microcontroller;
The work recovering step, described arbitration logic unit is opened all cores in the described multi-core microcontroller, and core enters at full speed concurrent working state according to memory data and the register data of described recovery in the described multi-core microcontroller.
The present invention's each core under normal mode of operation is worked separately, not the lifting of restriction system system energy.When crisis occurs, keep the odd number core in a plurality of cores, by the coordination co-treatment crisis of stamping-out logical block.
In the even number core that the present invention selects, can coordinate work between each core by arbitration logic unit even core is made mistakes still, make whole system keep the high reliability operation.
When detecting crisis, the present invention preserves the data of core by non-volatile holographic storage equipment.After the complete crisis of core processing, core can read the data in the non-volatile holographic storage equipment, core is returned to process the front state of crisis, and the assurance system can return to normal operating condition.
Description of drawings
Fig. 1 is the schematic diagram of three core microcontrollers in the prior art.
Fig. 2 is the schematic diagram of multi-core microcontroller arbitration framework of the present invention.
Fig. 3 is the process flow diagram of disposal route of the present invention.
Fig. 4 is the process flow diagram of crisis job step of the present invention.
Fig. 5 is the resume work process flow diagram of step of the present invention.
Fig. 6 is the schematic flow sheet of implementation disposal route of the present invention.
Embodiment
In conjunction with following specific embodiments and the drawings, the present invention is described in further detail.Implement process of the present invention, condition, experimental technique etc., except the following content of mentioning specially, be universal knowledege and the common practise of this area, the present invention is not particularly limited content.
Shown in Fig. 1-5.1-multi-core microcontroller, 2-non-volatility memorizer, the non-volatile register file of 3-, 4-volatility common memory, 5-IO interface control module, 6-arbitration logic unit.
Emergency response of the present invention is processed multi-core microcontroller arbitration framework, as shown in Figure 2, comprising:
Multi-core microcontroller 1, it is the processing unit that forms based on the core of reduced instruction set computer or sophisticated vocabulary of even number for quantity, realizes processing the data in the microcontroller.
Each core separate connection in the non-volatility memorizer 2, itself and multi-core microcontroller 1 comprises program storage and data-carrier store, is used for preserving or recovering the data of multi-core microcontroller 1 each core.
Each core separate connection in the non-volatile register file 3, itself and multi-core microcontroller 1 is used for preserving or recovering the register data of multi-core microcontroller.
Volatility common memory 4, it is connected with multi-core microcontroller 1, is used for the public data of storage multi-core microcontroller 1.
IO interface control module 5, it is connected with multi-core microcontroller 1 and volatility common memory 4, is used for the input and output of control multi-core microcontroller 1.
Arbitration logic unit 6, it is connected with described multi-core microcontroller 1, is used for the multi-core deal with data of multi-core microcontroller 1 is arbitrated.
Preferably, non-volatility memorizer 2 comprises program storage and data-carrier store.
Preferably, non-volatility memorizer 2 and non-volatile register file 3 all are nonvolatile memory and non-volatile register files of position level, its each bit had both had the common storage unit of common storer or register file function, had again nonvolatile memory cell.
Preferably, the data in position level nonvolatile memory and the non-volatile register file in the common storage unit can deposit corresponding nonvolatile memory cell in, and the data in the nonvolatile memory cell also can return in the corresponding usually storage unit.
As shown in Figure 3, emergency response of the present invention is processed the mode of operation of multi-core microcontroller arbitration framework, comprising:
Normal mode of operation, multi-core microcontroller 1 are at full speed concurrent working state, and each core in the multi-core microcontroller 1 is processed respectively different tasks.
Crisis mode of operation; when multi-core microcontroller 1 detects crisis; multi-core microcontroller 1 cuts out the odd number core according to performance or the predefined rule of processing core; multi-core microcontroller 1 other last odd number core is processed a task simultaneously, and is arbitrated by 6 pairs of results of arbitration logic unit.
Recovery mode of operation, after handling crisis, multi-core microcontroller 1 returns at full speed concurrent working state.
As shown in Figure 4, the crisis mode of operation among the present invention comprises:
Data are preserved step, and when multi-core microcontroller 1 detected crisis, multi-core microcontroller 1 was saved in the data of common storage unit in non-volatility memorizer 2 and the non-volatile register file 3 in the corresponding nonvolatile memory cell.
Dynamic adjustment step, 1 pair of multi-core of multi-core microcontroller detects, if the situation of damage or performance reduction appears in core wherein, closes described core by arbitration logic unit 6.If the situation that damage or performance reduce all appears in core, multi-core microcontroller 1 cuts out the odd number core by arbitration logic unit 6 according to predefined rule.
The Iogic judge step.Multi-core microcontroller 1 remaining other odd number core same task of co-treatment under the coordination of arbitration logic unit 6, and arbitrated by 6 pairs of results of arbitration logic unit.
As shown in Figure 5, the recovery mode of operation among the present invention comprises:
The data recovering step, the core of multi-core microcontroller 1 is sent data recovery control signal the data in the nonvolatile memory cell in non-volatility memorizer 2 and the non-volatile register file 3 is returned in the corresponding common storage unit, and the memory data of each core and register data are restored in the multi-core microcontroller 1.
The work recovering step, arbitration logic unit 6 is opened all cores in the multi-core microcontroller 1, and core enters at full speed concurrent working state according to the memory data that recovers and register data in the multi-core microcontroller 1.
Embodiment 1: the deposit data of Nonvolatile storage unit and output
Emergency response of the present invention is processed multi-core microcontroller arbitration framework both can satisfy system in the demand of constantly high-performance operation of non-crisis, can satisfy again the constantly requirement of high reliability of crisis.The present embodiment is take four core processing units as example, as shown in Figure 2, each core can be based on the processing core of reduced instruction set computer (RISC) or sophisticated vocabulary (CISC), each core has independently non-volatility memorizer 2 (comprising program storage and data-carrier store), and non-volatile register file 3.Non-volatility memorizer 2 is characterised in that each data bit adds a volatilization storage unit (such as phase-change memory cell PRAM by the storage unit (such as SRAM) of a volatilization, magnetic cell MRAM, resistance-change memory unit R RAM, flash cell flash etc.).
When core is carried out access to data or program be identical based on the SRAM static memory usually; but after core obtained depositing current data the order of non-volatility memorizer 2 in, multi-core microcontroller 1 can be carried out this instruction and the data in its volatilization storage unit is saved in the non-volatility memorizer 2 by volatility common memory 4 by corresponding control circuit.After if same core obtains recovering the instruction of data from non-volatility memorizer 2, multi-core microcontroller 1 can be carried out this instruction and return in the volatilization storage unit by the data of storer with non-volatility memorizer 2 by corresponding control circuit.
Non-volatile register file 3 features and nonvolatile memory are similar, and its each data bit also has corresponding nonvolatile memory cell, and multi-core microcontroller 1 is identical with common register file based on SRAM when using register to carry out computing.But non-volatile register file 3 is similar with non-volatility memorizer 2, also has the function that deposits data in non-volatile unit or recover data from nonvolatile memory cell.
Embodiment 2: the flow process of processing crisis
The micro controller frame that the present embodiment proposes is divided into two kinds of mode of operations: normal mode of operation and crisis mode of operation.
As shown in Figure 6, under normal mode of operation, four core microcontrollers are in parallel at full speed mode of operation, and the different task that each core processing system distributes makes system be in optimum performance.
When system detects crisis; four core microcontrollers enter the emergency response state; at first the common memory 4 (comprising program storage and data-carrier store) of the current use of each core and the value of register file (register file) are saved in non-volatility memorizer 2 and the non-volatile register file 3, namely preserve standing state.
Four core microcontrollers cut out the odd number core according to performance or the predefined rule of processing core, and remaining odd number core is processed a task simultaneously.Four core microcontrollers are carried out trace routine, if there is one to have and damage or degradation in four cores, by IO interface control module 5 it are closed, i.e. this core deal with data no longer.If all do not have in four nuclears to damage or degradation, four core microcontrollers then cut out that pre-set processing core, and its excess-three core is in single task co-operation state.When three cores are processed same task simultaneously, arbitrated by arbitration logic unit 6.This moment, system was in highly reliable crisis operational mode.As shown in table 1, arbitration logic unit 6 is arbitrated in the mode that the minority is subordinate to the majority according to majority ballot logic.The formula of its arbitration result is suc as formula (I):
In the formula (I), M represents arbitration result, and A, B, C are respectively the result of three cores.
M＝f(A，B，C)
| A | B | C | M |
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 1 |
The logical value of table 1 arbitration logic unit
Emergency response of the present invention is processed multi-core microcontroller arbitration framework both can satisfy the requirement at a high speed of system's high-performance, did not reduce again the reliability of system.
Embodiment 3: the flow process of resuming work
As shown in Figure 5, after handling crisis, multi-core microcontroller 1 reopens the core of cutting out.Multi-core microcontroller 1 writes data and register file in the volatility access unit of volatility common memory 4 from non-volatility memorizer 2 and non-volatile register file 3 difference reading out data and register files.All cores again return in the normal mode of operation among the embodiment 2 according to data and register file and work, and this moment, system returned to the optimum performance state.
Protection content of the present invention is not limited to above embodiment.Under the spirit and scope that do not deviate from inventive concept, those skilled in the art can to variation and advantage all be included in the present invention, and take appending claims as protection domain.
Claims (7)
1. an emergency response is processed multi-core microcontroller arbitration framework, it is characterized in that, comprising:
Multi-core microcontroller (1), it is the processing unit that forms based on the core of reduced instruction set computer or sophisticated vocabulary of even number for quantity, realizes processing the data in the microcontroller;
Each core separate connection in the non-volatility memorizer (2), itself and described multi-core microcontroller (1) is used for preserving or recovering the data of each core of described multi-core microcontroller (1);
Each core separate connection in the non-volatile register file (3), itself and described multi-core microcontroller (1) is used for preserving or recovering the data of described multi-core microcontroller;
Volatility common memory (4), it is connected with described multi-core microcontroller (1), is used for storing the public data of described multi-core microcontroller (1);
IO interface control module (5), it is connected with described multi-core microcontroller (1) and volatility common memory (4), is used for controlling the input and output of described multi-core microcontroller (1);
Arbitration logic unit (6), it is connected with described multi-core microcontroller (1), is used for the multi-core deal with data of described multi-core microcontroller (1) is arbitrated.
2. emergency response is processed multi-core microcontroller arbitration framework as claimed in claim 1, it is characterized in that, described non-volatility memorizer (2) comprises program storage and data-carrier store.
3. emergency response is processed multi-core microcontroller arbitration framework as claimed in claim 1; it is characterized in that; described non-volatility memorizer (2) and non-volatile register file (3) all are nonvolatile memory and non-volatile register files of position level; its each bit had both had the common storage unit of common storer or register file function, had again nonvolatile memory cell.
4. emergency response as claimed in claim 3 is processed multi-core microcontroller arbitration framework; it is characterized in that; data in institute's rheme level nonvolatile memory and the non-volatile register file in the common storage unit can deposit corresponding nonvolatile memory cell in, and the data in the nonvolatile memory cell also can return in the corresponding usually storage unit.
5. an emergency response is processed the mode of operation that the multi-core microcontroller is arbitrated framework, it is characterized in that, comprising:
Normal mode of operation, described multi-core microcontroller (1) are at full speed concurrent working state, and each core in the described multi-core microcontroller (1) is processed respectively different tasks;
Crisis mode of operation, when described multi-core microcontroller (1) when detecting crisis, described multi-core microcontroller (1) cuts out the odd number core according to performance or the predefined rule of processing core, other last odd number core of described multi-core microcontroller (1) is processed a task simultaneously, and by described arbitration logic unit (6) result is arbitrated;
Recovery mode of operation, after handling described crisis, described multi-core microcontroller (1) returns to described full speed concurrent working state.
6. emergency response is processed the mode of operation that the multi-core microcontroller is arbitrated framework as claimed in claim 5, it is characterized in that, described crisis mode of operation comprises:
Data are preserved step, when described multi-core microcontroller (1) when detecting crisis, described multi-core microcontroller (1) with in described non-volatility memorizer (2) and the non-volatile register file (3) usually the data of storage unit be saved in the corresponding nonvolatile memory cell;
Dynamic adjustment step, described multi-core microcontroller (1) detects described core, if the situation of damage or performance reduction appears in core wherein, closes described core by described arbitration logic unit (6); If the situation that damage or performance reduce all appears in core, described multi-core microcontroller (1) cuts out the odd number core by described arbitration logic unit (6) according to predefined rule;
The Iogic judge step; Remaining other odd number core of described multi-core microcontroller (1) same task of co-treatment under the coordination of described arbitration logic unit (6), and by described arbitration logic unit (6) result is arbitrated.
7. emergency response is processed the mode of operation that the multi-core microcontroller is arbitrated framework as claimed in claim 5, it is characterized in that, described recovery mode of operation comprises:
The data recovering step, the core of described multi-core microcontroller (1) is sent data recovery control signal the data in the nonvolatile memory cell in described non-volatility memorizer (2) and the non-volatile register file (3) is returned in the corresponding common storage unit, and memory data and the register data of each core are restored in the described multi-core microcontroller (1);
The work recovering step, described arbitration logic unit (6) is opened all cores in the described multi-core microcontroller (1), and core enters at full speed concurrent working state according to memory data and the register data of described recovery in the described multi-core microcontroller (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210572843XA CN103019863A (en) | 2012-12-25 | 2012-12-25 | Crisis emergency processing multi-core micro controller arbitration framework and working mode thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210572843XA CN103019863A (en) | 2012-12-25 | 2012-12-25 | Crisis emergency processing multi-core micro controller arbitration framework and working mode thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103019863A true CN103019863A (en) | 2013-04-03 |
Family
ID=47968493
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210572843XA Pending CN103019863A (en) | 2012-12-25 | 2012-12-25 | Crisis emergency processing multi-core micro controller arbitration framework and working mode thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103019863A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104331387A (en) * | 2013-08-28 | 2015-02-04 | 威盛电子股份有限公司 | Micro-processor and configuration method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1776570A (en) * | 2005-12-02 | 2006-05-24 | 威盛电子股份有限公司 | Power source management device and method for multi-processor system |
-
2012
- 2012-12-25 CN CN201210572843XA patent/CN103019863A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1776570A (en) * | 2005-12-02 | 2006-05-24 | 威盛电子股份有限公司 | Power source management device and method for multi-processor system |
Non-Patent Citations (2)
| Title |
|---|
| 张亚勇: "《一种面向事务处理的容错计算机仲裁技术研究与实现》", 《一种面向事务处理的容错计算机仲裁技术研究与实现》, 1 June 2010 (2010-06-01) * |
| 曾宪炼、马捷中、何世强: "基于容错技术的处理器设计", 《计算机测量与控制》, 30 December 2010 (2010-12-30) * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104331387A (en) * | 2013-08-28 | 2015-02-04 | 威盛电子股份有限公司 | Micro-processor and configuration method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103020002B (en) | Reconfigurable multiprocessor system | |
| CN102270189B (en) | Inter-core communication method based on FPGA (Field Programmable Gate Array) multi-core system | |
| CN103984560A (en) | Embedded reconfigurable system based on large-scale coarseness and processing method thereof | |
| CN103064503B (en) | SOC (system on a chip) and buffer thereof | |
| CN102308274A (en) | Method, network card and hard disk card of accessing power-off hard disk | |
| CN104317770A (en) | Data storage structure and data access method for multiple core processing system | |
| CN103440279A (en) | Data adapter and data adaptation method thereof in data acquisition process | |
| CN103235811A (en) | Data storage method and device | |
| CN102541750A (en) | Implementation method and device for data snapshot | |
| CN102609484A (en) | General method for managing log of system | |
| CN105426522A (en) | File system performance statistical method and system | |
| CN103176867A (en) | Fast file differential backup method | |
| CN107861878A (en) | The method, apparatus and equipment of java application performance issue positioning | |
| CN103197982B (en) | A kind of task local optimum check point interval searching method | |
| DE102012112363A1 (en) | Method for controlling power of chip system of multi-core system, involves comparing time interval between receipt of former and latter wake-up request signals and controlling output of wake-up request signal based on the comparison | |
| CN201804331U (en) | Date deduplication system based on co-processor | |
| CN202453889U (en) | Portable terminal of electronic manual for military vehicle maintenance | |
| CN102760106A (en) | PCI (peripheral component interconnect) academic data mining chip and operation method thereof | |
| CN204166522U (en) | A kind of high-speed high capacity FLASH veneer memory circuit plate | |
| CN103019863A (en) | Crisis emergency processing multi-core micro controller arbitration framework and working mode thereof | |
| CN103294169B (en) | A kind of redundancy protection systems of many core systems of optimised power consumption and method | |
| CN102681650B (en) | The storage system of a kind of Energy control power-economizing method and correspondence thereof | |
| CN202443462U (en) | Device for assisting upper computer to search free block in page mapping unit block | |
| US10452574B2 (en) | Read performance on a SATA storage device behind a host bus adapter | |
| CN103823766A (en) | High-efficiency storage method of flash memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130403 |