CN103003806A - Pcie port configuration method, device and equipment thereof - Google Patents
Pcie port configuration method, device and equipment thereof Download PDFInfo
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- CN103003806A CN103003806A CN201280001711XA CN201280001711A CN103003806A CN 103003806 A CN103003806 A CN 103003806A CN 201280001711X A CN201280001711X A CN 201280001711XA CN 201280001711 A CN201280001711 A CN 201280001711A CN 103003806 A CN103003806 A CN 103003806A
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- pcie port
- gating
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
Abstract
The invention is applicable to the field of bus interfaces and provides a PCIE port configuration method, a device and equipment thereof. The method comprises the following steps: receiving the CPU sends an identification signal; according to the received identification signal., obtaining the PCIe port information; a control multi-channel selector mux chip according to the PCIE port information is selected through the CPU; controlling the MUX chip according to the selection result to the PCIE ports. The embodiment of the invention, by obtaining the CPU type identification signal, recognizing the types of the CPU, thereby obtaining the CPU provides a PCIE interface information, control the MUX chip CPU gate and the gate of the CPU are connected, so as to realize the EPS device with different CPU PCIE port self-adapting and connection, ie, realizes flexible configuration of the PCIE port.
Description
Technical field
The invention belongs to the bus interface field, relate in particular to a kind of method, device and equipment of PCI allocation E port.
Background technology
High-speed peripheral assembly interconnect (Peripheral Component Interconnect Express, be called for short PCIE) be up-to-date bus and interface standard, CPU(Central Processing Unit, abbreviation CPU) passing through end points (endpoint the is called for short EP) equipment such as PCIE port and video card, internal memory connects.Different CPU may provide different PCIE port resources, namely may have different PCIE port numbers, and the passage (the English lane of being) of supporting different PCIE port types, for example CPU model A only supports the passage of PCIe 1.0 types, can support 8lane, only have a PCIe controller; And CPU model B can support the passage of PCIe 2.0 types, can support 4 lane, and two PCIe controllers are arranged.
The EP such as video card, internal memory equipment will adapt to the CPU of different PCIE port resources, namely need to adapt to PCIE port and the dissimilar passage of PCIE port of CPU varying number, and prior art can only be finished the configuration of PCIE port when hardware setting, can not flexible configuration PCIE port, adapt to different CPU with EP equipment such as good realization video card, internal memories.
Summary of the invention
The purpose of the embodiment of the invention is to provide a kind of method, device and equipment of PCI allocation E port, can not flexible configuration PCIE port to solve prior art, and with the problem of the CPU of the different PCIE ports of good adaptation.
On the one hand, provide a kind of method of PCI allocation E port, said method comprising the steps of:
Receive the id signal that central processor CPU sends, described id signal comprises to indicate the information of the model of described CPU;
According to the described id signal that receives, obtain the PCIE port information of described CPU, described PCIE port information comprises one or more in PCIE port number, PCIE port type, the PCIE port channel number;
Control MUX MUX chip carries out the CPU gating according to described PCIE port information;
Controlling described MUX chip carries out the PCIE port according to the result of described gating and connects.
On the other hand, provide a kind of device of PCI allocation E port, described device comprises:
Receiving element be used for to receive the id signal that central processor CPU sends, and described id signal comprises to indicate the information of the model of described CPU;
PCIE port information acquiring unit, be used for the id signal according to described receiving element reception, obtain the PCIE port information of described CPU, described PCIE port information comprises one or more in PCIE port number, PCIE port type, the PCIE port channel number;
Gating unit is used for control MUX MUX chip and carries out the CPU gating according to the PCIE port information that described PCIE port information acquiring unit obtains;
Linkage unit carries out the connection of PCIE port for controlling the result of described MUX chip according to described gating unit gating.
Again on the one hand, provide a kind of equipment of PCI allocation E port, described equipment comprises input media, processor, output unit, and described processor is carried out following steps:
Receive the id signal that central processor CPU sends, described identification information comprises to indicate the information of the model of described CPU;
According to the described id signal that receives, obtain the PCIE port information of described CPU, described PCIE port information comprises one or more in PCIE port number, PCIE port type, the PCIE port channel number;
Control MUX MUX chip carries out the CPU gating according to described PCIE port information;
Controlling described MUX chip carries out the PCIE port according to the result of described gating and connects.
The embodiment of the invention, identify the model of CPU by the type identification signal that obtains CPU, and then obtain the PCIE port information that CPU provides, control MUX (multiplexer, being called for short MUX) chip carries out the CPU gating and is connected with the PCIE port of the CPU of gating, thereby EP equipment can with the self-adaptation of the PCIE port of different CPU be connected, namely realized the flexible configuration of PCIE port.
Description of drawings
Fig. 1 is the process flow diagram of the PCI allocation E port method that provides of one embodiment of the invention;
Fig. 2 is the structural drawing of the PCI allocation E port device that provides of another embodiment of the present invention;
Fig. 3 is the structural drawing of the PCI allocation E port device that provides of yet another embodiment of the invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, is not intended to limit the present invention.
Be illustrated in figure 1 as the process flow diagram of the PCI allocation E port method that the embodiment of the invention provides, said method comprising the steps of:
In step S101, receive the id signal that CPU sends.
In embodiments of the present invention, EP equipment and CPU are connected on the backboard, can realize the data interaction of EP equipment and CPU by backboard.By backboard, EP equipment receives the id signal that CPU sends.Described id signal is used for indicating the model of CPU, can be the hardware signal of standard, also can be the software signal that uses the software such as I2C to realize.
In step S102, according to the id signal of described reception, obtain the PCIE port information that CPU provides.
In embodiments of the present invention, EP equipment is after the id signal that receives the CPU transmission, described id signal is analyzed identification, identify CPU model corresponding to this id signal, and then obtaining PCIE port information corresponding to described CPU model, described PCIE port information comprises: the passage lane quantity that the port number that provides, the type of each port (PCIE1.0, PCIE2.0 etc.), each port provide etc.
In step S103, control MUX MUX chip carries out the CPU gating according to the described PCIE port information that obtains.
In embodiments of the present invention, might connect a plurality of CPU on the backboard, EP equipment control this moment MUX chip is selected suitable CPU according to described PCIE port information, namely carries out the CPU gating, and described CPU gating is specially: the CPU corresponding to PCIE port of preferential selector channel quantity Matching; When all mating, the number of channels that provides selects to provide PCIE port number CPU how; When the number of channels that provides during all less than the number of channels of needs, the many CPU of preferential selector channel quantity; When the number of channels that provides during all greater than the number of channels of needs, the preferential few CPU of selector channel quantity.
In step S104, control MUX chip carries out the connection of PCIE port according to the result of described gating.
In embodiments of the present invention, EP equipment is (being after the CPU gating has the result) after choosing suitable CPU, control MUX chip carries out and being connected of the PCIE port of CPU, and concrete: if CPU only provides a PCIE port, then EP equipment control MUX chip is communicated with described PCIE port; If CPU provides a plurality of PCIE ports, then EP equipment control MUX chip is communicated with one of them PCIE port, and disconnection is communicated with other PCIE ports, and concrete connection method uses existing MUX chip technology, repeats no more herein.
Illustrate:
Supposing has two CPU:CPU A and CPU B simultaneously in a system, what be connected with backboard has an EP equipment C.CPU A can provide the PCIE port of 18 passage (X8), and CPU B can provide the PCIE port of 24 passages (X4).Concrete:
1, CPU A, CPU B send id signal to EP equipment simultaneously, can be the type signal herein, comprise the information of CPU model in the described type signal, can be hardware signals, also can be the software signals of realizing by software;
2, EP equipment receives the type signal that CPU sends, analyze described type signal acquisition CPU model, and then obtain the details of the PCIE port that CPU provides, that is: CPU A can provide the PCIE port of 18 passage (X8), and CPU B can provide the PCIE port of 24 passages (X4);
3, the suitable CPU of EP equipment control MUX MUX chip selection.
4, EP equipment control MUX chip is connected with the PCIE port of the CPU of selection, specifically: if a selects CPU A, CPU A can only provide 1 PCIE port, then is connected with all PCIE ports of CPU A, and concrete method of attachment is identical with the interconnection technique of existing MUX chip; If b selects CPU B, CPU B can provide 2 PCIE ports, is connected with the PCIE port of CPU B so, disconnects another one PCIE port, and concrete method of attachment is identical with the interconnection technique of existing MUX chip.
The embodiment of the invention, by obtaining the id signal of CPU, the model of identification CPU, and then obtain the PCIE port information that CPU provides, control MUX chip carries out the CPU gating and is connected with the PCIE port of the CPU of gating, thereby realized EP equipment can with the self-adaptation of the PCIE port of different CPU be connected, namely realized the flexible configuration of PCIE port.
Be illustrated in figure 2 as the structural drawing of the PCI allocation E port device that the embodiment of the invention provides, for convenience of explanation, the part relevant with the embodiment of the invention only be shown, comprising:
Receiving element 21 is used for receiving the id signal that central processor CPU sends.
In embodiments of the present invention, receiving element 21 all is connected on the backboard with CPU, can realize the data interaction of EP equipment and CPU by backboard.By backboard, EP equipment receives the id signal that CPU sends.The information that comprises the CPU model in the described id signal can be the hardware signal of standard, also can be the software signal that uses the software such as I2C to realize.
PCIE port information acquiring unit 22 is used for the id signal according to described receiving element 21 receptions, obtains the PCIE port information that CPU provides.
In embodiments of the present invention, PCIE port information acquiring unit 22 is after receiving element 21 receives the id signal of CPU transmission, described id signal is analyzed identification, identify CPU model corresponding to this id signal, and then obtaining PCIE port information corresponding to described CPU model, described PCIE port information comprises: the number of channels that the port number that can provide, the type of each port (PCIE1.0, PCIE2.0 etc.), each port provide etc.
Gating unit 23 is used for control MUX MUX chip and carries out the CPU gating according to the PCIE port information that described PCIE port information acquiring unit 22 obtains.
In embodiments of the present invention, a backboard might connect a plurality of CPU, this moment, gating unit 23 control MUX chips were selected suitable CPU according to described PCIE port information, namely carried out the CPU gating, and described CPU gating is specially: the CPU corresponding to port of preferential selector channel quantity Matching; When all mating, the number of channels that provides selects to provide PCIE port number CPU how; When the number of channels that provides during all less than the number of channels of needs, the many CPU of preferential selector channel quantity; When the number of channels that provides during all greater than the number of channels of needs, the preferential few CPU of selector channel quantity.
Linkage unit 24 carries out the connection of PCIE port for controlling the result of MUX chip according to described gating unit 23 gatings.
In embodiments of the present invention, linkage unit 24 control MUX chips carry out the connection of PCIE port according to the result of described gating unit 23 gatings, described linkage unit 24 specifically comprises: single port connexon unit 241, be used for when CPU only provides a PCIE port, control MUX chip is communicated with described PCIE port; A plurality of port connexons unit 242 is used for when CPU provides a plurality of PCIE port, and control MUX chip is communicated with one of them PCIE port, and disconnection is communicated with other PCIE ports, and concrete connection method uses existing MUX chip technology, repeats no more herein.
The embodiment of the invention, by obtaining the id signal of CPU, the model of identification CPU, and then obtain the PCIE port information that CPU provides, control MUX chip carries out the CPU gating and is connected with the PCIE port of the CPU of gating, thereby realized EP equipment can with the self-adaptation of the PCIE port of different CPU be connected, namely realized the flexible configuration of PCIE port.
Be illustrated in figure 3 as the structural drawing of the PCI allocation E port device that the embodiment of the invention provides, described equipment comprises input block 31, processor 32, output unit 33, and described processor 32 is carried out following steps:
Receive the id signal that central processor CPU sends.
In embodiments of the present invention, EP equipment and CPU are connected on the backboard, can realize the data interaction of EP equipment and CPU by backboard.By backboard, EP equipment receives the id signal that CPU sends.Comprising the information of indication CPU model in the described id signal, can be the hardware signal of standard, also can be the software signal that uses the software such as I2C to realize.
According to the id signal of described reception, obtain the PCIE port information that CPU provides.
In embodiments of the present invention, PCI allocation E port device is after the id signal that receives the CPU transmission, described id signal is analyzed identification, identify CPU model corresponding to this id signal, and then obtaining PCIE port information corresponding to described CPU model, described PCIE port information comprises: the number of channels that the port number that can provide, the type of each port (PCIE1.0, PCIE2.0 etc.), each port provide etc.
Control MUX MUX chip carries out the CPU gating according to the described PCIE port information that obtains.
In embodiments of the present invention, might connect a plurality of CPU on the backboard, EP equipment control this moment MUX chip is selected suitable CPU according to described PCIE port information, namely carries out the CPU gating, and described CPU gating is specially: the CPU corresponding to port of preferential selector channel quantity Matching; The many CPU of port number when all mating, the number of channels that provides are provided; When the number of channels that provides during all less than the number of channels of needs, the many CPU of preferential selector channel quantity; When the number of channels that provides during all greater than the number of channels of needs, the preferential few CPU of selector channel quantity.
Control MUX chip carries out the connection of PCIE port according to the result of described gating.
In embodiments of the present invention, EP equipment is (being after gating has the result) after choosing suitable CPU, control MUX chip carries out and being connected of PCIE port, and concrete: if CPU only provides a PCIE port, then EP equipment control MUX chip is communicated with described PCIE port; If CPU provides a plurality of PCIE ports, then EP equipment control MUX chip is communicated with one of them PCIE port, and disconnection is communicated with other PCIE ports, and concrete connection method uses existing MUX chip technology, repeats no more herein.
The embodiment of the invention, by obtaining the id signal of CPU, the model of identification CPU, and then obtain the PCIE port information that CPU provides, control MUX chip carries out the CPU gating and is connected with the PCIE port of the CPU of gating, thereby realized EP equipment can with the self-adaptation of the PCIE port of different CPU be connected, namely realized the flexible configuration of PCIE port.
The above only is preferred embodiment of the present invention, not in order to limiting the present invention, all any modifications of doing within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
It should be noted that among above-mentioned subscriber equipment and the base station embodiment that included unit is just divided according to function logic, but is not limited to above-mentioned division, as long as can realize corresponding function; In addition, the concrete title of each functional unit also just for the ease of mutual differentiation, is not limited to protection scope of the present invention.
In addition, one of ordinary skill in the art will appreciate that all or part of step that realizes in above-mentioned each embodiment of the method is to come the relevant hardware of instruction to finish by program, corresponding program can be stored in a kind of computer-readable recording medium, the above-mentioned storage medium of mentioning can be ROM (read-only memory), disk or CD etc.
The above; only be the better embodiment of the present invention; but protection scope of the present invention is not limited to this; anyly be familiar with those skilled in the art in the technical scope that the embodiment of the invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claim.
Claims (12)
1. the method for a configuration high-speed peripheral component interconnect PCIE port is characterized in that, said method comprising the steps of:
Receive the id signal that central processor CPU sends, described id signal comprises to indicate the information of the model of described CPU;
According to the described id signal that receives, obtain the PCIE port information of described CPU, described PCIE port information comprises one or more in PCIE port number, PCIE port type, the PCIE port channel number;
Control MUX MUX chip carries out the CPU gating according to described PCIE port information;
Controlling described MUX chip carries out the PCIE port according to the result of described gating and connects.
2. the method for claim 1 is characterized in that, described described id signal according to receiving obtains the PCIE port information of described CPU, is specially:
Described id signal is analyzed, obtained the model of described CPU, obtain the PCIE port information of described CPU according to the model of the described CPU that obtains.
3. the method for claim 1 is characterized in that, described control MUX MUX chip carries out the CPU gating according to described PCIE port information, is specially:
The CPU of the number of channels coupling that preferential selection provides;
The CPU that provides the PCIE port number many when all mating, the number of channels that provides as CPU is provided;
The number of channels that provides as CPU is during all less than the number of channels of needs, the many CPU of preferential gating number of channels;
The number of channels that provides as CPU is during all greater than the number of channels of needs, the preferential few CPU of gating number of channels.
4. the method for claim 1 is characterized in that, described control MUX chip carries out the step that the PCIE port connects according to the result of described gating and is specially:
If the CPU of described gating only provides a PCIE port, then control the described PCIE port that described MUX chip is communicated with the CPU of described gating; Perhaps,
If the CPU of described gating provides a plurality of PCIE ports, then control a PCIE port in the described a plurality of PCIE end of CPU that described MUX chip is communicated with described gating, disconnect and being communicated with of other PCIE ports.
5. the device of a configuration high-speed peripheral component interconnect PCIE port is characterized in that described device comprises:
Receiving element be used for to receive the id signal that central processor CPU sends, and described id signal comprises to indicate the information of the model of described CPU;
PCIE port information acquiring unit, be used for the id signal according to described receiving element reception, obtain the PCIE port information of described CPU, described PCIE port information comprises one or more in PCIE port number, PCIE port type, the PCIE port channel number;
Gating unit is used for control MUX MUX chip and carries out the CPU gating according to the PCIE port information that described PCIE port information acquiring unit obtains;
Linkage unit carries out the connection of PCIE port for controlling the result of described MUX chip according to described gating unit gating.
6. device as claimed in claim 5 is characterized in that, by described id signal is analyzed, obtains the model of described CPU, obtains the PCIE port information of described CPU according to the model of the described CPU that obtains.
7. device as claimed in claim 5 is characterized in that, described gating is specially:
The CPU of the number of channels coupling that preferential selection provides;
The CPU that provides the PCIE port number many when all mating, the number of channels that provides as CPU is provided;
The number of channels that provides as CPU is during all less than the number of channels of needs, the many CPU of preferential gating number of channels;
The number of channels that provides as CPU is during all greater than the number of channels of needs, the preferential few CPU of gating number of channels.
8. device as claimed in claim 5 is characterized in that, described linkage unit specifically comprises:
Single port connexon unit is used for controlling the described PCIE port that described MUX chip is communicated with the CPU of described gating when the CPU of described gating only provides a PCIE port;
A plurality of port connexons unit is used for when the CPU of described gating provides a plurality of PCIE port, controls a PCIE port in described a plurality of PCIE ends of CPU that described MUX chip is communicated with described gating, and disconnection is communicated with other PCIE ports.
9. the equipment of a configuration high-speed peripheral component interconnect PCIE port is characterized in that described equipment comprises input media, processor, output unit, and described processor is carried out following steps:
Receive the id signal that central processor CPU sends, described identification information comprises to indicate the information of the model of described CPU;
According to the described id signal that receives, obtain the PCIE port information of described CPU, described PCIE port information comprises one or more in PCIE port number, PCIE port type, the PCIE port channel number;
Control MUX MUX chip carries out the CPU gating according to described PCIE port information;
Controlling described MUX chip carries out the PCIE port according to the result of described gating and connects.
10. equipment as claimed in claim 9 is characterized in that, described described id signal according to receiving obtains the PCIE port information of described CPU, is specially:
Described id signal is analyzed, obtained the model of described CPU, obtain the PCIE port information of described CPU according to the model of the described CPU that obtains.
11. equipment as claimed in claim 9 is characterized in that, described control multichannel selects the MUX chip to carry out the step of CPU gating according to the described PCIE port information that obtains, and is specially:
The CPU of the number of channels coupling that preferential selection provides;
The CPU that provides the PCIE port number many when all mating, the number of channels that provides as CPU is provided;
The number of channels that provides as CPU is during all less than the number of channels of needs, the many CPU of preferential gating number of channels;
The number of channels that provides as CPU is during all greater than the number of channels of needs, the preferential few CPU of gating number of channels.
12. equipment as claimed in claim 9 is characterized in that, described control MUX chip carries out the step that the PCIE port connects according to the result of described gating and is specially:
If the CPU of described gating only provides a PCIE port, then control the described PCIE port that described MUX chip is communicated with the CPU of described gating; Perhaps,
If the CPU of described gating provides a plurality of PCIE ports, then control a PCIE port in the described a plurality of PCIE end of CPU that described MUX chip is communicated with described gating, disconnect and being communicated with of other PCIE ports.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2012/081144 WO2014036725A1 (en) | 2012-09-07 | 2012-09-07 | Method, device and equipment for pcie port configuration |
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| Publication Number | Publication Date |
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| CN103003806A true CN103003806A (en) | 2013-03-27 |
| CN103003806B CN103003806B (en) | 2015-12-02 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201280001711.XA Active CN103003806B (en) | 2012-09-07 | 2012-09-07 | A kind of method of PCI allocation E port, device and equipment |
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| Country | Link |
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| CN (1) | CN103003806B (en) |
| WO (1) | WO2014036725A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104714910A (en) * | 2013-12-17 | 2015-06-17 | 研祥智能科技股份有限公司 | Method and system for configuring PCIE bus interface in self-adaption mode |
| WO2018019009A1 (en) * | 2016-07-25 | 2018-02-01 | 中兴通讯股份有限公司 | Data processing method and system, peripheral component interconnect express device and host |
| CN109032981A (en) * | 2018-07-11 | 2018-12-18 | 郑州云海信息技术有限公司 | A kind of method and system counting PCIE information |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1694079A (en) * | 2004-04-28 | 2005-11-09 | 微软公司 | Configurable PCI express switch |
| CN101609442A (en) * | 2009-06-17 | 2009-12-23 | 成都市华为赛门铁克科技有限公司 | A kind of method of interface adaptive and device thereof, system |
| CN101647713A (en) * | 2008-08-13 | 2010-02-17 | 深圳迈瑞生物医疗电子股份有限公司 | Ultrasonic video acquisition system and device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8335884B2 (en) * | 2009-07-10 | 2012-12-18 | Brocade Communications Systems, Inc. | Multi-processor architecture implementing a serial switch and method of operating same |
-
2012
- 2012-09-07 WO PCT/CN2012/081144 patent/WO2014036725A1/en active Application Filing
- 2012-09-07 CN CN201280001711.XA patent/CN103003806B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1694079A (en) * | 2004-04-28 | 2005-11-09 | 微软公司 | Configurable PCI express switch |
| CN101647713A (en) * | 2008-08-13 | 2010-02-17 | 深圳迈瑞生物医疗电子股份有限公司 | Ultrasonic video acquisition system and device |
| CN101609442A (en) * | 2009-06-17 | 2009-12-23 | 成都市华为赛门铁克科技有限公司 | A kind of method of interface adaptive and device thereof, system |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104714910A (en) * | 2013-12-17 | 2015-06-17 | 研祥智能科技股份有限公司 | Method and system for configuring PCIE bus interface in self-adaption mode |
| CN104714910B (en) * | 2013-12-17 | 2018-11-30 | 研祥智能科技股份有限公司 | The method and system of adaptive configuration PCIE bus interface |
| WO2018019009A1 (en) * | 2016-07-25 | 2018-02-01 | 中兴通讯股份有限公司 | Data processing method and system, peripheral component interconnect express device and host |
| CN109032981A (en) * | 2018-07-11 | 2018-12-18 | 郑州云海信息技术有限公司 | A kind of method and system counting PCIE information |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103003806B (en) | 2015-12-02 |
| WO2014036725A1 (en) | 2014-03-13 |
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Effective date of registration: 20211227 Address after: 450046 Floor 9, building 1, Zhengshang Boya Plaza, Longzihu wisdom Island, Zhengdong New Area, Zhengzhou City, Henan Province Patentee after: Super fusion Digital Technology Co.,Ltd. Address before: 518129 Bantian HUAWEI headquarters office building, Longgang District, Guangdong, Shenzhen Patentee before: HUAWEI TECHNOLOGIES Co.,Ltd. |
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