CN103000674B - Transistor and manufacturing method thereof - Google Patents
Transistor and manufacturing method thereof Download PDFInfo
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- CN103000674B CN103000674B CN201210544375.5A CN201210544375A CN103000674B CN 103000674 B CN103000674 B CN 103000674B CN 201210544375 A CN201210544375 A CN 201210544375A CN 103000674 B CN103000674 B CN 103000674B
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Abstract
A transistor is in an inverted heterojunction structure, wherein an emitting electrode layer is formed before forming of a base layer and a collector layer. Good thermal budgets are provided for the critical base region morphology and the doping distribution control, so that a high cut-off frequency (fT) can be obtained; and the contact area of a collector region and a base region is minimized, so that the stray capacitance can be greatly reduced, and the highest oscillation frequency (fmax) can be increased. Thus, frequency characteristics of the transistor can be greatly improved. An atomic layer epitaxy (ALE) process can be used for forming the emitting electrode layer on an epitaxial monocrystalline metal silicide which is formed in advance, the base layer is formed on the emitting electrode layer, and the collector layer is formed on the base layer, so that the inverted heterojunction structure can be obtained.
Description
Technical field
The present invention relates to electronics technologies, more particularly to a kind of transistor and its manufacture method.
Background technology
In 0.5 to 6 Terahertz (THz, i.e., 1012Hertz) frequency system, imaging and spectroscopic system are in safety, health, remote sensing
There is important application with the field such as basic science.THz wave has very strong decay intensity in water, but to biological tissue
With larger penetration depth, without to biological tissue damage.Therefore, they are particularly suitable for being related to through opaque
Object carry out the safety applications of low-risk imaging, such as through the imaging of clothes, tooth, paper, plastics and ceramic material.Too
Hertz wave is also ideal in hygiene applications, such as the early diagnosiss of skin carcinoma.Therefore, recently to many be related to peace
Entirely, social foundation's application of medicine, bioanalysiss, the remote sensing for environmental monitoring and natural disaster reduction is widely ground
Study carefully.By its altofrequency, THz wave is applied equally to limit broadband connections.
However, up to the present, application of the Terahertz frequency range region in daily is considerably less.Which results in " terahertz
The appearance of hereby space " (THz gap) this statement, it inaccurately describes to lack enough technologies, low effectively to make up
Frequency range between microwave frequency in 1THz and the light frequency higher than 6THz, particularly, lacks in this specific frequency range
The weary actual source with available power level.Now, semiconductor electronic and laser optical element contract from each contrary direction
Little this Terahertz space.Advanced semiconductor technology, including silicon-complementary metal oxide semiconductors (CMOS) (Silicon-CMOS),
SiGe heterojunction bipolar transistor (SiGe HBT) and compound semiconductor HEMT device (HEMT), pole
The earth promotes the development of millimeter-wave technology.However, by most powerful and estimated with cost-benefit SiGe HBT technologies
Accessible frequency is in currently about 0.5THz.In optical field, by the modern solid-state of the electron state transformation from good definition
Laser instrument, when 6THz barriers are broken, encounters serious challenge, because the heat wave at room temperature such as light energy of such frequency
Dynamic energy, i.e. kT=26 millis electron-volt (meV).
At present, can be by passive device, such as frequency multiplier, into THz frequency ranges.However, such device is universal
With significant power attenuation, power and system bulk ratio will be unrealistic when this causes to use these devices in actual applications
It is little.Therefore, little and efficient active THz devices are unique solutions.Vacuum electron device, including klystron, by
It is considered as a kind of mode for making THz spaces up.This device perhaps may apply to military affairs and aerospace field, but can be with
, it is envisioned that the reliability of its large scale, significant energy expenditure and bad luck, will hinder them to the wide civilian neck such as safety and sanitation
Domain is permeated.Therefore, it is uniquely to be used for our daily life based on the solid electronic device of sophisticated semiconductor, especially with
Battery powered portable Terahertz system.
The transistor with 10 nanometers of (nm) channel lengths is needed based on the solution of CMOS in 1THz operations.So
And, in this grid length, due to quantum tunneling effect, transistor can export low-down power.By superior mutual conductance and
Noise characteristic, SiGe HBT technologies are generally considered to be provided to emerging altofrequency market most powerful and with cost benefit
Solution.At present, the basic technology of SiGe HBT is the SiGe by chemical vapor deposition (CVD).It is state-of-the-art at present
SiGe HBT have at room temperature the cut-off frequency of 0.4THz.The European FP7 plans of ongoing entitled " DOTFIVE ", bag
Include main European Semiconductor enterprises, it is intended to the SiGe HBT technologies of 0.5THz were released in 2013.Meriting attention is,
In the works, the circuit design for the complete frequency multiplier chain of 0.325THz represents current highest development to DOTFIVE
Level, but this not still very lossy method, also also fail to enter THz spaces.
The content of the invention
In one embodiment, SiGe HBT can pass through atomic layer epitaxy (ALE) method on the metal silicide of extension
Form the hetero-junctions of ultra-thin (for example, less than or equal to 10nm) quasiconductor.Stress engineering can apply to HBT subregions or
On Zone Full, for improving horizontal hole and longitudinal electronic conduction.SiGe HBT have inversion heterojunction structure, and by subtracting
Few ghost effect simultaneously provides more preferable heat treatment budget for crucial base morphology control, so as to obtain maximized frequency
Energy.Can be by using ALE technologies, launch site being epitaxially formed on the metal silicide being epitaxially formed in advance, on launch site
Base is epitaxially formed, collecting zone is then epitaxially formed on base to prepare inversion heterojunction structure.Using new contact
Mode, to provide extremely low contact resistance in some or all of HBT exits.
SiGe HBT can adopt the CMOS technology for being suitable for industrialized production to prepare.
In one embodiment, a HBT includes growth ultra thin single crystalline epitaxial metal silicide on a semiconductor substrate
Layer, its thickness is 10nm or thinner, and on the metal silicide layer monocrystalline emitter is formed, and base stage is formed on emitter stage,
Base stage has about 10nm or less width；And in base stage formed monocrystal silicon colelctor electrode.The HBT have colelctor electrode closer to
The inverted structure on HBT surfaces.
In a further embodiment, emitter stage is carbon doping.
In a further embodiment, single crystal epitaxial metal silicide is Ultra Thin Epitaxial NiSi on Si (100) substrate2
Film.
In a further embodiment, emitter and collector has respectively about 10nm or thinner thickness.
In a further embodiment, at least one of emitter stage, base stage and colelctor electrode pass through at least one ALE processes
Formed.
In a further embodiment, base stage includes SiGe (SiGe).
HBT further includes there is Metal-silicides Contact, and metallic silicon respectively on emitter stage, base stage and colelctor electrode
Compound resistivity of the contact with low-down about 45 milliohm centimetre.
In a further embodiment, colelctor electrode carries out in the transmit direction stress process to improve electron mobility.
In a further embodiment, the extremely lightly doped silicon of current collection and there is metal silicide layer on surface.
In a further embodiment, base stage carries out stress process, to strengthen in the horizontal hole of base stage and longitudinal electronics
Conduction, and further deformation process is carried out in the other direction.
In one embodiment, a kind of manufacture method of HBT is comprised the steps of：Epitaxial growth list on a semiconductor substrate
Brilliant metal silicide layer, and the metal silicide layer has 10nm or thinner thickness；The extension on the metal silicide layer
Growing single-crystal silicon emitter stage；In emitter stage Epitaxial growth SiGe base stages；In SiGe base stage Epitaxial growth monocrystal silicon colelctor electrodes.
In a further embodiment, metal silicide layer be by solid-state reaction (SSR) growth process on Si (100)
NiSi2, the method includes that one layer of sputtering sedimentation is approximately equal to the Ni films and rapid thermal treatment of 2 nanometer thickness.
In a further embodiment, emitter stage uses ALE growth process, and carbon doping in situ is carried out during ALE.
In a further embodiment, using the photon sent from lasing light emitter during ALE, help is released from substrate surface
Put hydrogen atom.
In a further embodiment, silicon emitter layer has carried out strained handling, and SiGe bases with SiGe base layers
Pole layer has carried out in a plurality of directions strained handling.
In a further embodiment, due to inverted structure, mechanical stress is applied to collector layer from HBT top surfaces
On.
Description of the drawings
Fig. 1 is the cross-sectional view of the SiGe HBT devices according to one embodiment；
Fig. 2 is the flow chart of the SiGe HBT device preparation methoies according to one embodiment；
Fig. 3 a to 3h are illustrated according to the corresponding cross section of each step of SiGe HBT device preparation methoies of one embodiment
Figure；
Fig. 4 A are that thick extensions NiSi of 6nm are grown on Si (100) according to the use SSR of one embodiment2Transmission-type
Ultramicroscope (TEM) image.
Fig. 4 B are to use molecular beam epitaxy in NiSi2The RHEED images of upper growth 10nm thick epitaxy Si.
Fig. 5 is the operating frequency (f of the SiGe HBT for big injection optimization according to one embodimentT) and colelctor electrode
The simulation result schematic diagram of relation between current density, J c.
Specific embodiment
According to one embodiment of present invention, there is provided one kind is new, can penetrate into Terahertz space from microwave direction
" inversion " SiGe heterojunction bipolar transistor (SiGe HBT) device of (THz gap) band operation.By using with material,
The Technology revolutionary thin film technique innovation relevant with device architecture, such as, given birth on Si using solid-state reaction (SSR) extension
Long NiSi2And in NiSi2Upper employing atomic layer epitaxy growth Si etc., is prepared SiGe HBT, and the HBT devices can work
In the frequency range of Terahertz space.
Fig. 1 is the cross-sectional view of inversion HBT 100 according to an embodiment of the invention.As shown in figure 1, the inversion
HBT 100 comprising the epitaxial layer 110 on quasiconductor (e.g., the silicon) substrate 101, the emitter stage 120 on epitaxial layer 110,
Base stage 130 on emitter stage 120 and the colelctor electrode in base layer 140.Therefore, the emitter stage being inverted in HBT 100
120th, the order of base stage 130 and colelctor electrode 140 is contrary with the order in traditional bipolar transistor.The one of this layout
Individual benefit is to be grounded in colelctor electrode-emitter stage (CE) structure with emitter stage exit in traditional bipolar transistor and differ
Sample, low potential region of the emitter stage in the present embodiment HBT 100 in substrate 101.On the other hand, current collection is very close to HBT
100 top or surface 102, therefore, colelctor electrode electric circuit metal layer (not shown) that is closer or direct and being connected with HBT
Contact, and be easy to from top device access.As a result, so that impact (particularly, the collector-base electricity of ghost effect
Hold Cbc) substantially reduce, so as to realize the gain in performance.
In one embodiment, epitaxial layer 110 includes the single-crystal silicide formed in heteroepitaxial growth process, transmitting
Pole includes epitaxially grown silicon.In improved embodiment, emitter stage include carbon doping silicon (Si (C)), the carbon doping silicon have than
The bigger band gap of silicon (Si), it is possible to achieve more enhanced carrier injection.It is good heterogeneous due to being formed on
The base stage of epitaxial silicon (Si) or SiGe (SiGe), extension silicon emitter can bring good high frequency performance.In an enforcement
In example, base stage is prepared by atomic layer epitaxy (ALE) method, and its width w can be very thin, so that base-transit time will not
Significantly limit the performance of HBT.
Such " being inverted ambipolar " structure can allow for carrying out colelctor electrode simple doping optimization, so as to be formed
Special heterojunction structure, enables device to work under higher electric current density, to reach higher frequency limitation.Additionally, should
Inverted structure can greatly simplify the applying to the critically important deformation that works in Terahertz frequency range.
In one embodiment, epitaxial layer 110 include epitaxial metal silicide, the metal silicide have about 50 ohm/
The sheet resistance of square, to minimize carrier transit time and series resistance, and improves radiating management.
In one embodiment, base layer includes Si or SiGe.Can obtain higher by forming the base stage with SiGe
Operating frequency.Although silicon substrate pole is also feasible, discussed below will concentrate mainly on the HBT with SiGe base layers
100, and below with the replacement HBT100 of SiGe HBT 100.In one embodiment, base layer strengthens base using stress engineering
The conduction of horizontal hole and longitudinal electronics in bottom.In one embodiment, in addition to using the SiGe layer for carrying out stress process,
Apply pressure in another direction, more greatly to improve the performance of device.Ripe stress technique is had developed into, than
As heterogenous junction epitaxy is processed and silicon nitride tensile and compression stress, state-of-the-art CMOS (Complementary Metal Oxide Semiconductor) half has been widely used in
In conductor (CMOS) technology, in being equally useful for the stress application of present invention discussion.
In one embodiment, the base stage 130 of SiGe HBT 100 includes extrinsic base region 130a and intrinsic base region
130b.In one embodiment, the thickness of intrinsic base region is about 10nm or thinner.In order to avoid so thin intrinsic base stage
Area and caused unnecessary high resistance, emitter stripes band 120 is done very narrow (such as, about 20 nanometers or narrower), HBT
100 can have multiple emitter stripes bands to optimize performance.In one embodiment, emitter stage uses beamwriter lithography or leaching
Profit formula photoetching technique is patterned, to obtain high-resolution.
In one embodiment, colelctor electrode includes silicon, and has carried out stress process.In one embodiment, current collection is extremely
Lightly doped silicon and there is metal silicide layer in upper surface, and carried out stress process in the transmit direction, moved with improving electronics
Shifting rate.The collector area domain structure on inverted close surface 102 conveniently carries out the applying and control of stress.In one embodiment
In, the size in the silicide contacts area 150 at the top of colelctor electrode can be big as colelctor electrode, to make contact resistance minimum
Change.
In one embodiment, SiGe HBT 100 are also included in the low resistivity contact area 150 of its exit.For example,
Can be that there is extremely low contact resistance (for example, less than 10 in emitter stage and base stage-8Ωcm2), and there is extremely low Xiao in colelctor electrode
Nisiloy (NiSi) contact area of special base potential barrier (SBH) (for example, about 0.1eV).
In one embodiment, the height using advanced ALE and epitaxial suicides technology manufacture operating frequency more than 1THz
Performance HBT.Under so high frequency, it should be specifically noted that all parasitic antennas including internal and outside are minimized,
Talk about if not so, adverse effect will be brought to active device.
The ALE process of one atomic layer of deposition every time, it is ensured that the atom during low temperature depositing in a layer is finally deposited
In correct lattice position.Therefore, compared with conventional chemical vapor deposition (CVD) for needing very temperature high deposition, ALE is not required to
Want extra high-temperature step.Compared with it can also reach the molecular beam epitaxy (MBE) of atomic-level deposition control, ALE is conducive to obtaining
The narrow distribution pattern realized is highly desirable in actual Terahertz element.In one embodiment, ultrahigh vacuum (UHV)
ALE is used for Growth of Carbon Doped silicon (representing with Si (C)) emitter stage, germanium silicon substrate pole and silicon colelctor electrode.
Fig. 2 is the flow chart of SiGe HBT preparation process 200 according to an embodiment of the invention.Fig. 3 a to 3h are
The corresponding cross-sectional view of each step in SiGe HBT preparation process 200.As illustrated in figures 2 and 3, there is provided (the step of Semiconductor substrate 301
It is rapid 201).Semiconductor substrate 101 can be silicon substrate or silicon-on-insulator (SOI) substrate.
As shown in Fig. 2 and 3b, by heterogenous junction epitaxy technique growing single-crystal metals silicide layer 110 on a semiconductor substrate
(step 210).The conventionally used thick highly doped silicon layer as electron collector of the replacement of epitaxial suicides layer 110, has
It is suitable for the sheet resistance of 50 below Ω of Terahertz frequency work.Due to silicide layer can very thin (≤10nm), therefore
The parasitic edge electric capacity being connected with any side wall of sub- emitter stage can be greatly reduced.
In one embodiment, extension disilicide layer 110 is grown on silicon substrate 100 using solid-state reaction (SSR) technique
Ultra-thin NiSi2Thin film.In one embodiment, SSR processes deposit first the Ni films of one layer of about 2 nanometer thickness in sputtering mode,
Then short heat-treatment is carried out at a temperature of about 700 DEG C.As shown in Figure 4 A, the extension of 6 nanometer thickness for growing on Si (100)
NiSi2The thickness of film is uniform, and has sharp interface and smooth surface in atomic layer rank.Additionally, the film has
Low-down resistivity, for example, 45 μ Ω-cm, or the about sheet resistance of the Ω of unit area 75.
As shown in Fig. 2 and 3c, carbon doping silicon (Si (C)) emitter stage 120 and SiGe base stages 130 are continuous using ALE techniques
Ground is formed to prolong outside and (correspond to step 220 and 230 respectively) on silicide layer 110.In ALE techniques, it is possible to achieve monoatomic layer
The thickness and Composition Control of precision, different chemical substances and material also can be processed promptly.Emitter stage 120 carries out original position
Doping, to realize the other precipitous Impurity Distribution of atomic level.ALE techniques with monoatomic layer control ability are often relied on
The circular treatment of two presomas, to form AxByType binary compound, such as III-V or II-VI group quasiconductor.ALE techniques 230
Key feature be from restricted, the characteristic by ultrahigh vacuum (UHV) environment, less than 400 DEG C at a temperature of chemistry suction
Attached process is realized.In this way it is possible to grow at most one monolayer in composition A or B in each cycle, and with growth
The length in cycle is unrelated.For the growth of the silicon fiml of single element, circular treatment can be by using silicon hexachloride (Si2Cl6) and
Silicoethane (Si2H6) realize.However, this process is not real from limiting, because the Si more than 400 DEG C2H6Hold very much
Easily decompose.In this regard, the ALE expections of germanium-silicon alloy can be more difficult in base stage 130, because such as germanium methane (GeH4)
Or germanium (the Ge of hexahydro two2H6) germanium presoma be easy to decompose at lower temperatures.In order to realize that atomic level is other from restriction
Growth, needs to carry out growth technique at low temperatures.One challenge of low-temperature epitaxy is carried out from the silicon face for growing
The desorption of hydrogen atom, is that follow-up silicon adsorbs and deposition is allowed some leeway.Can help discharge hydrogen original using photon or plasma
Son, so as to realize silicon atom layer extension.In order to avoid plasma body induction damage, Si and SiGe can be carried out using photonic methodologies
Extension, to realize monoatomic layer control.Conventional ultrahigh vacuum ALE with exterior laser source or ALD system can be used for reality
The ALE techniques of the existing present invention.
As shown in Fig. 2 process 200 is further included：To Si emitter stages 120 (step 225) and (step of SiGe base stages 130
235) carry out appropriate stress to process, to shorten the transition time, realize SiGe of the operating frequency (fT) more than 1.1 Terahertzs
HBT.By the combination for introducing single shaft and biaxial stress in heterojunction structure, carrier mobility and by carrier mobility
The operating frequency of the device of impact can be increased with significant.This can pass through inherent heterogenous junction epitaxy growth and external strain
Layer deposits to realize.Similarly, it is well known that hetero-junctions is conducive to transporting for the injection of carrier and carrier.As
Successful Application in CMOS technology is the same, carries out stress using strained layer and processes and can provide bigger for carrier mobility enhancing
Degree of freedom.
As shown in Fig. 2 and 3d, silicon layer 140 forms (step 240) by heterogenous junction epitaxy technique.In order to keep different layers it
Between precipitous dopant profiles, and to form a NPN HBT as a example by, the emitter stage 120 in ALE technical processs, base stage 130 and collection
Electrode 140 carries out respectively the doping in situ of N-type, p-type and N-type.For the NPN HBT according to one embodiment, in the normal work phase
Between, the bias (V between base stage and emitter stageBE) it is positive, the bias (V between base stage and colelctor electrodeBC) it is negative.
As shown in Fig. 2,3e to 3f, emitter stage 120, base stage 130 and colelctor electrode 140 are patterned in step 145
And etching, to form emitter stage 120, base stage 130 and colelctor electrode 140.As shown in figure 3g, insulation dielectric layer 103, Ran Houping is deposited
Smoothization, then forms contact hole in insulation dielectric layer 103.Contact hole 160 is used for subsequently in emitter stage, base stage and colelctor electrode
Form contact area.
As shown in Fig. 2 and 3h, on emitter stage, base stage and colelctor electrode contact area (step 250) is formed.In one embodiment
In, traditional autoregistration CMOS technology can be adopted to form nickle silicide (NiSi) contact area, without the need for extra mask.Transmitting
There is ultralow contact resistance (for example, less than 10 between pole and base stage-8Ωcm2), the metal that employing is developed in CMOS researchs-
Semiconductor contact impurity separates (DS：Dopant segregation) technology, the metal-semiconductor contact of colelctor electrode can reach
Low-down schottky barrier height (SBH) (for example, about 0.1eV).This will further improve the frequency of SiGe HBT100
Energy.Up to the present, make electrical contact with area in traditional HBT researchs and be little affected by concern.Structure constraint in view of HBT and
Its related process, common heavy doping technology and the appropriate metal with low contact resistance select to be not easily accomplished, therefore, for
THz devices, contact area becomes a major issue.In order to reduce the contact resistance of all three exit, can be using such as
The detached technology of impurity is changing the schottky barrier height between metal silicide and quasiconductor.
Therefore, SiGe HBT are formed by atomic layer epitaxy (ALE), specifically, are formed on extension metal silicide
Ultra-thin (for example, less than 10 nanometers) heterojunction semiconductor.Apply stress technique on some or all of regions of HBT so that laterally
Hole and longitudinal electronic conduction ability strengthen simultaneously.SiGeHBT have be inverted heterojunction structure, and by reduce ghost effect and
More preferable heat budget is provided for crucial base pattern and distributed controll, maximized frequency performance is obtained.Using new contact
Strategy, to obtain extremely low contact resistance in some or all of HBT exits.
Accordingly, it is capable to Terahertz frequency range work good inversions SiGe HBT can using be based on quasiconductor technique come
Make, Si, SiGe and carbon doping silicon Si (C) structure are formed on single-crystal silicide film using ALE techniques.Or, outside molecular beam
Prolong the growth that (MBE) can also be used for quasiconductor.Extension NiSi2Surface that film is obtained and interface performance to promote various Si or
Extension on SiGe film is critically important.For example, such as refletcion high-energy electron diffraction (the Reflection High-Energy in Fig. 4 B
Electron Diffraction, referred to as " RHEED ") image shows that the epitaxy Si of 10 nanometer thickness can be at 380 DEG C in extension
NiSi2Growth on film is obtained.Although not making meticulous surface treatment, the quality of growing surface has compared rationally.
Fig. 5 is based on the device architecture simulation result for big injection working condition optimization of one embodiment of the invention：
Operating frequency (the f of SiGe HBTT) curve chart of relation and Collector Current Density Jc between.
The performance advantage of SiGe HBT mostlys come from current-carrying caused by the less band gaps of SiGe and band gap gradient
Sub- longitudinal electric field accelerates.But, the longitudinal electron mobility critically important to base resistance and horizontal hole mobility are only minimum
Improvement.On the other hand, in CMOS technology, the key performance enhancer of less than 90 nanometers CMOS is by stress engineering reality
Existing transverse field Enhanced mobility.In one embodiment, band gap engineering and mobility engineering combine, and further improve
The performance of HBT.For example, extra stress processes and can be used to improve horizontal hole mobility, and SiGe HBT are limited most so as to reduce
The base resistance of big operating frequency.
Claims (21)
1. a kind of transistor, it is characterised in that include：
The single crystal epitaxial metal silicide layer in Semiconductor substrate；
The monocrystalline emitter being formed on the metal silicide layer；
The base stage being formed on the emitter stage；With formation monocrystal silicon colelctor electrode on said base；
The insulation dielectric layer being deposited on the emitter stage, base stage and colelctor electrode, the contact hole being formed in insulation dielectric layer；
It is formed in the contact area of the correspondence contact hole position on emitter stage, base stage and colelctor electrode；
Wherein, the transistor has inverted structure of the colelctor electrode closer to transistor surface.
2. transistor according to claim 1, it is characterised in that the single crystal epitaxial metal silicide is to be located at Si substrates
On extension NiSi2Film.
3. transistor according to claim 1, it is characterised in that the single crystal epitaxial metal silicide layer thickness be less than or
Person is equal to 10 nanometers, and the base stage has the width less than or equal to 10 nanometers.
4. transistor according to claim 1, it is characterised in that the emitter stage is carbon doping.
5. transistor according to claim 1, it is characterised in that the thickness of the emitter stage and the colelctor electrode is respectively less than
Or equal to 10 nanometers.
6. transistor according to claim 1, it is characterised in that in the emitter stage, the base stage and the colelctor electrode
At least one is formed by least one ALE techniques.
7. transistor according to claim 1, it is characterised in that the base stage includes SiGe SiGe.
8. transistor according to claim 1, further distinguishes on the emitter stage, the base stage and the colelctor electrode
Comprising Metal-silicides Contact area；The Metal-silicides Contact area has the resistivity of low-down 45 micro-ohm cm.
9. transistor according to claim 1, it is characterised in that the colelctor electrode is strained in carrier transport direction
Process.
10. transistor according to claim 1, it is characterised in that the extremely lightly doped silicon of the current collection and in upper surface
There is metal silicide layer.
11. transistors according to claim 1, it is characterised in that the base stage carries out strained handling.
12. transistors according to claim 11, it is characterised in that the base stage is further entered in an extra direction
Row strained handling.
13. a kind of manufacture methods of transistor, it is characterised in that comprise the steps of：
Epitaxial growth single-crystal metal silicide layer on a semiconductor substrate；
In the metal silicide layer Epitaxial growth monocrystalline emitter；
In the emitter stage Epitaxial growth base stage；
Epitaxial growth monocrystal silicon colelctor electrode on said base；
Insulation dielectric layer is deposited on the emitter stage, base stage and colelctor electrode, contact hole is formed in insulation dielectric layer；
The correspondence contact hole position forms contact area on emitter stage, base stage and colelctor electrode.
14. according to claim 13 transistor manufacture method, it is characterised in that the metal silicide layer is using solid
State reaction SSR techniques are grown in the NiSi on Si2Film.
15. according to claim 14 transistor manufacture method, it is characterised in that the SSR is processed and is included following sub-step
Suddenly：
Ni film of the sputtering sedimentation thickness less than or equal to 2 nanometers；
Heat treatment.
16. according to claim 13 transistor manufacture method, it is characterised in that the emitter stage is given birth to by ALE techniques
It is long.
17. according to claim 16 transistor manufacture method, it is characterised in that the emitter stage is in ALE technical processs
In carry out carbon doping in situ.
18. according to claim 16 transistor manufacture method, it is characterised in that in ALE technical processs, using from swash
The photon that light source sends helps the hydrogen atom on release liners surface.
19. according to claim 16 transistor manufacture method, it is characterised in that further comprise the steps of：To Si
Emitter layer carries out strained handling.
20. according to claim 16 transistor manufacture method, it is characterised in that further comprise the steps of：It is right
SiGe base layers carry out strained handling in multiple directions.
21. according to claim 16 transistor manufacture method, it is characterised in that further comprise the steps of：To collection
Electrode layer applies mechanical stress from the top surface of the transistor.
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| US4492971A (en) * | 1980-06-05 | 1985-01-08 | At&T Bell Laboratories | Metal silicide-silicon heterostructures |
| JPS5891631A (en) * | 1981-11-27 | 1983-05-31 | Hitachi Ltd | Semiconductor device |
| JP2001332565A (en) * | 2000-05-25 | 2001-11-30 | Nec Corp | Negative differential resistance element and its manufacturing method |
| US6825538B2 (en) * | 2002-11-20 | 2004-11-30 | Agere Systems Inc. | Semiconductor device using an insulating layer having a seed layer |
| US7102205B2 (en) * | 2004-09-01 | 2006-09-05 | International Business Machines Corporation | Bipolar transistor with extrinsic stress layer |
| CN101162730B (en) * | 2007-11-13 | 2010-04-07 | 清华大学 | Polycrystal collecting area invert structure SiGe hetero-junction transistor |
| US8716835B2 (en) * | 2008-10-21 | 2014-05-06 | Renesas Electronics Corporation | Bipolar transistor |
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| CN103000674A (en) | 2013-03-27 |
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