CN102998501A - Method for achieving data compression of digital oscilloscope based on field programmable gata array - Google Patents
Method for achieving data compression of digital oscilloscope based on field programmable gata array Download PDFInfo
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Abstract
The invention discloses a method for achieving data compression of a digital oscilloscope based on a field programmable gata array (FPGA). The method for achieving the data compression of the digital oscilloscope based on the FPGA includes that digital signal data which is collected by analog signals through a module converter is compressed by the FPGA, the FPGA firstly stores data in an external storage into a storage FIFO1, and a first value, a maximum value, a minimum value and a last value of data are found out from a set of data according to given compressibility and then are stored in a storage FIFO2 through a compression module, digital signals in the external storage are circularly processed, and when a data volume in the storage FIFO2 reaches a set value, the storage FIFO2 stores and retrieves the data no longer, and the data in the storage FIFO2 is sent to an oscilloscope screen to be displayed. The method for achieving the data compression of the digital oscilloscope based on the FPGA not only improves the storage depth of the oscilloscope, but also accelerates the update rate of the oscilloscope, a continuous wave shape is obtained, and the capture rate of the oscilloscope is improved.
Description
Technical field
The present invention relates to the oscillograph digital processing field, relate in particular to a kind of method that realizes the digital oscilloscope data compression based on FPGA.
Background technology
Digital oscilloscope is converted to digital signal by analog to digital converter (hereinafter to be referred as ADC) with analog quantity, gathers by FPGA finally to be shown on the screen.Storage depth is the important indicator parameter of digital oscilloscope.Storage depth is higher, and within the identical sampling time, oscillograph can demonstrate more obvious waveform details, is more conducive to the user and observes waveform.Refresh rate also is an oscillographic parameter, and refresh rate is faster, can allow the user see more continuous waveform, improves oscillographic capture rate.
But storage depth is more and more higher, needs the adc data of access also will become many in the time of sampling once, if directly whole adc datas are shown, can cause oscillographic refresh rate slack-off, the capture rate step-down of waveform.
Summary of the invention
The object of the present invention is to provide a kind of oscillographic storage depth that both improved, do not reduce again the method based on the data compression of FPGA realization digital oscilloscope of oscillograph refresh rate simultaneously.
To achieve these goals, the following technical scheme of the present invention:
A kind of method based on the data compression of FPGA realization digital oscilloscope, described oscillograph comprises:
External memory storage, the digital signal data that the outside simulating signal of storage collects through the analog-to-digital conversion device;
FPGA processes digital signal data in the described external memory storage;
Screen shows the digital signal after described FPGA processes;
Described external memory storage, FPGA and screen are electrically connected successively, it is characterized in that:
Described method based on the data compression of FPGA realization digital oscilloscope is: by FPGA the digital signal data after transforming through the analog-to-digital conversion device is compressed, digital signal after the conversion of analog-to-digital conversion device is stored in the external memory storage, the signal total amount that collects is defined as T, the FPGA compressibility is defined as N, each group data semaphore is a, the group number is T/N, according to given compressibility, FPGA takes out first a digital signal and deposits in the storer FIFO1 from the digital signal of external memory stores, and from a data semaphore, find out first value in this group digital signal, maximal value, minimum value and last are worth compressed module and deposit in the storer FIFO2, in the FPGA processing digital signal simultaneously, untreated digital signal in the external memory storage deposited in the storer FIFO1 prepare for value, each group data value that circulates is processed, until FPGA handles the signal total amount T that is stored in the external memory storage for T/N time through circulation, data volume reaches setting value in storer FIFO2, storer FIFO2 is access data no longer, gives the oscillograph screen display with the data in the storer FIFO2.
Described method concrete steps are as follows:
1). judge the data volume of storing in the storer FIFO1 among the FPGA, if the data volume of storing in the storer FIFO1 among the FPGA is less than setting value, then the data in the external memory storage are deposited in the storer FIFO1, if the data volume of storage is greater than setting value in the storer FIFO1 among the FPGA, then the data in the external memory storage do not deposit in the storer FIFO1;
2). the group of each in storer FIFO1 digital signal is that 1 arithmetic progression mode is numbered by tolerance among the FPGA to being deposited into, the first digit signal that deposits in is numbered a, last digital signal that deposits in is numbered 1, with this group be with numbered digital signal by number tolerance be 1 to carry out loss ratio pair, first data value, maximum data value, minimum data value and the compressed module of last data value in this group digital signal of obtaining are deposited among the FPGA in the storer FIFO2;
3). to being deposited into every group of digital signal repeating step 2 in the storer FIFO1 among the FPGA);
4). judge the data volume of storing in the storer FIFO2 among the FPGA, reach the data value of setting, then access data no longer sends to the oscillograph screen display with the data of storing in the storer FIFO2 among the FPGA, do not reach the data value of setting, then continue access data.
Described external memory storage, storer FIFO1 and storer FIFO2 are first in first out formula storer.
Described analog-to-digital conversion device is collected simulating signal, and the digital signal that transforms is deposited in the external memory storage.
The present invention adopts above technical scheme, utilize FPGA that simulating signal is compressed through the digital signal data that the analog-to-digital conversion device collects, FPGA deposits the data in the external memory storage in the storer FIFO1 in first, according to given compressibility, from one group of data, find out first value of data, maximal value, minimum value and last are worth compressed module and deposit in the storer FIFO2, constantly the datacycle in the external memory storage is processed afterwards, data volume reaches setting value in storer FIFO2, storer FIFO2 is access data no longer, give the oscillograph screen display with the data in the storer FIFO2, the present invention had both improved oscillographic storage depth, accelerated simultaneously the oscillograph refresh rate, obtain more continuous waveform, improve oscillographic capture rate.
Description of drawings
Now by reference to the accompanying drawings the present invention is further described:
Fig. 1 is the schematic flow sheet of FPGA data compression of the present invention;
Fig. 2 is the process flow diagram of FPGA data compression algorithm of the present invention.
Embodiment
See also shown in one of Fig. 1-2, the present invention includes external memory storage 1, the digital signal data that the outside simulating signal of storage collects through the analog-to-digital conversion device, FPGA2, process digital signal data in the described external memory storage, screen 3 shows the digital signal after described FPGA2 processes, and described external memory storage 1, FPGA2 and screen 3 are electrically connected successively.
See also Fig. 1, in this embodiment, introduced the basic procedure of ADC data in the FPGA internal compression.
Described method based on the data compression of FPGA realization digital oscilloscope is: by FPGA2 the digital signal data after transforming through analog-to-digital conversion device 7 is compressed, digital signal after analog-to-digital conversion device 7 transforms is stored in the external memory storage 1, the signal total amount that collects is defined as T, the FPGA compressibility is defined as N, each group data semaphore is a, the group number is T/N, according to given compressibility, FPGA2 takes out first a digital signal and deposits in the storer FIFO1 4 from the digital signal of external memory stores 1, and from a data semaphore, find out first value in this group digital signal, maximal value, minimum value and last are worth compressed module and deposit in the storer FIFO2 6, in the FPGA2 processing digital signal simultaneously, untreated digital signal in the external memory storage 1 deposited in the storer FIFO1 4 prepare for value, each group data value that circulates is processed, until FPGA2 handles the signal total amount T that is stored in the external memory storage 1 for T/N time through circulation, when storer FIFO2 6 interior data volumes reach setting value, storer FIFO2 6 is access data no longer, gives oscillograph screen 3 with the data in the storer FIFO2 6 and shows.
Provide a preferential embodiment at this, further the present invention is explained in connection with given data compression rate, set external memory storage 1 simulating signal collects T=10M through analog-to-digital conversion device 7 digital signal data, data compression rate N is 10000:1, the semaphore of each group is defined as a, and concrete steps are as follows:
1). judge the data volume of storer FIFO1 4 interior storages among the FPGA2, if the data volume of storer FIFO1 4 interior storages is less than setting value among the FPGA2, then the data in the external memory storage 1 are deposited in the storer FIFO1 4, if the data volume of storer FIFO1 4 interior storages is greater than setting value among the FPGA2, then the data in the external memory storage do not deposit in the storer FIFO1 4, and concrete grammar is as follows:
Judge that whether the data volume of storer FIFO1 4 interior storages is less than 64, if the data volume of storer FIFO1 4 interior storages is less than 64, then the data in the external memory storage 1 are deposited in the storer FIFO1 4, if the data volume of storer FIFO1 4 interior storages is greater than 64, then the data in the external memory storage do not deposit in the storer FIFO1 4;
Judge among this embodiment of the present invention that setting value is 64 in the data volume step of storer FIFO1 4 interior storages among the FPGA 2, be to be understood that, the setting value here only for explanatory purposes, it is not restriction interest field of the present invention, setting value is identical from the digital signal amount that external memory storage 1 reads each time with storer FIFO1 4 in the present embodiment, the digital signal amount that the type of memory difference then reads at every turn is different, can set according to the type of storer, general setting value is the signal quantity that storer reads at every turn.
2). the group of each in the storer FIFO1 4 digital signal is that 1 arithmetic progression mode is numbered by tolerance among the FPGA2 to being deposited into, the first digit signal that deposits in is numbered a, last digital signal that deposits in is numbered 1, with this group be with numbered digital signal by number tolerance be 1 to carry out loss ratio pair, first data value, maximum data value, minimum data value and the compressed module 5 of last data value in this group digital signal of obtaining are deposited among the FPGA2 in the storer FIFO2 6, and concrete grammar is as follows:
A). be N with semaphore a assignment, a carried out from subtracting that being about to semaphore a assignment is 10000, and be 1 to successively decrease successively the numbering of semaphore a by tolerance, for making things convenient for digital signal circulation grouping, at this every group of semaphore is defined as compressibility, a=N is such as Fig. 2 step S1;
B). judge whether semaphore a is N, namely when semaphore a=10000, RD_en is set to 1, WR_en and is set to 1 in the compression module, the compressed module 5 of first data value that reads in the storer FIFO1 is deposited among the FPGA 2 in the storer FIFO2 6, such as Fig. 2 step S11;
C). judge that semaphore is whether between 1＜a＜N, namely work as semaphore a in 1＜a＜10000, RD_en is set to 1 in the compression module 5, WR_en is set to 0, with each data reading, and compare with upper data, obtain maximal value and the minimum value of data, compressed module 5 deposits among the FPGA 2 in the storer FIFO2 6, such as Fig. 2 step S12;
D). judge whether semaphore is 1, namely when semaphore a=1, RD_en is set to 1, WR_en and is set to 0 in the compression module, the compressed module 5 of last data value that reads in the storer FIFO1 is deposited among the FPGA 2 in the storer FIFO2 6, such as Fig. 2 step S13;
3). to being deposited into every group of digital signal repeating step 2 in the storer FIFO1 4 among the FPGA 2);
When the value of semaphore a is 1, be 10000 with semaphore a assignment again, begin circulation, such as Fig. 2 step S2
4). judge the data volume of storer FIFO2 6 interior storages among the FPGA 2, reach the data value of setting, access data no longer then sends to oscillograph screen 3 with the data of storer FIFO2 6 interior storages among the FPGA 2 and shows, do not reach the data value of setting, then continue access data.
Among this embodiment, the data volume of storing in the external memory storage is 10M, data compression rate N is 10000:1, in every this circulation, with first data value in this group digital signal of obtaining, maximum data value, minimum data value and the compressed module 5 of last data value deposit among the FPGA2 in the storer FIFO26, the method of 10000 data in present embodiment in each group becomes 4 data, so when the data volume in the storer FIFO2 6 does not reach 4000, then continue access data, when the data volume in the storer reaches 4000, storer FIFO2 6 is access data no longer, give the oscillograph screen display with the data of storer FIFO2 6, so far data the oscillograph screen show Paint Gloss, other requires emphasis a bit, and when the digital signal of the present invention in to every group was numbered, numbering was by descending being numbered of appended compressibility value, for making things convenient for embodiment to illustrate, be not the restriction to the inventive method only.
The method of the description in the present embodiment is when processing data, and relative one traditional processing mode had both improved oscillographic storage depth, had accelerated simultaneously the oscillograph refresh rate, obtained more continuous waveform, improved oscillographic capture rate.
Detailed description by above embodiment, wish more to know description feature of the present invention, belong to claim of the present invention and equivalent technologies scope thereof if those skilled in the art carries out various changes and distortion to the present invention, then the present invention also comprises these changes and distortion.
Claims (4)
1. realize the method for digital oscilloscope data compression based on FPGA for one kind, described oscillograph comprises:
External memory storage, the digital signal data that the outside simulating signal of storage collects through the analog-to-digital conversion device;
FPGA processes digital signal data in the described external memory storage;
Screen shows the digital signal after described FPGA processes;
Described external memory storage, FPGA and screen are electrically connected successively, it is characterized in that:
Described method based on the data compression of FPGA realization digital oscilloscope is: by FPGA the digital signal data after transforming through the analog-to-digital conversion device is compressed, digital signal after the analog-to-digital conversion device transforms is stored in the external memory storage, the signal total amount that collects is defined as T, the FPGA compressibility is defined as N, each group data semaphore is a, the group number is T/N, according to given compressibility, FPGA takes out first a digital signal and deposits in the storer FIFO1 from the digital signal of external memory stores, and from a data semaphore, find out first value in this group digital signal, maximal value, minimum value and last are worth compressed module and deposit in the storer FIFO2, in the FPGA processing digital signal simultaneously, untreated digital signal in the external memory storage deposited in the storer FIFO1 prepare for value, each group data value that circulates is processed, until FPGA handles the signal total amount T that is stored in the external memory storage for T/N time through circulation, data volume reaches setting value in storer FIFO2, storer FIFO2 is access data no longer, gives the oscillograph screen display with the data in the storer FIFO2.
2. according to claim 1ly realize the method for digital oscilloscope data compression based on FPGA, it is characterized in that: described method concrete steps are as follows:
1). judge the data volume of storing in the storer FIFO1 among the FPGA, if the data volume of storing in the storer FIFO1 among the FPGA is less than setting value, then the data in the external memory storage are deposited in the storer FIFO1, if the data volume of storage is greater than setting value in the storer FIFO1 among the FPGA, then the data in the external memory storage do not deposit in the storer FIFO1;
2). be that 1 arithmetic progression mode is numbered to being deposited into the group of each in the storer FIFO1 among FPGA digital signal by tolerance, the first digit signal that deposits in is numbered a, last digital signal that deposits in is numbered 1, with this group be with numbered digital signal by number tolerance be 1 to carry out loss ratio pair, first data value, maximum data value, minimum data value and the compressed module of last data value in this group digital signal of obtaining are deposited among the FPGA in the storer FIFO2;
3). to being deposited into every group of digital signal repeating step 2 in the storer FIFO1 among the FPGA);
4). judge the data volume of storing in the storer FIFO2 among the FPGA, reach the data value of setting, then access data no longer sends to the oscillograph screen display with the data of storing in the storer FIFO2 among the FPGA, do not reach the data value of setting, then continue access data.
3. according to claim 1 and 2ly realize the method for digital oscilloscope data compression based on FPGA, it is characterized in that: described external memory storage, storer FIFO1 and storer FIFO2 are first in first out formula storer.
4. the method that realizes the digital oscilloscope data compression based on FPGA according to claim 1 and 2, it is characterized in that: described analog-to-digital conversion device is collected simulating signal, and the digital signal that transforms is deposited in the external memory storage.
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| CN103592487A (en) * | 2013-10-31 | 2014-02-19 | 江苏绿扬电子仪器集团有限公司 | Peak detection device for meeting glitch capturing requirement of oscilloscope |
| CN103630721A (en) * | 2013-11-19 | 2014-03-12 | 中国电子科技集团公司第四十一研究所 | Method for improving mixed oscillograph digital channel waveform capture rate |
| CN103969484A (en) * | 2014-05-30 | 2014-08-06 | 广州致远电子股份有限公司 | High-refresh-rate waveform synthesizer and high-refresher-rate oscilloscope |
| CN104267281A (en) * | 2014-09-25 | 2015-01-07 | 国家电网公司 | Method for monitoring state of distributed low-voltage distribution network and compressing data |
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| CN103630721A (en) * | 2013-11-19 | 2014-03-12 | 中国电子科技集团公司第四十一研究所 | Method for improving mixed oscillograph digital channel waveform capture rate |
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| CN104267281A (en) * | 2014-09-25 | 2015-01-07 | 国家电网公司 | Method for monitoring state of distributed low-voltage distribution network and compressing data |
| CN104267281B (en) * | 2014-09-25 | 2017-03-15 | 国家电网公司 | A kind of distributed low-voltage network Condition Monitoring Data compression method |
| CN104730307A (en) * | 2015-03-02 | 2015-06-24 | 深圳市鼎阳科技有限公司 | Gray level digital oscilloscope and waveform processing module and method thereof |
| CN104730307B (en) * | 2015-03-02 | 2017-07-18 | 深圳市鼎阳科技有限公司 | Tonal gradation digital oscilloscope and its waveform processing module and method |
| CN104881339A (en) * | 2015-05-18 | 2015-09-02 | 昆山龙腾光电有限公司 | Testing device, testing method and display system |
| CN104881339B (en) * | 2015-05-18 | 2018-09-18 | 昆山龙腾光电有限公司 | A kind of test device, test method and display system |
| CN105467182A (en) * | 2015-12-16 | 2016-04-06 | 福建利利普光电科技有限公司 | Oscilloscope with data recording function and data recording method |
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| CN106680560B (en) * | 2016-11-21 | 2019-07-05 | 成都定为电子技术有限公司 | A kind of the measuring signal 3 D displaying method and system of high capture rate |
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| CN112199010B (en) * | 2020-12-03 | 2021-03-30 | 深圳市鼎阳科技股份有限公司 | Full storage depth measuring method, digital oscilloscope and storage medium |
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