CN102971809B - Multilayer ceramic electronic component and manufacture method thereof - Google Patents
Multilayer ceramic electronic component and manufacture method thereof Download PDFInfo
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- CN102971809B CN102971809B CN201180032422.1A CN201180032422A CN102971809B CN 102971809 B CN102971809 B CN 102971809B CN 201180032422 A CN201180032422 A CN 201180032422A CN 102971809 B CN102971809 B CN 102971809B
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- 239000000919 ceramic Substances 0.000 title claims abstract description 378
- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000004020 conductor Substances 0.000 claims abstract description 468
- 239000010410 layer Substances 0.000 claims description 517
- 239000012212 insulator Substances 0.000 claims description 28
- 239000011229 interlayer Substances 0.000 claims description 23
- 238000002360 preparation method Methods 0.000 claims description 6
- 238000005245 sintering Methods 0.000 description 7
- 230000000052 comparative effect Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 238000009413 insulation Methods 0.000 description 5
- 238000007747 plating Methods 0.000 description 5
- 230000011218 segmentation Effects 0.000 description 5
- 229910000859 α-Fe Inorganic materials 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000006071 cream Substances 0.000 description 3
- 238000002788 crimping Methods 0.000 description 3
- 239000000428 dust Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 229910007565 Zn—Cu Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000002270 dispersing agent Substances 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000008012 organic excipient Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000004014 plasticizer Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 239000000080 wetting agent Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/2804—Printed windings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
- H01F17/0013—Printed inductances with stacked layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
- H01F41/02—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets
- H01F41/04—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets for manufacturing coils
- H01F41/041—Printed circuit coils
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/165—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed inductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/4902—Electromagnet, transformer or inductor
Abstract
The present invention relates to multilayer ceramic electronic component and manufacture method thereof.In the multilayer ceramic electronic component possessing coil-conductor, the performance of coil can not be sacrificed and reduce the stacked number of ceramic layer, or need not maximize and just can increase the number of turn of coil.In multilayer ceramic electronic component, for 1 layer of ceramic layer, form the coil-conductor of the number of turn had more than 1 circle.This coil-conductor comprises the surface coils conductor (14,19,24,29) that the surface along each ceramic layer (2-1 ~ 2-4) stacked gradually exists and the layer interior loop conductor (17,22,27,32) being positioned at the inside of ceramic layer in the scope of thickness being no more than 1 ceramic layer, and surface coils conductor and layer interior loop conductor are connected in series via connecting portion (16,21,26,31).
Description
Technical field
The present invention relates to multilayer ceramic electronic component and manufacture method thereof, particularly relate to the multilayer ceramic electronic component and manufacture method thereof that possess coil-conductor.
Background technology
As the typical case of multilayer ceramic electronic component possessing the coil-conductor extended in coiled type in inside, such as, there is laminated coil parts described such in Japanese Patent Publication 63-44286 publication (patent documentation 1).When manufacturing laminated coil parts, implement following operation: form coil-conductor according to the surface of the ceramic green sheet at magnetic or insulator, the mode that one end of this coil-conductor is connected with other coil-conductor via the hole being located at ceramic green sheet, stacked multiple ceramic green sheet, and crimp, thus produce the operation of unsintered article body; And to the operation that unsintered article body sinters.Above-mentioned coil-conductor is formed at the surface of ceramic green sheet by the printing employing conductive paste.
Therefore, according to the technology described in patent documentation 1, in unsintered article body, can cause defining thickness difference between the part of coil-conductor and part in addition and density contrast in ceramic green sheet.And, when having sintered article body, defining between the part of coil-conductor and part in addition, because Shrinkage behavior can produce difference, often in article body, produce crack, or coil-conductor breaking.
In addition, according to the technology described in patent documentation 1, at stacked multiple ceramic green sheet, and carry out in the operation crimped, likely can the skew of generating coil conductor, distortion and broken string.
In order to solve the above problems, such as Japanese Unexamined Patent Publication 10-12455 publication (patent documentation 2) proposes following proposal, namely in ceramic green sheet, arranges grooving, by filled conductive cream in this grooving, forms coil-conductor.
But, for the technology recorded in one section of document any in patent documentation 1 and 2, seeking to take into account the multifunction of electronic unit and the present of miniaturization, also having further room for improvement.Such as, if when the performance of keeping coil is constant, the stacked number of ceramic layer can be reduced, then can be conducive to the high performance of electronic unit and taking into account of miniaturization.
Patent documentation 1: Japanese Patent Publication 63-44286 publication
Patent documentation 2: Japanese Unexamined Patent Publication 10-12455 publication
Summary of the invention
So, the object of the present invention is to provide the problem that can solve above-mentioned look-ahead technique and meet with, and multilayer ceramic electronic component and the manufacture method thereof of above-mentioned hope can be met.
The present invention relates to first towards the technology of multilayer ceramic electronic component, it is characterized in that, multilayer ceramic electronic component possesses article body, the inner conductor that this article body comprises stacked multi-layer ceramics layer and arranges with correlating with specific ceramic layer, inner conductor comprises coil-conductor, this coil-conductor extend over plural layers ceramic layer is connected in series successively, and extend in coiled type, in order to solve above-mentioned technical task, for the ceramic layer of 1 layer, above-mentioned coil-conductor has the number of turn more than 1 circle.
Multilayer ceramic electronic component of the present invention preferred embodiment in, the ceramic layer of relative 1 layer is had for the coil-conductor more than the number of turn of 1 circle, this coil-conductor comprises the surface coils conductor that the surface along ceramic layer exists and the layer interior loop conductor being positioned at the inside of ceramic layer in the scope of thickness being no more than 1 ceramic layer, and possesses the connecting portion for being connected in series surface coils conductor and layer interior loop conductor.
Above-mentioned preferred embodiment in, for more specifically the 1st example for, through on the thickness direction that layer interior loop conductor is provided in ceramic layer, the state being formed as being electrically insulated from each other except connecting portion for making surface coils conductor and layer interior loop conductor, surface coils conductor and layer interior loop conductor are positioned at position different from each other on the interarea direction of ceramic layer.
In addition, above-mentioned preferred embodiment in, for more specifically the 2nd example for, not through on the thickness direction that layer interior loop conductor is provided in ceramic layer, the state being formed as being electrically insulated from each other except connecting portion for making surface coils conductor and layer interior loop conductor, also possesses the insulator be arranged on layer interior loop conductor, effects on surface coil-conductor and the above-mentioned insulator of layer interior loop conductor are present in each other, and the surface coils conductor being formed at a side of adjacent ceramic layer and the layer interior loop conductor being formed at the opposing party are positioned at position different from each other on the interarea direction of ceramic layer.
In addition, above-mentioned preferred embodiment in, also can comprise and only be provided with surface coils conductor that the surface along ceramic layer the exists ceramic layer as coil-conductor.
In addition, above-mentioned preferred embodiment in, also can comprise only be provided with the inside being positioned at ceramic layer in the scope of the thickness being no more than 1 ceramic layer layer interior loop conductor as the ceramic layer of coil-conductor.
Multilayer ceramic electronic component of the present invention can be the form of component-mounted substrate, namely also possess the external conductor film that is formed on the outer surface of article body and be connected with external conductor film and be installed in the surface mounting electronic member on the outer surface of article body, can also be the form of chip coil, namely also possess and to be connected with inner conductor and to be drawn to the bonding conductor of the outer surface of article body and to be connected with bonding conductor and to be formed in the external terminal electrode on the outer surface of article body.
The present invention is in addition also towards the manufacture method of multilayer ceramic electronic component.
The feature of the manufacture method of multilayer ceramic electronic component of the present invention is to possess: the operation preparing the multiple ceramic green sheets that form respectively the coil-conductor extended in coiled type; According to the mode of the multiple coil-conductors be in turn connected to form in each ceramic green sheet, stacked multiple ceramic green sheet, and crimp, thus make the operation of unsintered article body; And sinter the operation of unsintered article body, in order to solve aforesaid technical task, possess following formation.
Namely, the feature preparing the operation of above-mentioned ceramic green sheet is, comprise the operation of preparation the 1st ceramic green sheet, described 1st ceramic green sheet is provided with surface coils conductor, the layer interior loop conductor being positioned at the inside of ceramic green sheet in the scope of thickness not exceeding ceramic green sheet and the connecting portion for being connected in series surface coils conductor and layer interior loop conductor that the surface along ceramic green sheet exists.
In preferred 1st execution mode of the manufacture method about multilayer ceramic electronic component of the present invention, the operation preparing the 1st ceramic green sheet possesses: form a layer operation for interior loop conductor according to mode through on the thickness direction of ceramic green sheet; The position different from layer interior loop conductor on the interarea direction of ceramic green sheet forms the operation of surface coils conductor.
In preferred 2nd execution mode of the manufacture method about multilayer ceramic electronic component of the present invention, the operation preparing the 1st ceramic green sheet possesses: form a layer operation for interior loop conductor according to mode not through on the thickness direction of ceramic green sheet; Layer interior loop conductor is formed the operation of insulator; And form the operation of surface coils conductor on insulator.
In the manufacture method of multilayer ceramic electronic component of the present invention, prepare the operation that the operation of ceramic green sheet can also comprise preparation the 2nd ceramic green sheet, the 2nd ceramic green sheet is only provided with surface coils conductor that the surface along ceramic green sheet exists as coil-conductor.In this situation, the operation making unsintered article body comprises: the operation arranging interlayer connection conductor according to mode through on the thickness direction of specific ceramic green sheet; According to the mode connecting a part for surface coils conductor for the 1st ceramic green sheet and a part for the surface coils conductor of the 2nd ceramic green sheet via interlayer connection conductor, stacked multiple ceramic green sheet, and carry out the operation that crimps.
In the manufacture method of multilayer ceramic electronic component of the present invention, the operation preparing ceramic green sheet can also comprise the operation of preparation the 3rd ceramic green sheet, and the 3rd ceramic green sheet is only provided with the layer interior loop conductor of the inside being positioned at ceramic green sheet in the scope of the thickness being no more than 1 ceramic green sheet as coil-conductor.In this situation, the operation making unsintered article body comprises: according to the mode of a part for a part for the layer interior loop conductor of connection the 1st ceramic green sheet and the layer interior loop conductor of the 3rd ceramic green sheet, stacked multiple ceramic green sheet, and carry out the operation that crimps.
According to the present invention, possess for 1 layer of ceramic layer, there is the coil-conductor of the number of turn more than 1 circle, therefore, it is possible to do not sacrifice the performance of coil and reduce the stacked number of ceramic layer, or multilayer ceramic electronic component can not be made to maximize and increase the number of turn of coil.Therefore, also can realize the miniaturization of multilayer ceramic electronic component, especially slimming and high performance simultaneously.
The surface coils conductor existed along the surface of ceramic layer by combination and the layer interior loop conductor being positioned at the inside of ceramic layer in the scope of thickness being no more than 1 ceramic layer, form coil-conductor, and utilize connecting portion to be connected in series surface coils conductor and layer interior loop conductor, like this, easily can realize the ceramic layer for 1 layer as described above, there is the coil-conductor of the number of turn more than 1 circle.
When above-mentioned, through on the thickness direction that layer interior loop conductor is provided in ceramic layer, because surface coils conductor and layer interior loop conductor are formed as the state for being electrically insulated from each other except above-mentioned connecting portion, if surface coils conductor and layer interior loop conductor are positioned at position different from each other on the interarea direction of ceramic layer, the situation that then coil-conductor concentrates on 1 place is alleviated, therefore, it is possible to make the crack of the article body that can produce in the sintering circuit of the manufacture of multilayer ceramic electronic component, the broken string of coil-conductor, or, the skew of the coil-conductor that can produce in crimping process, distortion and broken string are difficult to produce.
In addition, not through on the thickness direction that layer interior loop conductor is provided in ceramic layer, because surface coils conductor and layer interior loop conductor are formed as the state for being electrically insulated from each other except connecting portion, even if be therefore provided with insulator on layer interior loop conductor, when there is above-mentioned insulator among each other in surface coils conductor and layer interior loop conductor, due between adjacent ceramic layer, surface coils conductor and layer interior loop conductor are in position different from each other on the interarea direction of ceramic layer, therefore the situation with above-mentioned is same, the situation that coil-conductor concentrates on 1 place is alleviated.Therefore, it is possible to make the crack of the article body that can produce in the sintering circuit of the manufacture of multilayer ceramic electronic component, the broken string of coil-conductor, or the skew of the coil-conductor that can produce in crimping process, distortion and broken string are difficult to produce.
Accompanying drawing explanation
Fig. 1 is the profile of the multilayer ceramic electronic component representing the 1st execution mode of the present invention.
Fig. 2 is the vertical view of multiple ceramic layers of the coiler part separately representing the multilayer ceramic electronic component shown in pie graph 1.
Fig. 3 only takes out and represents the profile of the coiler part of the multilayer ceramic electronic component of the 2nd execution mode of the present invention.
Fig. 4 is the vertical view of the multiple ceramic layers separately representing the coiler part shown in pie graph 3.
Fig. 5 only takes out and represents the profile of the coiler part of the multilayer ceramic electronic component of the 3rd execution mode of the present invention.
Fig. 6 is the vertical view of the multiple ceramic layers separately representing the coiler part shown in pie graph 5.
Fig. 7 only takes out and represents the profile of the coiler part of the multilayer ceramic electronic component of the 4th execution mode of the present invention.
Fig. 8 represents the 1st layer of ceramic layer of the coiler part shown in pie graph 7, and (1), (2) and (3A) are the vertical views of the manufacture process representing the 1st layer of ceramic layer in order, and (3B) is the profile of the line B-B along (3A).
Fig. 9 represents the 2nd layer of ceramic layer of the coiler part shown in pie graph 7, and (1), (2) and (3A) are the vertical views of the manufacture process representing the 2nd layer of ceramic layer in order, and (3B) is the profile of the line B-B along (3A).
Figure 10 represents the 3rd layer of ceramic layer of the coiler part shown in pie graph 7, and (1), (2) and (3A) are the vertical views of the manufacture process representing the 3rd layer of ceramic layer in order, and (3B) is the profile of the line B-B along (3A).
Figure 11 represents the 4th layer of ceramic layer of the coiler part shown in pie graph 7, and (1), (2) and (3A) are the vertical views of the manufacture process representing the 4th layer of ceramic layer in order, and (3B) is the profile of the line B-B along (3A).
Figure 12 is the profile of the multilayer ceramic electronic component representing the 5th execution mode of the present invention.
Figure 13 is the profile of the multilayer ceramic electronic component represented as comparative example of the present invention.
Figure 14 is the vertical view of the multiple ceramic layers separately representing the coiler part forming the multilayer ceramic electronic component shown in Figure 13.
Embodiment
With reference to Fig. 1, the multilayer ceramic electronic component 1 of the 1st execution mode of the present invention is described.
Multilayer ceramic electronic component 1 possesses the article body 3 of lit-par-lit structure, and the article body 3 of this lit-par-lit structure is formed with stacked multiple ceramic layers 2.The upper main surface and below interarea of article body 3 are respectively arranged with external conductor film 4 and 5.In the inside of article body 3, with specific ceramic layer 2 associated be provided with several inner conductor.
Inner conductor has various form.1st, there is the face inner wire film 6 extended between ceramic layer 2.2nd, exist along the through interlayer connection conductor 7 of the thickness direction of ceramic layer 2.And then, when classifying from the viewpoint of electric function, there is the coil-conductor 8 playing function as coil.Multiple ceramic layer 2-1,2-2,2-3 and 2-4 that coil-conductor 8 spreads all over the coiler part 9 being arranged in article body 3 are connected in series in order, and extend in coiled type.
In addition, the Reference numeral " 2 " marked " ceramic layer " is for comprising all ceramic layers of " ceramic layer 2-1,2-2,2-3 and 2-4 ".And, when needing the ceramic layer 2 being positioned at coiler part 9 to distinguish with other ceramic layer, to the ceramic layer 2 being positioned at coiler part 9, use the Reference numeral of " 2-1 ", " 2-2 ", " 2-3 " and " 2-4 ".
Aftermentioned to the detailed content of coil-conductor 8, the feature of coil-conductor 8 is, to 1 layer of ceramic layer, has the number of turn more than 1 circle.In addition, be arranged in the ceramic layer 2-1 ~ 2-4 of coiler part 9, although not shown, but the inner conductor beyond coil-conductor 8 also can be set.
Ceramic layer 2 is such as made up of ferrite ceramics.As ferrite ceramics, such as, can use the ferrite ceramics of composition of Fe-Ni-Zn-Cu system, Fe-Zn-Cu system or Fe-Mn-Zn system.In addition, all ceramic layers 2 can be formed by ferrite ceramics, or, also can only form by ferrite ceramics the ceramic layer 2-1 ~ 2-4 being positioned at coiler part 9, also can be made up of other ceramic layer 2 dielectric ceramics or ceramic insulator.
This multilayer ceramic electronic component 1 such as forms DC-DC converter, mounting surface mount type electronic unit 10 and 11 in article body 3 upper main surface.Electronic unit 10 is such as IC chip, is electrically connected with external conductor film 4 via solder projection 12.Another electronic unit 11 is such as chip capacitor, is electrically connected with external conductor film 4 via solder 13.The external conductor film 5 be formed on the below interarea of article body 3 uses as terminal electrode when installing this multilayer ceramic electronic component 1 on not shown mother substrate.
Then, with reference to Fig. 1 and Fig. 2, the formation of coiler part 9 is described.In fig. 2, the go up most the 1st layer of ceramic layer 2-1 vertical view formed in the ceramic layer 2-1 ~ 2-4 of coiler part 9 illustrates in (1), the 2nd layer of ceramic layer 2-2 vertical view under it is shown in (2), the 3rd layer of ceramic layer 2-3 vertical view under it is shown in (3), and the 4th layer of ceramic layer 2-4 vertical view under it illustrates in (4).The profile of Fig. 1 represents the section of the line A-A along Fig. 2 (1) to (4).
If be roughly described, then coil-conductor 8 comprises the layer interior loop conductor of the inside of the surface coils conductor that each layer surface along ceramic layer 2-1 ~ 2-4 exist and each layer being positioned at ceramic layer 2-1 ~ 2-4 in the scope of thickness being no more than 1 ceramic layer, also possesses the connecting portion for being connected in series surface coils conductor and layer interior loop conductor.In fig. 2, above-mentioned surface coils conductor is subjected to closeer hacures to illustrate, and above-mentioned layer interior loop conductor is subjected to reverse thicker hacures and illustrates.In addition, so hatched mode is also used in other accompanying drawing of correspondence.
With reference to Fig. 2 (1), at the upper surface of the 1st layer of ceramic layer 2-1, surface coils conductor 14, from the top 15 of the upper left of figure, almost defines 1 circle clockwise, and at connecting portion 16 place, layer interior loop conductor 17 and surface coils conductor 14 are connected in series.The top 15 of surface coils conductor 14 is electrically connected with other not shown electric circuit elements.Layer interior loop conductor 17, according to the mode of the thickness direction of the inside and through ceramic layer 2-1 that are positioned at ceramic layer 2-1, forms almost 1/4 circle.
The state being formed as electrically insulated from one another except connecting portion 16 except for making surface coils conductor 14 and layer interior loop conductor 17, surface coils conductor 14 and layer interior loop conductor 17 are formed at position different from each other on the interarea direction of ceramic layer 2.
Like this, in the 1st layer of ceramic layer 2-1, surface coils conductor 14 and layer interior loop conductor 17 are with roughly 5/4 circle altogether, and not in the same face, and the state staggered along the direction orthogonal with the interarea direction of ceramic layer 2-1 is formed.Layer interior loop conductor 17 is through on the thickness direction of ceramic layer 2-1, and therefore also can expose in the lower face side of ceramic layer 2-1, only the terminal 18 of layer interior loop conductor 17 leaves the connecting portion with the 2nd layer of ceramic layer 2-2 for.
Then, with reference to Fig. 2 (2), at the upper surface of the 2nd layer of ceramic layer 2-2, surface coils conductor 19 forms almost 1 circle clockwise from the top 20 be connected with the terminal 18 of above-mentioned layer interior loop conductor 17, at connecting portion 21 place, layer interior loop conductor 22 and surface coils conductor 19 are connected in series.Layer interior loop conductor 22, according to being positioned at the inside of ceramic layer 2-2 and mode through on the thickness direction of ceramic layer 2-2, forms almost 1/4 circle.The state being formed as being electrically insulated from each other except connecting portion 21 except for making surface coils conductor 19 and layer interior loop conductor 22, surface coils conductor 19 and layer interior loop conductor 22 are formed at position different from each other on the interarea direction of ceramic layer 2.In addition, surface coils conductor 19 except its top 20, with the 1st layer by layer the position of interior loop conductor 17 on the interarea direction of ceramic layer 2 staggered.
Like this, in the 2nd layer of ceramic layer 2-2, surface coils conductor 19 and layer interior loop conductor 22 are also with roughly 5/4 circle altogether, and not in the same face, and the state staggered on the direction that the interarea direction with ceramic layer 2-2 is orthogonal is formed.Layer interior loop conductor 22 is through on the thickness direction of ceramic layer 2-2, and therefore also can expose in the lower face side of ceramic layer 2-2, only the terminal 23 of layer interior loop conductor 22 leaves the connecting portion with the 3rd layer of ceramic layer 2-3 for.
Then, with reference to Fig. 2 (3), at the upper surface of the 3rd layer of ceramic layer 2-3, surface coils conductor 24 forms almost 1 circle clockwise from the top 25 be connected with the terminal 23 of above-mentioned layer interior loop conductor 22, at connecting portion 26 place, layer interior loop conductor 27 and surface coils conductor 24 are connected in series.Layer interior loop conductor 27, according to being positioned at the inside of ceramic layer 2-3 and mode through on the thickness direction of ceramic layer 2-3, forms almost 1/4 circle.The state being formed as being electrically insulated from each other except connecting portion 26 except for making surface coils conductor 24 and layer interior loop conductor 27, surface coils conductor 24 and layer interior loop conductor 27 are formed at position different from each other on the interarea direction of ceramic layer 2.In addition, surface coils conductor 24 except its top 25, with the 2nd layer by layer the position of interior loop conductor 22 on the interarea direction of ceramic layer 2 staggered.
Like this, in the 3rd layer of ceramic layer 2-3, surface coils conductor 24 and layer interior loop conductor 27 are with roughly 5/4 circle altogether, and not in the same face, and the state staggered on the direction that the interarea direction with ceramic layer 2-3 is orthogonal is formed.Layer interior loop conductor 27 is through on the thickness direction of ceramic layer 2-3, and therefore also can expose in the lower face side of ceramic layer 2-3, only the terminal 28 of layer interior loop conductor 27 leaves the connecting portion with the 4th layer of ceramic layer 2-4 for.
Then, with reference to Fig. 2 (4), at the upper surface of the 4th layer of ceramic layer 2-4, surface coils conductor 29 forms almost 1 circle clockwise from the top 30 be connected with the terminal 28 of above-mentioned layer interior loop conductor 27, locate in connecting portion 31, layer interior loop conductor 32 and surface coils conductor 29 are connected in series.Layer interior loop conductor 32, according to being positioned at the inside of ceramic layer 2-4 and mode through on the thickness direction of ceramic layer 2-4, forms almost 1/4 circle.The state being formed as being electrically insulated from each other except connecting portion 31 except for making surface coils conductor 29 and layer interior loop conductor 32, surface coils conductor 29 and layer interior loop conductor 32 are formed at position different from each other on the interarea direction of ceramic layer 2.In addition, surface coils conductor 29 except its top 30, with the 3rd layer by layer the position of interior loop conductor 27 on the interarea direction of ceramic layer 2 staggered.
Like this, in the 4th layer of ceramic layer 2-4, surface coils conductor 29 and layer interior loop conductor 32 are also with roughly 5/4 circle altogether, and not in the same face, and the state staggered on the direction that the interarea direction with ceramic layer 2-3 is orthogonal is formed.Layer interior loop conductor 32 is through on the thickness direction of ceramic layer 2-4, and therefore also can expose in the lower face side of ceramic layer 2-4, the terminal 33 of layer interior loop conductor 32 leaves the connecting portion with other electric circuit element (not shown) for.
The above expression that is formed in also is identified along in Fig. 1 of the section of the line A-A of Fig. 2 (1) to (4).
Then, the manufacture method of multilayer ceramic electronic component 1 is described.
First, the ceramic green sheet that will become ceramic layer 2 is prepared.These ceramic green sheets in ceramic material powder, add adhesive, plasticizer, wetting agent, dispersant etc. carry out slurried, and be configured as sheet and obtain.
Then, by forming through hole in specific ceramic green sheet, in through hole, filled conductive cream forms unsintered interlayer connection conductor 7, in addition, by printing conductive paste on specific ceramic green sheet, form unsintered external conductor film 4 and 5 and face inner wire film 6.
For the ceramic green sheet that will become ceramic layer 2-1 ~ 2-4, for forming layer interior loop conductor 17,22,27 and 32, through gap is set, wherein filled conductive cream, then, for forming surface coils conductor 14,19,24 and 29, printing conductive paste.In this operation, also can give the conductive paste of layer interior loop conductor 17,22,27 and 32 and the conductive paste of surface coils conductor 14,19,24 and 29 simultaneously.
As the conductive paste forming said external electrically conductive film 4 and 5, face inner wire film 6, interlayer connection conductor 7, surface coils conductor 14,19,24 and 29 and layer interior loop conductor 17,22,27 and 32, such as can use with Ag, Ag ?Pd, Ag ?the metal dust such as Pt, Cu, Au, Pt, Al principal component that is electric conducting material, make such metal dust be scattered in the conductive paste being formed as paste in organic excipients.In addition, form the conductive paste of external conductor film 4 and 5, face inner wire film 6 and surface coils conductor 14,19,24 and 29 compared with forming the conductive paste of interlayer connection conductor 7 and layer interior loop conductor 17,22,27 and 32, in order to improve printing, also can carry out making adjustment such as comprised metal dust less grade.
Then, with the stacked above-mentioned ceramic green sheet of the order specified, then by carrying out crimping the duplexer of the non-sintering state obtaining article body 3.In this unsintered article body 3, according to the mode forming coil-conductor 8 in aforesaid mode, become the state of be linked in sequence surface coils conductor 14,19,24 and 29 and layer interior loop conductor 17,22,27 and 32.
In addition, when the article body 3 of operation such above to the Set Status for manufacturing multiple multilayer ceramic electronic component 1 is simultaneously implemented, in order to easily splitting the article body 3 of this Set Status afterwards, slot segmentation is formed with.
Then, sinter unsintered article body 3, thus, obtain the article body 3 after sintering.
Then, plating process is implemented to the external conductor film 4 and 5 exposed on the surface of article body 3.More specifically, implement plating, thus, such as, form plated nickel film and tin-plated coating film in order.In addition, plating process also can be undertaken by electroless plating, in this situation, such as, forms plated nickel film and gold-plated film in order.
Then, in the upper main surface of article body 3, carry surface mounting electronic member 10 and 11 according to the mode becoming the state be electrically connected with external conductor film 4.
And, when implementing above operation to the article body 3 of Set Status, implementing the operation split along aforesaid slot segmentation, separating multilayer ceramic electronic component 1 one by one.Although not shown, but as required, multilayer ceramic electronic component 1 can install metal cap body.
In the above description, before sintering circuit, define slot segmentation, also can not form slot segmentation, before sintering circuit, the article body 3 of segmentation Set Status, takes out the article body 3 of the state of the life of the article body 3 of multilayer ceramic electronic component 1 one by one.In this situation, sintering circuit is implemented article body 3 one by one, in plating process, such as, can apply the electrolysis plating of bucket.
With reference to Fig. 3 and Fig. 4, the 2nd execution mode of the present invention is described.In Fig. 3 and Fig. 4, for ceramic layer 2-1 ~ 2-4, mark the Reference numeral same with the situation of Fig. 1 and Fig. 2.Fig. 3 is the profile only taking out the coiler part 9a corresponding with the coiler part 9 of the multilayer ceramic electronic component 1 shown in Fig. 1 and represent.The profile of Fig. 3 represents the section of the line A-A along Fig. 4 (1) to (4).Fig. 4 is the figure corresponding with Fig. 2, represents the vertical view of multiple ceramic layer 2-1,2-2,2-3 and the 2-4 of the coiler part 9a shown in pie graph 3 respectively.In addition, in Fig. 3 and Fig. 4, the interval between the width of coil-conductor and coil-conductor and other execution mode illustrate narrowly, but such difference is not internal for the 2nd execution mode.
With reference to Fig. 4 (1), at the upper surface of the 1st layer of ceramic layer 2-1, surface coils conductor 34 deasil forms roughly 1 circle from the top 35 of the upper left of figure, and at connecting portion 36 place, layer interior loop conductor 37 and surface coils conductor 34 are connected in series.The top 35 of surface coils conductor 34 is electrically connected with other not shown electric circuit element.Layer interior loop conductor 37, according to being positioned at the inside of ceramic layer 2-1 and mode through on the thickness direction of ceramic layer 2-1, forms roughly 1 circle.The state being formed as being electrically insulated from each other except connecting portion 36 except for making surface coils conductor 34 and layer interior loop conductor 37, surface coils conductor 34 and layer interior loop conductor 37 are formed at position different from each other on the interarea direction of ceramic layer 2.
Like this, in the 1st layer of ceramic layer 2-1, surface coils conductor 34 and layer interior loop conductor 37 are with roughly 2 circles altogether, and not in the same face, and the state staggered on the direction that the interarea direction with ceramic layer 2-1 is orthogonal is formed.Layer interior loop conductor 37 is through on the thickness direction of ceramic layer 2-1, and therefore also can expose in the lower face side of ceramic layer 2-1, only the terminal 38 of layer interior loop conductor 37 leaves the connecting portion with the 2nd layer of ceramic layer 2-2 for.
Then, with reference to Fig. 4 (2), in the 2nd layer of ceramic layer 2-2, layer interior loop conductor 39 forms almost 1 circle clockwise from the top 40 be connected with the terminal 38 of above-mentioned layer interior loop conductor 37.Layer interior loop conductor 39 is positioned at the inside of ceramic layer 2-2 and through on the thickness direction of ceramic layer 2-2.In order to be formed except the terminal 38 of layer interior loop conductor 37 and the connecting portion at the top 40 of layer interior loop conductor 39, layer interior loop conductor 37 and the state of layer interior loop conductor 39 for being electrically insulated from each other, layer interior loop conductor 37 and layer interior loop conductor 39 are formed at position different from each other on the interarea direction of ceramic layer 2.
Layer interior loop conductor 39 is through on the thickness direction of ceramic layer 2-2, and therefore also can expose in the lower face side of ceramic layer 2-2, only the terminal 41 of layer interior loop conductor 39 leaves the connecting portion with the 3rd layer of ceramic layer 2-3 for.
Then, with reference to Fig. 4 (3), at the upper surface of the 3rd layer of ceramic layer 2-3, surface coils conductor 42 is from the top 43 be connected with the terminal 41 of above-mentioned layer interior loop conductor 39, deasil form almost 1 circle, at connecting portion 44 place, layer interior loop conductor 45 and surface coils conductor 42 are connected in series.Layer interior loop conductor 45, according to being positioned at the inside of ceramic layer 2-3 and mode through on the thickness direction of ceramic layer 2-3, forms roughly 1 circle.The state being formed as being electrically insulated from each other except connecting portion 44 except to make surface coils conductor 42 and layer interior loop conductor 45, surface coils conductor 42 and layer interior loop conductor 45 are formed at position different from each other on the interarea direction of ceramic layer 2.In addition, surface coils conductor 42 and layer interior loop conductor 45 except the top 43 of surface coils conductor 42, with the 2nd layer by layer the position of interior loop conductor 39 on the interarea direction of ceramic layer 2 staggered.
Like this, in the 3rd layer of ceramic layer 2-3, surface coils conductor 42 and layer interior loop conductor 45 are with roughly 2 circles altogether, and not in the same face, and the state staggered on the direction that the interarea direction with ceramic layer 2-3 is orthogonal is formed.Layer interior loop conductor 45 is through on the thickness direction of ceramic layer 2-3, and therefore also can expose in the lower face side of ceramic layer 2-3, only the terminal 46 of layer interior loop conductor 45 leaves the connecting portion with the 4th layer of ceramic layer 2-4 for.
Then, with reference to Fig. 4 (4), at the upper surface of the 4th layer of ceramic layer 2-4, layer interior loop conductor 47 forms almost 9/8 circle clockwise from the top 48 be connected with the terminal 46 of above-mentioned layer interior loop conductor 45.Layer interior loop conductor 47 is positioned at the inside of ceramic layer 2-4 and through on the thickness direction of ceramic layer 2-4.In order to be formed except the terminal 46 of layer interior loop conductor 45 and the connecting portion at the top 48 of layer interior loop conductor 47, layer interior loop conductor 45 and layer interior loop conductor 47 are the state of electric insulation each other, and layer interior loop conductor 45 and layer interior loop conductor 47 are formed at position different from each other on the interarea direction of ceramic layer 2.The terminal 49 of layer interior loop conductor 47 leaves the connecting portion with other electric circuit element (not shown) for.
The above expression that is formed in also is identified along in Fig. 3 of the section of the line A-A of Fig. 4 (1) to (4).
With reference to Fig. 5 and Fig. 6, the 3rd execution mode of the present invention is described.In Fig. 5 and Fig. 6, for ceramic layer 2-1 ~ 2-4, mark the Reference numeral same with the situation of Fig. 1 and Fig. 2.Fig. 5 only takes out the profile that the coiler part 9b corresponding with the coiler part 9 of the multilayer ceramic electronic component 1 shown in Fig. 1 represent.The profile of Fig. 5 represents the section of the line A-A along Fig. 6 (1) to (4).Fig. 6 is the figure corresponding with Fig. 2, is the vertical view of multiple ceramic layer 2-1,2-2,2-3 and the 2-4 representing the coiler part 9b shown in pie graph 5 respectively.
With reference to Fig. 6 (1), at the upper surface of the 1st layer of ceramic layer 2-1, surface coils conductor 50 forms roughly 1 circle clockwise from the top 51 of the upper left of figure, and at connecting portion 52 place, layer interior loop conductor 53 and surface coils conductor 50 are connected in series.The top 51 of surface coils conductor 50 is electrically connected with other not shown electric circuit elements.Layer interior loop conductor 53, according to being positioned at the inside of ceramic layer 2-1 and mode through on the thickness direction of ceramic layer 2-1, forms roughly 1 circle.For making surface coils conductor 50 and layer interior loop conductor 53 be formed as the state be electrically insulated from each other except connecting portion 52, surface coils conductor 50 and layer interior loop conductor 53 are formed at position different from each other on the interarea direction of ceramic layer 2.
Like this, in the 1st layer of ceramic layer 2-1, surface coils conductor 50 and layer interior loop conductor 53 are with roughly 2 circles altogether, and not in the same face, and the state staggered on the direction that the interarea direction with ceramic layer 2-1 is orthogonal is formed.Layer interior loop conductor 53 is through on the thickness direction of ceramic layer 2-1, and therefore also can expose in the lower face side of ceramic layer 2-1, only the terminal 54 of layer interior loop conductor 53 leaves the connecting portion with the 2nd layer of ceramic layer 2-2 for.
Then, with reference to Fig. 6 (2), at the upper surface of the 2nd layer of ceramic layer 2-2, surface coils conductor 55 forms roughly 1 circle clockwise from the top 56 be connected with the terminal 54 of above-mentioned layer interior loop conductor 53.Surface coils conductor 55 is in order to be formed as except its top 56 is with except the connecting portion of the terminal 54 of layer interior loop conductor 53, with the state of layer interior loop conductor 53 electric insulation, therefore on the interarea direction of ceramic layer 2, be formed at position different from each other with layer interior loop conductor 53.
The interlayer connection conductor 58 of through ceramic layer 2-2 is in a thickness direction provided with in the terminal 57 of surface coils conductor 55.Interlayer connection conductor 58 is also exposed in the lower face side of ceramic layer 2-2, and only interlayer connection conductor 58 leaves the connecting portion with the 3rd layer of ceramic layer 2-3 for.
Then, with reference to Fig. 6 (3), at the upper surface of the 3rd layer of ceramic layer 2-3, surface coils conductor 59 forms almost 1 circle clockwise from the top 60 be connected with above-mentioned interlayer connection conductor 58, at connecting portion 61 place, layer interior loop conductor 62 and surface coils conductor 59 are connected in series.Layer interior loop conductor 62 is according to the inside being positioned at ceramic layer 2-3 and mode through on the thickness direction of ceramic layer 2-3 forms roughly 1 circle.For making surface coils conductor 59 and layer interior loop conductor 62 be formed as the state be electrically insulated from each other except connecting portion 61, surface coils conductor 59 and layer interior loop conductor 62 are formed at position different from each other on the interarea direction of ceramic layer 2.
Like this, in the 3rd layer of ceramic layer 2-3, surface coils conductor 59 and layer interior loop conductor 62 are with roughly 2 circles altogether, and not in the same face, and the state staggered on the direction that the interarea direction with ceramic layer 2-3 is orthogonal is formed.Layer interior loop conductor 62 is through on the thickness direction of ceramic layer 2-3, and therefore also can expose in the lower face side of ceramic layer 2-3, only the terminal 63 of layer interior loop conductor 62 leaves the connecting portion with the 4th layer of ceramic layer 2-4 for.
Then, with reference to Fig. 6 (4), at the upper surface of the 4th layer of ceramic layer 2-4, surface coils conductor 64 forms roughly 1 circle clockwise from the top 65 be connected with the terminal 63 of above-mentioned layer interior loop conductor 62.Surface coils conductor 64 except its top 65, with the 3rd layer by layer the position of interior loop conductor 62 on the interarea direction of ceramic layer 2 staggered.In the terminal 66 of surface coils conductor 64, mode through on the thickness direction of ceramic layer 2-4 is provided with interlayer connection conductor 67, this interlayer connection conductor 67 leaves the connecting portion with other electric circuit element (not shown) for.
The above expression that is formed in also is identified in Fig. 5 of the section of the line A-A of Fig. 6 (1) to (4).
With reference to Fig. 7 to Figure 11, the 4th execution mode of the present invention is described.In Fig. 7 to Figure 11, for ceramic layer 2-1 ~ 2-4, give the Reference numeral identical with the situation of Fig. 1 and Fig. 2.Fig. 7 only takes out the profile that the coiler part 9c corresponding with the coiler part 9 of the multilayer ceramic electronic component 1 shown in Fig. 1 represent.The profile of Fig. 7 represents the section of the line A-A along Fig. 8 to Figure 11.
First, with reference to Fig. 8, the 1st layer of ceramic layer 2-1 of the coiler part 9c shown in pie graph 7 is described.
As shown in Fig. 8 (1), in the 1st layer of ceramic layer 2-1, first, layer interior loop conductor 68 deasil forms roughly 1 circle to terminal 70 from its top 69.Layer interior loop conductor 68 is as shown in Fig. 8 (3B), and the lower surface being provided in ceramic layer 2-1 exposes, but not through in a thickness direction.In addition, Fig. 8 (3B) represents the section along the line B-B of Fig. 8 (3A), and thickness direction size is expressed turgidly.In other accompanying drawings of correspondence too.
Then, as shown in Fig. 8 (2), according to except the top 69 except layer interior loop conductor 68, the mode of cover layer interior loop conductor 68 arranges insulator 71.Specifically, insulator 71 by filling ceramic size and being formed in the gap of conductive paste having imported layer interior loop conductor 68.
Then, as shown in Fig. 8 (3A) and (3B), insulator 71 arranges surface coils conductor 72.Surface coils conductor 72 deasil forms roughly 1 circle from its top 73 to terminal 74.The terminal 74 of surface coils conductor 72 is connected with the top 69 of layer interior loop conductor 68.
Like this, in the 1st layer of ceramic layer 2-1, terminal 70 from the top 73 of surface coils conductor 72 to layer interior loop conductor 68, with not in the same face, and the state staggered on the direction that the interarea direction with ceramic layer 2-1 is orthogonal forms the coil-conductor extended along clockwise direction.
Layer interior loop conductor 68 exposes in the lower face side of ceramic layer 2-1, and therefore only the terminal 70 of layer interior loop conductor 68 leaves the connecting portion with the 2nd layer of ceramic layer 2-2 for.
Then, with reference to Fig. 9, the 2nd layer of ceramic layer 2-2 of the coiler part 9c shown in pie graph 7 is described.
As shown in Fig. 9 (1), in the 2nd layer of ceramic layer 2-2, first, layer interior loop conductor 75 deasil forms roughly 1 circle from its top 76 to terminal 77.As shown in Fig. 9 (3B), the lower surface that layer interior loop conductor 75 is provided in ceramic layer 2-2 exposes, but not through in a thickness direction.
Then, as shown in Fig. 9 (2), according to except the top 76 except layer interior loop conductor 75, the mode of cover layer interior loop conductor 75 arranges insulator 78.Specifically, insulator 78 by filling ceramic size and being formed in the gap of conductive paste having imported layer interior loop conductor 75.
Then, as shown in Fig. 9 (3A) and (3B), insulator 78 arranges surface coils conductor 79.Surface coils conductor 79 deasil forms roughly 1 circle from its top 80 to terminal 81.The terminal 81 of surface coils conductor 79 is connected with the top 76 of layer interior loop conductor 75.
Like this, in the 2nd layer of ceramic layer 2-2, from the terminal 77 of top 80 to the layer interior loop conductor 75 of surface coils conductor 79, with not in the same face, and the state staggered on the direction that the interarea direction with ceramic layer 2-2 is orthogonal forms the coil-conductor extended along clockwise direction.
The terminal 70 being arranged in the layer interior loop conductor 68 of the 1st layer of ceramic layer 2-1 is connected with the top 80 of above-mentioned surface coils conductor 79.In addition, in order to be formed as except the terminal 70 of layer interior loop conductor 68 and the connecting portion at the top 80 of surface coils conductor 79, layer interior loop conductor 68 is the state of electric insulation with surface coils conductor 79, and layer interior loop conductor 68 and surface coils conductor 79 are formed at position different from each other on the interarea direction of ceramic layer 2.
Layer interior loop conductor 75 exposes in the lower face side of ceramic layer 2-2, and therefore only the terminal 77 of layer interior loop conductor 75 leaves the connecting portion with the 3rd layer of ceramic layer 2-3 for.
Then, with reference to Figure 10, the 3rd layer of ceramic layer 2-3 of the coiler part 9c shown in pie graph 7 is described.
As shown in Figure 10 (1), in the 3rd layer of ceramic layer 2-3, first, layer interior loop conductor 82 deasil forms roughly 1 circle from its top 83 to terminal 84.As shown in Figure 10 (3B), the lower surface that layer interior loop conductor 82 is provided in ceramic layer 2-3 exposes, but not through in a thickness direction.
Then, as shown in Figure 10 (2), according to except the top 83 except layer interior loop conductor 82, the mode of cover layer interior loop conductor 82 arranges insulator 85.Specifically, insulator 85 by filling ceramic size and being formed in the gap of conductive paste having imported layer interior loop conductor 82.
Then, as shown in Figure 10 (3A) and (3B), insulator 85 arranges surface coils conductor 86.Surface coils conductor 86 deasil forms roughly 1 circle from its top 87 to terminal 88.The terminal 88 of surface coils conductor 86 is connected with the top 83 of layer interior loop conductor 82.
Like this, in the 3rd layer of ceramic layer 2-3, terminal 84 from the top 87 of surface coils conductor 86 to layer interior loop conductor 82, with not in the same face, and the state staggered on the direction that the interarea direction with ceramic layer 2-3 is orthogonal forms the coil-conductor extended along clockwise direction.
The terminal 77 being positioned at the layer interior loop conductor 75 of the 2nd layer of ceramic layer 2-2 is connected with the top 87 of above-mentioned surface coils conductor 86.In addition, in order to be formed except the terminal 77 of layer interior loop conductor 75 and the connecting portion at the top 87 of surface coils conductor 86, layer interior loop conductor 75 is the state of electric insulation with surface coils conductor 86, and layer interior loop conductor 75 and surface coils conductor 86 are formed at position different from each other on the interarea direction of ceramic layer 2.
Layer interior loop conductor 82 exposes in the lower face side of ceramic layer 2-3, and therefore only the terminal 84 of layer interior loop conductor 82 leaves the connecting portion with the 4th layer of ceramic layer 2-4 for.
Then, with reference to Figure 11, the 4th layer of ceramic layer 2-4 of the coiler part 9c shown in pie graph 7 is described.
As shown in Figure 11 (1), in the 4th layer of ceramic layer 2-4, first, layer interior loop conductor 89 deasil forms roughly 1 circle from its top 90 to terminal 91.As shown in Figure 11 (3B), the lower surface that layer interior loop conductor 89 is provided in ceramic layer 2-4 exposes, but not through in a thickness direction.
Then, as shown in Figure 11 (2), according to except the top 90 except layer interior loop conductor 89, the mode of cover layer interior loop conductor 89 arranges insulator 92.Specifically, insulator 92 by filling ceramic size and being formed in the gap of conductive paste having imported layer interior loop conductor 89.
Then, as shown in Figure 11 (3A) and (3B), insulator 92 arranges surface coils conductor 93.Surface coils conductor 93 deasil forms roughly 1 circle from its top 94 to terminal 95.The terminal 95 of surface coils conductor 93 is connected with the top 90 of layer interior loop conductor 89.
Like this, in the 4th layer of ceramic layer 2-4, terminal 91 from the top 94 of surface coils conductor 93 to layer interior loop conductor 89, with not in the same face, and the state staggered on the direction that the interarea direction with ceramic layer 2-4 is orthogonal forms the coil-conductor extended along clockwise direction.
The terminal 84 being positioned at the layer interior loop conductor 82 of the 3rd layer of ceramic layer 2-3 is connected with the top 94 of above-mentioned surface coils conductor 93.In addition, in order to be formed as except the terminal 84 of layer interior loop conductor 82 and the connecting portion at the top 94 of surface coils conductor 93, layer interior loop conductor 82 is the state of electric insulation with surface coils conductor 93, and layer interior loop conductor 82 and surface coils conductor 93 are formed at position different from each other on the interarea direction of ceramic layer 2.
Layer interior loop conductor 89 exposes in the lower face side of ceramic layer 2-4, and therefore the terminal 91 of layer interior loop conductor 89 leaves the connecting portion with other electric circuit element (not shown) for.
The above expression that is formed in also is identified in Fig. 7 of the section of the line A-A of Fig. 8 to Figure 11.
In addition, in Fig. 7 to Figure 11, not through on the thickness direction that layer interior loop conductor is provided in ceramic layer, but it is through on the thickness direction that also layer interior loop conductor can be arranged in ceramic layer, and coated with ceramic slurry forms insulator, form surface coils conductor on insulator thereon.
Figure 12 is the profile of the cascade type chip coil 101 of the multilayer ceramic electronic component represented as the 5th execution mode of the present invention.Cascade type chip coil 101 shown in Figure 12 possesses the element general with the multilayer ceramic electronic component 1 illustrated with reference to Fig. 1 and Fig. 2, therefore mark same Reference numeral to general element, and the repetitive description thereof will be omitted.
Cascade type chip coil 101 possess be formed at article body 102 upper main surface and below interarea on terminal electrode 103 and 104.One terminal electrode 103 is via top 15(reference Fig. 2 (1) of bonding conductor 105 with the surface coils conductor 14 in coil-conductor 8) be connected.Another terminal electrode 104 is via terminal 33(reference Fig. 2 (4) of bonding conductor 106 with the layer interior loop conductor 32 in coil-conductor 8) be connected.
In addition, above-mentioned bonding conductor 105 and 106 does not appear on the section shown in Figure 12, therefore represented by dashed line.Although not shown, but also can change to form terminal electrode 103 and 104 on the side of article body 102, bonding conductor 105 and 106 is drawn in the side towards article body 102.
In the 1st to the 5th execution mode described above, the number of plies forming the ceramic layer 2 of coiler part 9 is 4 layers, but this number of plies also can increase and decrease as required.
In order to confirm effect of the present invention, for the embodiment 1 ~ 4 coil structure of aforesaid 1st to the 4th execution mode being applied to cascade type chip coil as shown in Figure 12, have rated each inductance coefficent.
Here, in order to can easily effect more of the present invention with past case, as comparative example, the cascade type chip coil 111 shown in Figure 13 and Figure 14 have been made.
If be described the cascade type chip coil 111 of comparative example, then cascade type chip coil 111 possesses the article body 113 of lit-par-lit structure, and the article body 113 of this lit-par-lit structure is formed with stacked multiple ceramic layers 112.The upper main surface and below interarea of article body 113 are respectively arranged with terminal electrode 114 and 115.In the inside of article body 113, be formed with coil-conductor 116.Be connected in series in order in the scope of coil-conductor 116 4 layers of ceramic layer 112-1,112-2,112-3 and 112-4 in article body 113, and extend in coiled type.
More specifically, as shown in Figure 14 (1), at the upper surface of the 1st layer of ceramic layer 112-1, surface coils conductor 117 deasil forms roughly 1 circle from top 118 to terminal 119, at terminal 119 place, arranges interlayer connection conductor 120 through in a thickness direction.
Then, as shown in Figure 14 (2), at the upper surface of the 2nd layer of ceramic layer 112-2, surface coils conductor 121 deasil forms roughly 1 circle from top 122 to terminal 123.Aforesaid interlayer connection conductor 120 is connected with the top 122 of surface coils conductor 121.The terminal 123 of surface coils conductor 121 is provided with interlayer connection conductor 124 through in a thickness direction.
Then, as shown in Figure 14 (3), at the upper surface of the 3rd layer of ceramic layer 112-3, surface coils conductor 125 deasil forms roughly 1 circle from top 126 to terminal 127.Aforesaid interlayer connection conductor 124 is connected with the top 126 of surface coils conductor 125.The terminal 127 of surface coils conductor 125 is provided with interlayer connection conductor 128 through in a thickness direction.
Then, as shown in Figure 14 (4), at the upper surface of the 4th layer of ceramic layer 112-4, surface coils conductor 129 deasil forms roughly 1 circle from top 130 to terminal 131.Aforesaid interlayer connection conductor 128 is connected with the top 130 of surface coils conductor 129.The terminal 131 of surface coils conductor 129 is provided with interlayer connection conductor 132 through in a thickness direction.
Referring again to Figure 13, a terminal electrode 114 is via top 118(reference Figure 14 (1) of bonding conductor 133 with the surface coils conductor 117 in coil-conductor 116) be connected.Another terminal electrode 115 via bonding conductor 134 be arranged in coil-conductor 116 surface coils conductor 129 terminal 131 interlayer connection conductor 132(with reference to Figure 14 (4)) be connected.
For embodiment 1 ~ 4 such above and comparative example, the number of plies making ceramic layer is uniformly 4 layers, and each thickness making ceramic layer is 25 μm, makes the width of coil-conductor be 200 μm, and inductance coefficent when measuring 1MHz.Result is shown in table 1.Also the number of turn of coil is shown in table 1.
[table 1]
| The number of turn of coil | Inductance coefficent | |
| Embodiment 1 | 5 | 0.61 |
| Embodiment 2 | 6 | 0.82 |
| Embodiment 3 | 6 | 0.81 |
| Embodiment 4 | 8 | 1.21 |
| Comparative example | 4 | 0.45 |
Known according to table 1, according to embodiment 1 ~ 4, obtain the number of turn of the coil more than the number of plies of ceramic layer, result, compared with comparative example, achieve high inductance coefficent.
The explanation of Reference numeral
1 multilayer ceramic electronic component; 2,2-1,2-2,2-3,2-4 ceramic layer; 3,102 article body; 4,5 external conductor films; 8 coil-conductors; 9,9a, 9b, 9c coiler part; 10,11 surface mounting electronic members; 14,19,24,29,34,42,50,55,59,64,72,79,86,93 surface coils conductors; 16,21,26,31,36,44,52,61 connecting portions; 17,22,27,32,37,39,45,47,53,62,68,75,82,89 layers of interior loop conductor; 58,67 interlayer connection conductor; 71,78,85,92 insulators; 101 cascade type chip coils; 103,104 terminal electrodes; 105,106 bonding conductors.
Claims (8)
1. a multilayer ceramic electronic component, wherein,
This multilayer ceramic electronic component possesses article body, the inner conductor that this article body comprises stacked multi-layer ceramics layer and arranges with correlating with specific described ceramic layer, described inner conductor comprises coil-conductor, this coil-conductor is connected in series successively in the scope of ceramic layer described in multilayer, and extend in coiled type
For the described ceramic layer of 1 layer, described coil-conductor has the number of turn more than 1 circle,
For the coil-conductor described ceramic layer of relative 1 layer to the number of turn exceeding described 1 circle, this coil-conductor comprises the surface coils conductor that the surface along ceramic layer exists and the layer interior loop conductor being positioned at the inside of ceramic layer in the scope of thickness being no more than 1 ceramic layer, and described coil-conductor possesses the connecting portion for being connected in series described surface coils conductor and described layer interior loop conductor further
Not through on the thickness direction that described layer interior loop conductor is provided in ceramic layer, the state being formed as being electrically insulated from each other except described connecting portion for making described surface coils conductor and described layer interior loop conductor, also possesses the insulator be arranged on described layer interior loop conductor, be present in each other concerning described insulator described surface coils conductor and described layer interior loop conductor, and the described surface coils conductor being formed at side's ceramic layer of adjacent described ceramic layer and the described layer interior loop conductor being formed at the opposing party's ceramic layer are positioned at position different from each other on the interarea direction of ceramic layer.
2. multilayer ceramic electronic component according to claim 1, wherein,
Described ceramic layer comprises and only arranges surface coils conductor that the surface along ceramic layer the exists ceramic layer as described coil-conductor.
3. multilayer ceramic electronic component according to claim 1, wherein,
Described ceramic layer comprise only be arranged on the thickness being no more than 1 ceramic layer scope in be positioned at the ceramic layer of layer interior loop conductor as described coil-conductor of the inside of ceramic layer.
4. multilayer ceramic electronic component according to claim 1, wherein,
Described multilayer ceramic electronic component also possesses the external conductor film on the outer surface being formed in described article body; And to be connected with described external conductor film and to be arranged on the surface mounting electronic member on the outer surface of described article body.
5. multilayer ceramic electronic component according to claim 1, wherein,
Described multilayer ceramic electronic component also possesses and to be connected with described inner conductor and to be drawn to the bonding conductor of the outer surface of described article body, and is connected with described bonding conductor and is formed at the external terminal electrode on the outer surface of described article body.
6. a manufacture method for multilayer ceramic electronic component, wherein, possesses:
Prepare the operation of the multiple ceramic green sheets that form respectively the coil-conductor extended in coiled type;
According to the mode of the multiple described coil-conductor be in turn connected to form in ceramic green sheet described in each, stacked multiple described ceramic green sheet, and crimp, thus make the operation of unsintered article body; And
Sinter the operation of described unsintered article body,
The operation preparing described ceramic green sheet comprises the operation of preparation the 1st ceramic green sheet, described 1st ceramic green sheet is provided with surface coils conductor, the layer interior loop conductor being positioned at the inside of ceramic green sheet in the scope of thickness not exceeding ceramic green sheet and the connecting portion for being connected in series described surface coils conductor and described layer interior loop conductor that the surface along ceramic green sheet exists
The operation preparing described 1st ceramic green sheet possesses: the operation forming described layer interior loop conductor according to mode not through on the thickness direction of ceramic green sheet; Described layer interior loop conductor is formed the operation of insulator; And on described insulator, form the operation of described surface coils conductor,
Described insulator is according to except the top except layer interior loop conductor, and the mode of cover layer interior loop conductor is arranged, and described connecting portion is for the terminal at the top and described surface coils conductor that connect described layer interior loop conductor.
7. the manufacture method of multilayer ceramic electronic component according to claim 6, wherein,
The operation preparing described ceramic green sheet comprises the operation of preparation the 2nd ceramic green sheet, and described 2nd ceramic green sheet is only provided with surface coils conductor that the surface along ceramic green sheet exists as described coil-conductor,
The operation making described unsintered article body comprises: arrange the operation of interlayer connection conductor according to through mode on the thickness direction of specific described ceramic green sheet; According to the mode connecting a part for described surface coils conductor for described 1st ceramic green sheet and a part for the described surface coils conductor of described 2nd ceramic green sheet via described interlayer connection conductor, stacked multiple described ceramic green sheet, and carry out the operation that crimps.
8. the manufacture method of multilayer ceramic electronic component according to claim 6, wherein,
The operation preparing described ceramic green sheet comprises the operation of preparation the 3rd ceramic green sheet, and described 3rd ceramic green sheet is only provided with the layer interior loop conductor of the inside being positioned at ceramic green sheet in the scope of the thickness being no more than 1 ceramic green sheet as described coil-conductor,
The operation making described unsintered article body comprises the mode according to connecting a part for described layer interior loop conductor for described 1st ceramic green sheet and a part for the described layer interior loop conductor of described 3rd ceramic green sheet, stacked multiple described ceramic green sheet, and carry out the operation that crimps.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010-145796 | 2010-06-28 | ||
| JP2010145796 | 2010-06-28 | ||
| PCT/JP2011/063331 WO2012002133A1 (en) | 2010-06-28 | 2011-06-10 | Multilayer ceramic electronic component and method for producing same |
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| Publication Number | Publication Date |
|---|---|
| CN102971809A CN102971809A (en) | 2013-03-13 |
| CN102971809B true CN102971809B (en) | 2016-02-17 |
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| WO2015002115A1 (en) * | 2013-07-01 | 2015-01-08 | 株式会社 村田製作所 | Stacked inductor element and manufacturing method for same |
| WO2015178061A1 (en) * | 2014-05-21 | 2015-11-26 | 株式会社 村田製作所 | Circuit module |
| CN105336842B (en) * | 2014-07-29 | 2019-03-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| JP6575198B2 (en) * | 2015-07-24 | 2019-09-18 | Tdk株式会社 | Multilayer coil parts |
| CN209949596U (en) | 2016-05-19 | 2020-01-14 | 株式会社村田制作所 | Multilayer substrate |
| JP6477608B2 (en) * | 2016-06-16 | 2019-03-06 | 株式会社村田製作所 | Electronic components |
| JP6635054B2 (en) * | 2017-01-06 | 2020-01-22 | 株式会社村田製作所 | Resistance element and method of manufacturing the same |
| KR101987213B1 (en) * | 2017-09-20 | 2019-06-10 | 삼성전기주식회사 | Coil component and manufacturing method for the same |
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| CN101040354A (en) * | 2004-10-18 | 2007-09-19 | 株式会社村田制作所 | Method for manufacturing monolithic ceramic electronic component, and multilayer composite |
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| JPS5810810A (en) | 1981-07-13 | 1983-01-21 | Tdk Corp | Manufacture of laminated inductor |
| JP2655657B2 (en) * | 1987-12-08 | 1997-09-24 | ティーディーケイ株式会社 | Structure of laminated application parts |
| JPH1012455A (en) * | 1996-06-24 | 1998-01-16 | Tdk Corp | Lamination type coil component and its manufacture |
| JP2001313211A (en) * | 2000-04-28 | 2001-11-09 | Toko Inc | Laminated electronic part |
| US6537671B2 (en) * | 2000-12-05 | 2003-03-25 | Alpha Coating Technologies, Llc | Coating powders having enhanced electrostatic chargeability |
| JP4573498B2 (en) * | 2002-12-02 | 2010-11-04 | 富士電機システムズ株式会社 | Ultra-compact power converter |
| JP3800555B2 (en) * | 2003-04-24 | 2006-07-26 | 松下電器産業株式会社 | High frequency circuit |
| JP4211591B2 (en) * | 2003-12-05 | 2009-01-21 | 株式会社村田製作所 | Method for manufacturing multilayer electronic component and multilayer electronic component |
| JP4213679B2 (en) * | 2005-03-18 | 2009-01-21 | Ｔｄｋ株式会社 | Multilayer inductor |
| US7994889B2 (en) * | 2006-06-01 | 2011-08-09 | Taiyo Yuden Co., Ltd. | Multilayer inductor |
| JPWO2009016937A1 (en) * | 2007-07-30 | 2010-10-14 | 株式会社村田製作所 | Chip coil parts |
| KR101282143B1 (en) * | 2008-10-30 | 2013-07-04 | 가부시키가이샤 무라타 세이사쿠쇼 | Electronic part |
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| CN102971809A (en) | 2013-03-13 |
| WO2012002133A1 (en) | 2012-01-05 |
| JPWO2012002133A1 (en) | 2013-08-22 |
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| US20130113595A1 (en) | 2013-05-09 |
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