CN102971719B - Memorizer is read or method, equipment and the assembly of write - Google Patents

Abstract

In order to improve the efficiency running application, determine and use caching (140) or directly use storage (150) to be specific for (131) more efficiently, block size ground；And the type of memory determined is used for the data stream with corresponding blocks size.

Description

Memorizer is read or method, equipment and the assembly of write

Technical field

The present invention relates to storage or the retrieval of data, and especially, relate to the data stream reading and/or writing for application.

Background technology

The speed of application that run on computers, that performed by one or more processors is mainly determined by the following: the access speed to information to be processed, and treated information can be with stored speed before processing further or inputting at needs.

Use in computer systems and there is different qualities, particularly friction speed, thus there is the different memory type of different price.Further, the different bus used between memorizer and the processor running application, and it is connected to component influences reading and/or the writing speed of bus.Further, the feature of memorizer is in evolution, and the memorizer in a computer or used by computer can be updated to faster memorizer.Basic division between memorizer is: memorizer is caching, and it is used as the buffer storage of the high speed storing for the instruction and data being accessed frequently；Or memorizer is so-called main storage or storage.Basically there exist two kinds of memory I/O(i.e., write/read) operation: directly access storage or use all data stream to be delivered to main storage and/or autonomous memory transmits the caching passed through.Currently used caching is default solution.But, the most directly accessing storage can more efficiently and have less expense.

WO 2008/004149 discloses solution, and the part of the flash memory being wherein used as storage is allocated to the buffering with the remainder acting on flash memory, to minimize the abrasion of time overhead and flash memory.In this solution, all writes and read requests are through Memory Controller.When Memory Controller receives in time being written into the data stream of memorizer, the size of received data stream is compared by it with the packet of predetermined number, if and this data stream is more than the packet of predetermined number, then this data stream is directly stored its target destination, otherwise this data stream is stored in buffer portion to be stored in target destination after a while and to be read from buffer portion, as long as this data stream is at buffer portion.When the data from buffer portion are stored, and exist have identical destination more than a blocks of data time, only store a up-to-date blocks of data.

Solution in WO 2008/004149 still occurs in storage, and the data to Memory Controller with from Memory Controller flow through and transmitted by caching, may be more efficiently although directly accessing flash memory.

Summary of the invention

The following simplified summary describing the present invention, with provide to the present invention some in terms of basic comprehension.This summary of the invention is not the general overview of the present invention.Its key/decisive element being not intended to identify the present invention or detailed description the scope of the present invention.Its sole purpose is to introduce some designs of the present invention in schematic form, as the preamble in greater detail introduced after a while.

The aspect of some embodiments includes information based on the block size about data stream and for the caching of determination of this block size and storage performance, judges use caching or directly use storage, and correspondingly takes action.

Various aspects of the invention are included in the method defined in independent claims, equipment and computer program.It is disclosed in the dependent claims further embodiment of the present invention.

Accompanying drawing explanation

Below, different embodiment will be described in greater detail with reference to the attached drawings, in the accompanying drawings:

Fig. 1 is the simplified block diagram according to embodiment；And

Fig. 2 to 4 is the flow chart of diagram embodiment.

Detailed description of the invention

Now the most hereinafter, the exemplary embodiment of the present invention will be described more fully hereinafter with reference to the accompanying drawings, illustrated therein is some and the not all embodiments of the present invention.It practice, the present invention can implement in many different forms, and should not be construed as being limited to the embodiment illustrated in this article；On the contrary, it is provided that these embodiments so that the disclosure will meet the legal requirement being suitable for.Although this specification may refer to " one " or " some " embodiments in some positions, but, this not necessarily means each such quoting and is only applied to single embodiment for identical (one or more) embodiment or feature.Can also be combined to provide other embodiments to the single feature of different embodiments.

Embodiments of the invention are suitable to calculating equipment, computer, corresponding assembly and/or support to use any calculating system or the network of caching.Calculating equipment can include any kind of processor, operating system and one or more memorizer.Therefore, all words and expression by broad interpretation, and should be intended to illustrative not limiting embodiment.

Illustrate the general layout of the equipment that calculates according to embodiment in FIG.Fig. 1 is the simplified block diagram of some assemblies only illustrating calculating equipment, and this assembly is used to embodiment is described.It should be appreciated that calculating equipment can include need not being described in detail here other assemblies, module, connect, coupling etc..

The calculating equipment 100 describing computing environment includes running application 120 and being coupled to judge the processor 110 of assembly 130 via bus 101.Judge assembly 130, and thus processor and application, be further coupled to cache 140 and be further coupled to store 150 via bus 103 via bus 102.Such as, it is achieved the calculating equipment 100 below with the function judging assembly 130 of embodiment description not only includes prior-art devices, and includes for judging it is to use caching or the direct device using storage.More accurately, calculating equipment includes the device of the function utilizing embodiment to describe for realization, and can include that separate device or device for each separate function may be configured to perform two or more functions, and the function of even combination difference embodiment.

Generally, processor 110 is CPU (CPU), but processor can be other operation processor.It should be appreciated that calculating equipment can include other assemblies, and/or caching and storage may be located at via in interface another calculating equipment addressable.

Judge that assembly 130 is configured to the function performing to describe below with embodiment, and it may be configured to perform the function from different embodiments.For this purpose, it is determined that assembly can include a small amount of memorizer for storing critical table 131, and depends on embodiment, and be connected to processor 110 or self include the processor (not shown in figure 1) for performing function.Further, it is determined that assembly can include other unit, and, it such as includes for receiving and transferring control information, data and write or the distinct interface of read requests.

Judgement assembly according to embodiment typically can be attached to internal storage and the controller of various interfaces of equipment, control unit, microcontroller etc..Judge that assembly can be configured to microprocessor, such as single-chip microcomputer element or as chipset or at least include for providing the memorizer of the memory area for arithmetical operation and for performing the plate of the arithmetic processor of arithmetical operation.Judge that assembly can include one or more computer processor, special IC (ASIC), digital signal processor (DSP), digital signal processor (DSPD), PLD (PLD), field programmable gate array (FPGA) and/or be programmed that other nextport hardware component NextPorts for the mode of one or more functions performing one or more embodiments.Embodiment will judge that assembly is provided as on any calculating device distribution/data storage medium the computer program implemented, it programmed instruction including constituting identifying unit when being loaded into equipment.Program, also referred to as program product, including software routines, constitute the usability of program fragments of " program library ", applet (applet) and grand, and this program can be stored in any medium, and can be downloaded in calculating equipment.

Caching 140 and storage 150 can be volatibility and/or nonvolatile memory, and they can be different types of.Such as, caching and/or store and can store computer program code, such as software application or operating system, information, data, content etc. perform the step being associated with the operation applying 120 for CPU or alignment processing device.Caching and/or storage can be such as random access memory, hard disk, flash memory, solid-state memory (SSD) or other fixed data memorizeies or storage device.Further, cache and/or store or its (they) part can be removably connected to the removable memorizer of equipment.

Bus 102 and bus 103 can be any kind of buses transferring any type of data between the components, and they can be different types of.Bus can be being to carry the parallel bus of data on multiple lines parallel or carry the universal serial bus of data in Bits Serial mode or use parallel and Bits Serial to connect both buses.Therefore, bus 102 and bus 103 can be any physical layout, comprise and provide the different of transmission of data to connect and assembly.

Although the most calculating equipment being depicted as an entity, however, it is possible to realize memorizer with one or more physically or logically entities.For example, it is possible to be embodied as caching and/or storage storing device across distributed (the sharing) of multiple calculating equipment, and bus calculating device interior or can transmit data between computing devices.Unit and function can be software and/or software-hardware and/or fastener components (can not be recorded with eliminating and implement on the medium of such as read only memory or in hardwired computer circuit).

Fig. 2 diagram is according to the function judging assembly of embodiment.In this embodiment, it is determined that assembly determines use caching by measuring specific block size or is directly stored in storage more efficiently, i.e. which in storage class is type more efficiently.Block size can be such as 512,1,2,4 ..., 1024kB.(block is write and/or the unit read).

In this embodiment, it is determined that assembly performs following step respectively for reading (input) and write (output).It should be appreciated that they can be performed and/or sequentially executed according to another in addition to following order the most simultaneously.In another embodiment, it is determined that assembly is only used for reading or writing and perform following step, then it is used for result reading and both write.But, owing to reading and write are separate tasks, the overall performance for reading and perform both write steps with I/O is the advantage of obtainable full blast in calculating equipment.

In the example shown in the series of figures, for clarity, it is assumed that the time reading (or write) is used as decision factor to judge which is more efficiently.But, the content as decision factor is not restricted, and it can be the combination of different factor.Such as, it is determined that factor relevant with the processor resource using such as cpu resource (less cpu resource is used for same amount of work or same amount of cpu resource and performs more work by more efficient way) or decision factor can consider that time and processor resource use both.Further, the reading of calculating equipment and/or the application of write operation is used can to have the demand affecting decision factor.In an embodiment, for example, it is possible to give, by providing a user with selective listing, the chance that user selects decision factor, the selection of user is then used.

Judge that assembly obtains the first block size (step 201), in step 202., read this amount from caching, measure its time spent simultaneously.Then, in step 203, directly read equal amount from storage, and measure its time spent.Then, in step 204, it is determined that Unit selection type of memory more efficiently, the fastest one, and in step 205, type of memory is associated for reading with this block size.Then, in step 206, check whether that all block sizes are all associated with type of memory.If it is not, then judge that assembly performs foregoing for next block, continue the most in step 201.If all block sizes are all associated with type of memory, then they are ready for (step 207) and read (input).

In this embodiment, previous step is then repeated for write.In other words, substitute and read, in step 202 and 203, perform write.Then, result can be to have to be respectively used to reading and the critical table of the type of memory selection specific to block size for write, is used for the type of memory of reading and is used for the identical or different, as illustrated in fig. 1 of write.

The advantage of this embodiment is when determining type of memory to be used, considers all component, different bus etc. according to its actual functional capability.This has further advantage: minimizes the load of processor, thus generates less heat, and needs less energy.

In further embodiment of the present invention, substitute the measurement performing such as to measure the time, judge that assembly obtains systematic parameter, such as memorizer is (i.e., caching and storage) size, presently, there are how many available memories, bus speed, and use the information to calculate type of memory more efficiently (via buffer memory or directly storage) into each block size.

In a further embodiment, it is determined that assembly is configured to not only measure but also calculate, and by measurement result and comparison of computational results hardware is verified.Offered the advantage that by checking hardware: it helps the fault that detection is possible, consequently facilitating carried out fault correction before any more major break down occurs.

Measurement/calculating described above can be when turning on the power, with specific interval and/or when there is such as operating system online updating in calculating equipment, driving renewal, cache management software upgrading, the hardware installing new memory plate etc. or software to perform when changing.

In another embodiment, when every secondary data stream starts, the block size used by this data stream is performed measurement/calculating.

Fig. 3 illustrates in step 301, it is determined that assembly receives the instruction of the block size of data stream and is to be read about data stream or the situation of the information of write.Then, in step 302, it is determined that assembly uses the instruction received to come from the table acquired value created, such as, as above with described in Fig. 2, this value is " caching " or " storage ".If the block size received is not in the block size of test, i.e. it does not have the type of memory of associated, then depend on embodiment, and it is rounded up to next block size up or down or uses immediate block size.Then, in step 303, the type of memory of acquisition is used for this data stream.Such as, if this data stream to be written into, then depend on which step 302 obtains, by this data stream from judging that assembly is transferred to caching or storage.

Above content be also applied to data stream block size instruction and to be read about data stream or write information through judgement assembly, but actual data stream without judge assembly embodiment.

Judge that assembly can be transparent to application.But, Fig. 4 illustrates embodiment, wherein after block size associates for read/write with corresponding type of memory, in step 401, it is determined that assembly determines optimical block size, and in step 402, notices this optimical block size to application.By using the measurement obtained during the process utilizing Fig. 2 to describe and/or result of calculation preferably to determine optimical block size, and this is most preferably the block size providing best total result (for example, it is desirable to speed or top performance).Therefore, embodiment provides dynamic optimum to be advertised, and this value is by considering that computing environment and measurement and/or calculating to the change that it is made obtain.Noticing such value and improve efficiency, this is for rarely found during the value of the hard coded notice of prior art, and the value that the hard coded of the prior art is noticed, by the estimation made based on developer, is i.e. the preferably conjecture of developer when it is typically hard coded.

Above-mentioned steps in Fig. 2 is to 4 and correlation function do not have an absolute time order, and can simultaneously or according to provide order different and perform some in this step.For example, it is possible to (step 201 and 206) perform to read and write measurement (step 202-205) for a block size before obtaining another block size.Can also between the steps or in step, perform other functions.Some in step or the part in step can also be omitted.Such as, read and/or the application of write data can ask the control of himself to read and/or write, in this case, although data stream can be via judging component passes, but, it is determined that component responds, in this request, does not obtain type of memory to be used, i.e., then, skip step 302 and 303.Further, some in step or the part in step can also be integrated together or by the part replacement of corresponding step or step.Such as, substitute and measure time or in addition in step 202 and 203, the use of CPU can be measured.

To those skilled in the art it should be apparent that along with technology develops, inventive concept can be realized in every way.The present invention and embodiment are not limited to above-mentioned example, but can change within the scope of the claims.

Claims (13)

1., for a method for computing environment, described method includes:

By using the one or more decision factor from decision factor group, at described calculating ring Border determines for block size use caching and directly use in storage any be more efficiently Mode, described group includes: read have described block size block spend time, write institute State time that block spends, the usage amount of processor resource for reading described piece, for writing The usage amount of the processor resource of described piece；And

In response to having the data stream of described block size, will determined by more efficient way use In described block size.

Method the most according to claim 1, wherein said determine farther include:

Specific block size is measured use caching and directly use in storage any be described More efficient way；

For the more efficient way described in the selection of each block size measured；And

Described block size is associated with selected mode.

Method the most according to claim 1, wherein said determine farther include:

Obtaining the systematic parameter of described computing environment, acquired systematic parameter affects memorizer to be made Efficiency；

By the systematic parameter acquired in using, specific block size is calculated and uses caching and straight Connect use storage in any be described more efficient way；

For the more efficient way described in the selection of each block size calculated；And

Described block size is associated with selected mode.

Method the most according to claim 2, farther includes:

Obtaining the systematic parameter of described computing environment, acquired systematic parameter affects memorizer to be made Efficiency；

By the systematic parameter acquired in use, described specific block size is calculated and uses caching With the efficiency directly using storage；

Corresponding measurement result and result of calculation are compared to checking in described computing environment Hardware.

The most according to the method in claim 2 or 3, farther include:

Based on to perform the measurement result of described selection, determine optimical block size；And

Described optimical block size is noticed to application.

6., according to the method described in any one in claim 1,2 or 3, wrap further Include: perform the step in corresponding claims respectively for reading and writing.

7., for an equipment for computing environment, described equipment includes

For determining use caching for block size in described computing environment and directly using storage In any be the device of more efficient way, the described device for determining is configured to Using the one or more decision factor from decision factor group, described group includes: reads and has Time that the block of described block size spends, write described piece of time spent, described for reading The usage amount of the processor resource of block and the usage amount of the processor resource for writing described piece； And

For in response to having the data stream of described block size, by determined by side more efficiently Formula is for the device of described block size.

Equipment the most according to claim 7, described equipment farther include described caching, The assembly that described storage and data stream are flowed through, described assembly at least includes: for based on for Described caching or described storage are used for described piece greatly by the described more efficient way of block size Little device.

9., for a computer module for computing environment, described computer module is configured to:

By the one or more decision factor in measuring following group, right in described computing environment In specific block size measure use caching and directly use in storage any be for block size More efficient way, described group include reading there is the block of described block size and spend time, Write the described piece of time spent, for the usage amount of processor resource, the use that read described piece Usage amount in the processor resource of described piece of write；

Based on to described caching and the measurement result of directly use described storage acquisition, for each The more efficient way described in block size selection of individual measurement；

Described block size is associated with selected mode；And

In response to having the data stream of described block size, will determined by more efficient way use In described block size.

Computer module the most according to claim 9, is further configured to: respectively Measure for reading with write, select, associate and use.

11., according to the computer module described in claim 9 or 10, are further configured to:

Obtaining the systematic parameter of described computing environment, acquired systematic parameter affects memorizer to be made Efficiency；

By the systematic parameter acquired in use, described specific block size is calculated and uses caching With the efficiency directly using storage；

Corresponding measurement result and result of calculation are compared to checking in described computing environment Hardware.

12., according to the computer module described in claim 9 or 10, are further configured to:

Receive the information of the block size about data stream；

Determine the block size which block size of described data stream measured corresponding to；And

Associated mode is used for described data stream.

13. according to the computer module described in claim 9 or 10, described computer module are Controller, control unit, microcontroller, single-chip microcomputer element, chipset or at least include for There is provided the memorizer of the memory area for arithmetical operation and for performing at the computing of arithmetical operation The plate of reason device.