CN102957545A - Method and device for maintaining synchronous network clocks - Google Patents
Method and device for maintaining synchronous network clocks Download PDFInfo
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- CN102957545A CN102957545A CN2011102359176A CN201110235917A CN102957545A CN 102957545 A CN102957545 A CN 102957545A CN 2011102359176 A CN2011102359176 A CN 2011102359176A CN 201110235917 A CN201110235917 A CN 201110235917A CN 102957545 A CN102957545 A CN 102957545A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0647—Synchronisation among TDM nodes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/14—Monitoring arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/10—Active monitoring, e.g. heartbeat, ping or trace-route
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Abstract
The invention discloses a method and a device for maintaining synchronous network clocks. The method includes sending search requests to clock units of all devices in a network at a set time; receiving operation state data from each clock unit; and sequentially judging whether the clock units are abnormal or not according to the received operation state data. By the method and the device for maintaining the synchronous network clocks, conditions of clock performance of the clock units in all the devices in the network can be monitored effectively, and network maintenance staff can be informed to handle before the conditions of the clock performance deteriorate to damage a business. In addition, the method and the device are simple to implement, the clock performance of the clock units is only detected by existing input clock signals without adding an extra device, and accordingly maintenance of the synchronous network clocks is enhanced effectively.
Description
Technical field
The present invention relates to the communications field, in particular to a kind of maintaining method and device of synchronous network clock.
Background technology
In the synchronous network of needs; as: SDH (Synchronous Digital Hierarchy) (Synchronous Digital Hierarchy; referred to as SDH) field and the field that needs Network Synchronization; when network clocking exists in the unusual or disabled situation; can cause service damage, when serious even professional blocking-up can occur.So, need to protect network clocking.At present, the most general way is to use a plurality of clock units, if the clock unit abnormal of current use then switches to clock unit for subsequent use.
Find that by patent retrieval at present, the method for switching about a plurality of clock units is very many.Publication number CN1838586, realize method and the device of clock active/standby changeover error-free, the method that realizes that two clock units are switched has been described, to reduce impact and the publication number CN101183928 on output clock, clock switch method, clock switch unit, clock apparatus and system have also described and have switched to realize the processing method of switching by the first and second clock units.
But, unavailable about how judging whether clock unit has been deteriorated to its output clock, then there is not better method.Publication number CN101145800, whether a kind of reliable method and apparatus that switches of clock board that improves has wherein been described with the ready state of clock unit and has been come telltable clock normal.Yet ready state can't identify clock unit and whether be in asymptotic deterioration state.
Clock unit mainly is comprised of a phase-locked loop.Fig. 1 is the analog phase-locked look structural representation according to correlation technique.As shown in Figure 1, phase-locked loop is by phase discriminator (Phase detector, referred to as PD), loop filter (Loop filters is referred to as LF), voltage controlled oscillator (Voltage-controlled oscillators is referred to as VCO) form; Fig. 2 is the digital phase-locked loop structural representation according to correlation technique.As shown in Figure 2, phase-locked loop is comprised of PD, LF, digital controlled oscillator DCO.
The below describes the operation principle of phase-locked loop take Fig. 1 as example.Specific as follows: as to calculate the difference of the clock signal of input clock signal and VCO, by the control voltage of filtering adjustment VCO, make clock signal follow the tracks of upper input clock signal.Whole process is a degenerative automatic control flow chart.And when reality is used, the voltage controlled oscillator of clock unit is not continual and steady, it self can be undertaken deteriorated by its physical characteristic (such as temperature, service time etc.), when enough long or operational environment changes (such as supply power voltage) when running time, phase-locked loop can't be followed the tracks of input clock signal, cause using the equipment generation service damage of clock unit clock signal.
Therefore, when the phase-locked loop of clock unit goes wrong, can't be confirmed to be by input clock signal and cause, or caused by clock unit.If additionally provide the individual character can better clock signal to clock unit, can greatly increase again the cost of the network equipment.
Summary of the invention
For in the correlation technique when the phase-locked loop of clock unit goes wrong, can't be confirmed to be and to be caused by input clock signal, still the problem that is caused by clock unit, main purpose of the present invention is to provide a kind of maintaining method and device of synchronous network clock, one of to address the above problem at least.
A kind of maintaining method of synchronous network clock is provided according to an aspect of the present invention.
Maintaining method according to synchronous network clock of the present invention comprises: regularly the clock unit of all devices sends query requests in the network; Reception comes from the running state data of each clock unit; Judge successively whether abnormal of clock unit according to the running state data that receives.
Above-mentioned running state data comprises: the current running status of the phase-locked loop of described clock unit and the continuous working period of described current running status; Described clock unit overall operation state; The timing reference input source-information; The assessment result of described clock unit clock performance.
Judging successively according to the described running state data that receives whether abnormal comprises described clock unit: physical connection topological relation and described timing reference input source-information according to pre-stored described equipment are set up the network time clock tracking relation; In described network time clock tracking relation, judge successively whether abnormal of described clock unit according to the flow direction of clock signal.
Judging that successively described clock unit whether after the abnormal, also comprises: when having the clock unit of abnormal in determining network, stop unusually to judge and sending alarm.
Judging that successively described clock unit whether after the abnormal, also comprises: the output judged result.
A kind of attending device of synchronous network clock is provided according to a further aspect in the invention.
Attending device according to synchronous network clock of the present invention comprises: sending module is used for timing to the clock unit transmission query requests of network all devices; Receiver module is for the running state data that comes from each described clock unit; Judge module is used for judging successively whether abnormal of described clock unit according to the described running state data that receives.
Above-mentioned running state data comprises: the current running status of the phase-locked loop of described clock unit and the continuous working period of described current running status; Described clock unit overall operation state; The timing reference input source-information; The assessment result of described clock unit clock performance.
Above-mentioned judge module comprises: set up the unit, be used for setting up the network time clock tracking relation according to pre-stored physical connection topological relation and described timing reference input source-information; Judging unit is used for judging successively whether abnormal of described clock unit in described network time clock tracking relation according to the flow direction of clock signal.
Said apparatus also comprises: alarm module is used for stopping unusually to judge and sending alarm when there is the clock unit of abnormal in definite network.
Said apparatus also comprises: output module is used for the output judged result.
By the present invention, adopt regularly that the clock unit of all devices sends query requests in the network; Reception comes from the running state data of each clock unit; Judge successively whether abnormal of clock unit according to the running state data that receives, solved in the correlation technique when the phase-locked loop abnormal of clock unit, can't be confirmed to be and to be caused by input clock signal, still the problem that is caused by clock unit, and then reached the clock performance situation of the clock unit of all devices in the effective monitor network, before it is deteriorated to the damage business, can the informing network attendant process; Simultaneously, the present invention realizes simply, only detects the clock performance of clock unit with existing input clock signal, and does not need to increase extra device, has effectively strengthened the effect of synchronous network clock maintainability.
Description of drawings
Accompanying drawing described herein is used to provide a further understanding of the present invention, consists of the application's a part, and illustrative examples of the present invention and explanation thereof are used for explaining the present invention, do not consist of improper restriction of the present invention.In the accompanying drawings:
Fig. 1 is the analog phase-locked look structural representation according to correlation technique;
Fig. 2 is the digital phase-locked loop structural representation according to correlation technique;
Fig. 3 is the maintaining method flow chart according to the synchronous network clock of the embodiment of the invention;
Fig. 4 is the network physical link topological relation schematic diagram according to the embodiment of the invention;
Fig. 5 is that the network time clock tracking according to the embodiment of the invention concerns schematic diagram;
Fig. 6 is the attending device according to the synchronous network clock of the embodiment of the invention;
Fig. 7 is the attending device of synchronous network clock according to the preferred embodiment of the invention;
Fig. 8 is the attending device of synchronous network clock according to the preferred embodiment of the invention.
Embodiment
Hereinafter also describe in conjunction with the embodiments the present invention in detail with reference to accompanying drawing.Need to prove that in the situation of not conflicting, embodiment and the feature among the embodiment among the application can make up mutually.
Fig. 3 is the maintaining method flow chart according to the synchronous network clock of the embodiment of the invention.As shown in Figure 3, the method comprises following processing:
Step S302: regularly the clock unit of all devices sends query requests in the network;
Step S304: receive the running state data that comes from each clock unit;
Step S306: judge successively whether abnormal of clock unit according to the running state data that receives.
In the correlation technique, when the phase-locked loop abnormal of clock unit, can't be confirmed to be by input clock signal and cause, or the problem that is caused by clock unit.In the maintaining method of synchronous network clock shown in Figure 3, adopt regularly that the clock unit of all devices sends query requests in the network; Reception comes from the running state data of each clock unit; Judge successively whether abnormal of clock unit according to the running state data that receives, solved in the correlation technique when the phase-locked loop abnormal of clock unit, can't be confirmed to be and to be caused by input clock signal, still the problem that is caused by clock unit, and then reached the clock performance situation of the clock unit of all devices in the effective monitor network, before it is deteriorated to the damage business, can the informing network attendant process; Simultaneously, the present invention realizes simply, only detects the clock performance of clock unit with existing input clock signal, and does not need to increase extra device, has effectively strengthened the effect of synchronous network clock maintainability.
Need to prove that the concrete operations of each step can be carried out by arbitrary network equipment of network management side in the said method.
In concrete implementation process, the running state data among above-mentioned steps S304 and the step S306 can include but not limited to:
(1) the current running status of the phase-locked loop of clock unit: i.e. self-oscillating regime, lock-out state, hold mode, trap state etc., the phase-locked loop operation state of this state indication present clock unit, the relation between expression local clock and input clock;
(2) continuous working period of current running status: under trap state, if time remaining is long, represent that then local clock may have problems;
(3) clock unit overall operation state: namely, the state that the non-phase-locked loop of clock unit is relevant is usually with normal or unusual expression;
(4) timing reference input source-information: the expression input clock enters into equipment from which clock interface, and by the physical link of this interface, the input clock that just can determine equipment is from other certain concrete equipment;
(5) assessment result of clock unit clock performance: when the clock unit is under self-vibration or the hold mode, may not have input clock signal, the Performance Evaluation result of this moment is invalid; When the clock unit is under seizure or the lock-out state, there is input clock signal, at this moment, phase-locked loop to different implementation methods, take input clock as reference signal, (Field Programmable Gata Array is referred to as FPGA) calculates clock performance by field programmable gate array.
The below does to describe further to the assessment result of above-mentioned clock unit clock performance according to the phase-locked loop (being DPLL digital phase-locked loop and simulaed phase locked loop) of different implementation methods:
In synchronizing network is used, the high grade of the clock performance of reference clock Performance Ratio clock unit, in the SDH network, reference clock generally adopts Building Integrated Timing Supply BITS (Building Integrate Timing System) source, its performance satisfy at least be applicable to the Synchronization Network nodal clock require (ITU-TG.812) from clock timing, and the clock unit clock, its performance satisfy synchronizing digital hierarchy equipment operation applicable from clock timing characteristic (ITU-TG.813), than the low grade of reference clock.Like this, the reference clock that is input to network is credible and normal all the time.
For simulaed phase locked loop, referring to aforementioned shown in Figure 1, phase-locked loop changes its output frequency by voltage control voltage controlled oscillator (being oscillator), the output frequency of its voltage controlled oscillator-voltage control curve chart can be measured before it is not completely deteriorated.When input clock signal normal, clock unit phase-locked loop locking, the scope of the control voltage of oscillator can precompute according to output frequency-voltage control curve chart.When oscillator was deteriorated, then output frequency-voltage control curve chart will produce great changes, and under identical normal input clock signal, its control voltage will be unusual so.This information can be for assessment of the degradation of oscillator.
For DPLL digital phase-locked loop, referring to aforementioned shown in Figure 2, its phase-locked loop makes its output clock follow the tracks of upper input clock by control digital controlled oscillator (Digital-controlled oscillators is referred to as DCO).To digital controlled oscillator, need a reference clock, general from the oscillator on the clock unit, along with the variation of operational environment and time, oscillator is always deteriorated.So by on-site programmable gate array FPGA, take input clock as reference, measure the relative frequency skew of the reference clock that offers DCO, these data can be for assessment of the degradation of oscillator.
Preferably, in said method, judge successively whether abnormal of clock unit according to the running state data that receives, further comprising following processing:
Step 1: physical connection topological relation and described timing reference input source-information according to pre-stored described equipment are set up the network time clock tracking relation; For example, can concern for tree structure.
Step 2: in described network time clock tracking relation, judge successively whether abnormal (being to analyze successively whether abnormal of described clock unit by tree root to leaf in the tree structure) of described clock unit according to the flow direction of clock signal.
Example below in conjunction with Fig. 4 and Fig. 5 further describes above-mentioned preferred implementation.
Fig. 4 is the network physical link topological relation schematic diagram according to the embodiment of the invention.As shown in Figure 4, the network equipment of network management side can form network physical link topological relation according to the link situation of the all-network equipment of network user's side in the existing network, then is stored in the middle of the network equipment of network management side.Certainly, the storage mode of network physical link topological relation is not limited to the form of employing figure, can also adopt other mode to store (as, form).
Fig. 5 is that the network time clock tracking according to the embodiment of the invention concerns schematic diagram.The network equipment of as shown in Figure 5, network management side is set up the network time clock tracking relation according to physical connection topological relation and the timing reference input source-information of pre-stored equipment.This network time clock tracking graph of a relation is being seen in shape, is a tree structure, from the tree root to the leaf, judges successively whether abnormal of clock unit according to the flow direction of clock signal in network time clock tracking relation.By the operation in tandem from the tree root to the leaf, BITS is that network reference clock provides equipment, and the flow direction of arrow relation expression clock signal among the figure concerns that such as the arrow of equipment #2 and equipment #0 the input clock of the clock unit of indication equipment #2 is provided by equipment #0.Equipment #0 in elder generation's analysis chart assesses its data by predetermined method, if normal, represents that then its clock signal does not go wrong, and namely sends to equipment #1, and the clock signal of #2 is also normal; If have abnormal conditions to occur, then need stop to continue to providing the follow-up equipment of clock signal to analyze by equipment #0.
Preferably, judge successively that in step S306 clock unit is whether after the abnormal, can also comprise following processing: when in determining network, having the clock unit of abnormal, stop unusual judgement, to can't with the equipment of Network Synchronization, with the mode prompting maintenance personnel of alarm, such as equipment #Q, can't with Network Synchronization.
Preferably, judge successively clock unit whether after the abnormal in step S306, can also comprise following processing: the judged result that will analyze successively according to the method described above each equipment from the tree root to the leaf is exported to the attendant.
By being analyzed to the mode (being that the clock signal flows to) of leaf by tree root, can guarantee that if tree root offers the clock signal of leaf be normal, the clock unit of leaf equipment is exactly believable with the clock performance of this input clock signal assessment so, when so just having avoided phase-locked loop to go wrong, can't be confirmed to be because the problem of input clock or because obscuring of causing of the problem of clock unit self loop device.
Fig. 6 is the attending device according to the synchronous network clock of the embodiment of the invention.As shown in Figure 6, the attending device of synchronous network clock of the present invention comprises: sending module 10 is used for timing to the clock unit transmission query requests of network all devices; Receiver module 20 is for the running state data that comes from each clock unit; Judge module 30 is used for judging successively whether abnormal of clock unit according to the running state data that receives.
In the correlation technique, when the phase-locked loop abnormal of clock unit, can't be confirmed to be by input clock signal and cause, or the problem that is caused by clock unit.In the attending device of synchronous network clock shown in Figure 6, sending module 10 regularly in the network clock unit of all devices send query requests; Receiver module 20 receives the running state data that comes from each clock unit; Judge module 30 is judged whether abnormal of clock unit successively according to the running state data that receives, solved in the correlation technique when the phase-locked loop abnormal of clock unit, can't be confirmed to be and to be caused by input clock signal, still the problem that is caused by clock unit, and then reached the clock performance situation of the clock unit of all devices in the effective monitor network, before it is deteriorated to the damage business, can the informing network attendant process; Simultaneously, the present invention realizes simply, only detects the clock performance of clock unit with existing input clock signal, and does not need to increase extra device, has effectively strengthened the effect of synchronous network clock maintainability.
In concrete implementation process, the running state data that receiver module 20 receives includes but not limited to:
(1) the current running status of the phase-locked loop of clock unit: i.e. self-oscillating regime, lock-out state, hold mode, trap state etc., the phase-locked loop operation state of this state indication present clock unit, the relation between expression local clock and input clock;
(2) continuous working period of current running status: under trap state, if time remaining is long, represent that then local clock may have problems;
(3) clock unit overall operation state: namely, the state that the non-phase-locked loop of clock unit is relevant is usually with normal or unusual expression;
(4) timing reference input source-information: the expression input clock enters into equipment from which clock interface, and by the physical link of this interface, the input clock that just can determine equipment is from other certain concrete equipment;
(5) assessment result of clock unit clock performance: when the clock unit is under self-vibration or the hold mode, may not have input clock signal, the Performance Evaluation result of this moment is invalid; When the clock unit is under seizure or the lock-out state, there is input clock signal, at this moment, phase-locked loop to different implementation methods, take input clock as reference signal, (Field Programmable Gata Array is referred to as FPGA) calculates clock performance by field programmable gate array.
Fig. 7 is the attending device of synchronous network clock according to the preferred embodiment of the invention.As shown in Figure 7, the judge module 30 in said apparatus may further include: set up unit 300, be used for setting up the network time clock tracking relation according to pre-stored physical connection topological relation and timing reference input source-information; Judging unit 302 is used for judging successively whether abnormal of clock unit in the network time clock tracking relation according to the flow direction of clock signal.
Fig. 8 is the attending device of synchronous network clock according to the preferred embodiment of the invention.As shown in Figure 8, said apparatus also comprises: alarm module 40, be connected with judge module 30, and be used for when there is the clock unit of abnormal in definite network, stopping unusually to judge and sending alarm;
As shown in Figure 8, said apparatus also comprises: output module 50, be connected with judge module 30, and be used for judged result is exported to the network maintenance staff.
As can be seen from the above description, the present invention has realized following technique effect: the effective clock performance situation of the clock unit of all devices in the monitor network, before it is deteriorated to the damage business, can the informing network attendant process; Simultaneously, the present invention realizes simply, only detects the clock performance of clock unit with existing input clock signal, and does not need to increase extra device, has effectively strengthened the maintainability of synchronous network clock.
Obviously, those skilled in the art should be understood that, above-mentioned each module of the present invention or each step can realize with general calculation element, they can concentrate on the single calculation element, perhaps be distributed on the network that a plurality of calculation elements form, alternatively, they can be realized with the executable program code of calculation element, thereby, they can be stored in the storage device and be carried out by calculation element, and in some cases, can carry out step shown or that describe with the order that is different from herein, perhaps they are made into respectively each integrated circuit modules, perhaps a plurality of modules in them or step are made into the single integrated circuit module and realize.Like this, the present invention is not restricted to any specific hardware and software combination.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. the maintaining method of a synchronous network clock is characterized in that, comprising:
Regularly the clock unit of all devices sends query requests in the network;
Reception comes from the running state data of each described clock unit;
Judge successively whether abnormal of described clock unit according to the described running state data that receives.
2. method according to claim 1 is characterized in that, described running state data comprises:
The current running status of the phase-locked loop of described clock unit and the continuous working period of described current running status;
Described clock unit overall operation state;
The timing reference input source-information;
The assessment result of described clock unit clock performance.
3. method according to claim 2 is characterized in that, is judging successively according to the described running state data that receives whether abnormal comprises described clock unit:
Physical connection topological relation and described timing reference input source-information according to pre-stored described equipment are set up the network time clock tracking relation;
In described network time clock tracking relation, judge successively whether abnormal of described clock unit according to the flow direction of clock signal.
4. each described method in 3 according to claim 1 is characterized in that, is judging that successively described clock unit whether after the abnormal, also comprises:
When in determining network, having the clock unit of abnormal, stop unusually to judge and sending alarm.
5. each described method in 3 according to claim 1 is characterized in that, is judging that successively described clock unit whether after the abnormal, also comprises: the output judged result.
6. the attending device of a synchronous network clock is characterized in that, comprising:
Sending module is used for timing to the clock unit transmission query requests of network all devices;
Receiver module is for the running state data that comes from each described clock unit;
Judge module is used for judging successively whether abnormal of described clock unit according to the described running state data that receives.
7. device according to claim 6 is characterized in that, described running state data comprises:
The current running status of the phase-locked loop of described clock unit and the continuous working period of described current running status;
Described clock unit overall operation state;
The timing reference input source-information;
The assessment result of described clock unit clock performance.
8. device according to claim 7 is characterized in that, described judge module comprises:
Set up the unit, be used for setting up the network time clock tracking relation according to pre-stored physical connection topological relation and described timing reference input source-information;
Judging unit is used for judging successively whether abnormal of described clock unit in described network time clock tracking relation according to the flow direction of clock signal.
9. each described device in 8 according to claim 6 is characterized in that described device also comprises:
Alarm module is used for stopping unusually to judge and sending alarm when there is the clock unit of abnormal in definite network.
10. each described device in 8 according to claim 6, it is characterized in that described device also comprises: output module is used for the output judged result.
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| CN201110235917.6A CN102957545B (en) | 2011-08-17 | 2011-08-17 | The maintaining method and device of synchronous network clock |
| PCT/CN2012/079739 WO2013023538A1 (en) | 2011-08-17 | 2012-08-06 | Synchronization network clock maintenance method and device |
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| CN201110235917.6A CN102957545B (en) | 2011-08-17 | 2011-08-17 | The maintaining method and device of synchronous network clock |
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| CN105847049A (en) * | 2016-03-22 | 2016-08-10 | 飞亚达（集团）股份有限公司 | Local area time synchronization system and monitoring method thereof |
| WO2016161751A1 (en) * | 2015-04-08 | 2016-10-13 | 中兴通讯股份有限公司 | Configuration method and apparatus for synchronization network |
| WO2017211140A1 (en) * | 2016-06-06 | 2017-12-14 | 中兴通讯股份有限公司 | Method and apparatus for detecting clock/time of network device, and computer storage medium |
| CN109474442A (en) * | 2017-09-07 | 2019-03-15 | 中国移动通信有限公司研究院 | Log processing method, electronic equipment and storage medium |
| CN111181947A (en) * | 2019-12-25 | 2020-05-19 | 航天信息股份有限公司 | Clock equipment state management device and method |
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