CN102957492B - Method and device for locking 64B/67B coding boundary - Google Patents
Method and device for locking 64B/67B coding boundary Download PDFInfo
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- CN102957492B CN102957492B CN201110237692.8A CN201110237692A CN102957492B CN 102957492 B CN102957492 B CN 102957492B CN 201110237692 A CN201110237692 A CN 201110237692A CN 102957492 B CN102957492 B CN 102957492B
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Abstract
The invention provides a method for locking a 64B/67B coding boundary. The method includes steps of offsetting a first shift register with a 99-bit width to a high order by 32 bits in each clock cycle, and inputting first 32-bit data to a low-order 32-bit position of the first shift register; controlling the interval of the clock cycles and extracting the offset quantity, so that when the interval is N clock cycles and the data in the first shift register exceeds 67-bit, extracting second 67-bit data from the first shift register, wherein N is a positive integer and the continuously extracted second data for twice is coherent; storing the second 67-bit data which are extracted from the first shift register twice in a second shift register with a 134-bit width; and determining an initial extracting address, starting from the initial extracting address to extract third 67-bit data in the second shift register, and locking a boundary of the third data. The method has the advantages that the 32-bit data which are inputted continuously are recovered into the effective 67-bit data meeting 64B/67B coding requirements, the conversion speed is high, and logic control units are simple.
Description
Technical field
The present invention relates to Ethernet art, particularly relate to one and realize 64B/67B encoded boundary locking means and device based on continuous 32 Bit datas inputs.
Background technology
At present, huge application demand has promoted the fast development of the communication technology, and traffic rate also increases thereupon, in order to improve the characteristic that online data is transmitted, communication bus of new generation adopts serial data transmission, employs 8B/10B, the coded systems such as 64B/66B, 64B/67B transmit data.
Wherein 64B/67B coding method is the Data Control head increasing by 3 bits on the basis of 64 Bit datas, the Data Control head of highest order has reversed nature, can come originally makeing mistakes in a passage or revise close to the position of makeing mistakes, tighter control DC balance, improve the reliability that data are transmitted in system, network bandwidth utilization factor is high simultaneously, is used more and more widely in existing data communication network chip.
Usually, in interface circuit design, first need high-speed differential serial signal between plate to be converted into the 67 bit valid data meeting 64B/67B coding requirement, parse real data to be supplied to 64B/67B decoder.But in prior art, the high-speed differential serial signal received can not be converted into parallel 67 bit bit wide data by serial receiver, can only be converted into the data of fixing bit wide, as 32 bit bit wides.Due to 32 bits and 67 bits can not pact, be difficult to 32 bits input data integral multiples to be combined into 67 Bit datas and to export.
Summary of the invention
The object of the present invention is to provide a small amount of logic of a kind of use, realize the method 32 Bit datas inputted continuously being reverted to the 67 bit valid data meeting 64B/67B coding requirement.
Another object of the present invention is to a kind of device realizing 32 Bit datas inputted continuously to revert to the 67 bit valid data meeting 64B/67B coding requirement, the method described in described application of installation is to realize the object of the invention.
Correspondingly, the method realizing the locking of 64B/67B encoded boundary of one embodiment of the present invention, comprises the following steps:
S1, in each clock cycle, the first shift register of one 99 bit bit wides is offset 32 bits to a high position, and the first data of low level 32 bit input one 32 bits to described first shift register;
S2, control clock cycle interval and extraction side-play amount, extract the second data of 67 bits from described first shift register;
S3, the second data of double extraction are stored in the second shift register of one 134 bit bit wides;
S4, determine initial extraction address, from described initial extraction address, from described second shift register, extract the 3rd data of 67 bits, and lock the border of described 3rd data.
As a further improvement on the present invention, described step S2 specifically comprises the steps:
S21, setting clock cycle are spaced apart 2 clock cycle, often extract once described second data, and extracting side-play amount increases by 3 bits, extract side-play amount and are increased to 30 bits from 0 bit;
S22, setting clock cycle are spaced apart 2 clock cycle, often extract once described second data, and extracting side-play amount increases by 3 bits, extract side-play amount and are increased to 31 bits from 1 bit;
S23, setting clock cycle are spaced apart 2 clock cycle, often extract once described second data, and extracting side-play amount increases by 3 bits, extract side-play amount and are increased to 29 bits from 2 bits.
As a further improvement on the present invention, after described step S1 completes, 3 clock cycle of interval start to perform described step S2, and after described step S2 completes, 3 clock cycle of interval start to perform described step S3.
As a further improvement on the present invention, in described step S1, " the first data to low level 32 bit input one 32 bits of described first shift register " specifically comprise: input 32 Bit datas continuously to described low level 32 bit according to the order from a high position to low level.
As a further improvement on the present invention, described step S3 is specially: in the second data of double extraction, front the second data once extracted are stored in high 67 bits of described second shift register, by after the second data of once extracting be stored in low 67 bits of described second shift register.
As a further improvement on the present invention, described step S4 is specially:
S41, determine initial extraction address, from described initial extraction address, from described second shift register, extract data continuously;
S42, judge the validity of data, if data are effective, then initial extraction address is constant, if data invalid, then initial extraction address increases by 1 bit;
Described 3rd data of S43, extraction acquisition 1 bit, and lock using the initial extraction address of described 3rd data as border.
Correspondingly, the device realizing the locking of 64B/67B encoded boundary of one embodiment of the present invention, comprising:
99 bit bit wide shift register cells: in each clock cycle, the first shift register of one 99 bit bit wides is offset 32 bits to a high position, and to described first shift register low level 32 bit input one 32 bits the first data;
Extract skew control logic unit: for controlling clock cycle interval and extracting side-play amount, extract the second data of 67 bits from described first shift register;
134 bit bit wide shift register cells: for the second data of double extraction being stored in the second shift register of one 134 bit bit wides;
Edge locking control logic unit: for determining initial extraction address, extracts the 3rd data of 67 bits from described initial extraction address from described second shift register, and locks the border of described 3rd data.
As a further improvement on the present invention, described extraction skew control logic cell operation is in three phases:
First stage: the setting clock cycle is spaced apart 2 clock cycle, often extracts once described second data, extracting side-play amount increases by 3 bits, extracts side-play amount and is increased to 30 bits from 0 bit;
Second stage: the setting clock cycle is spaced apart 2 clock cycle, often extracts once described second data, extracting side-play amount increases by 3 bits, extracts side-play amount and is increased to 31 bits from 1 bit;
Phase III: the setting clock cycle is spaced apart 2 clock cycle, often extracts once described second data, extracting side-play amount increases by 3 bits, extracts side-play amount and is increased to 29 bits from 2 bits.
As a further improvement on the present invention, after the described first stage completes, 3 clock cycle of interval start to enter second stage, and after described second stage completes, 3 clock cycle of interval start to enter the phase III.
As a further improvement on the present invention, described edge locking control logic unit also comprises a data validity judging unit: for judging the validity of data, if data are effective, then initial extraction address is constant, if data invalid, then initial extraction address increases by 1 bit;
The invention has the beneficial effects as follows: the present invention extracts skew control logic and edge locking control logic by using, achieve the 67 bit valid data being reverted to by 32 Bit datas inputted continuously and meet 64B/67B coding requirement, conversion speed is fast, and logic control element is simple.
Accompanying drawing explanation
Fig. 1 is the flow chart of the method realizing the locking of 64B/67B encoded boundary in an embodiment of the present invention;
Fig. 2 is the first shift register shifting function schematic diagram in an embodiment of the present invention;
Fig. 3 is the second schematic diagram data extracting 67 bits in an embodiment of the present invention from the first shift register;
Fig. 4 is the 3rd schematic diagram data extracting 67 bits in an embodiment of the present invention from the second shift register;
Fig. 5 is the device schematic diagram realizing the locking of 64B/67B encoded boundary in an embodiment of the present invention.
Embodiment
Describe the present invention below with reference to embodiment shown in the drawings.But these execution modes do not limit the present invention, the structure that those of ordinary skill in the art makes according to these execution modes, method or conversion functionally are all included in protection scope of the present invention.
As shown in Figure 1, for realizing the flow chart of the method for 64B/67B encoded boundary locking in an embodiment of the present invention, the method comprises the following steps:
S1, in each clock cycle, the first shift register of one 99 bit bit wides is offset 32 bits to a high position, and the first data of low level 32 bit input one 32 bits to described first shift register.Here it should be noted that, the clock cycle herein, represent the clock cycle corresponding for 32 Bit data inputs, that is, in each described clock cycle, all can carry out the action of 32 Bit data inputs.
Wherein, step S11, in each clock cycle, the first shift register of one 99 bit bit wides is offset 32 bits to a high position.Data in shift register mentioned in the present invention can in shift pulse effect once shift to right or left by turn, data both can walk abreast input, parallel output, also can serial input, Serial output, can also be walked abreast input, Serial output, serial input, parallel output, this type of register is very flexible, has many uses too.As shown in Figure 2 (in figure, bit represents bit), described first shift register comprises 99 bits, what number in the figure 11 showed is the state of current input clock cycle shift register, this moment, first shift register comprises the data Data0 of 3 bits, the data Data1 being all 32 bits, Data2, Data3, and described data Data0, Data1, Data2, Data3 deposit in the first shift register according to the order from a high position to low level successively; What number in the figure 12 showed is the state of next input clock cycle shift register, in the clock cycle at this moment, a shifting function done by described first shift register, 32 bits are offset to a high position by all data in described first shift register, after being shifted, the last week interim Data0 position replace by Data1, the position of Data1 replace by Data2, the position of Data2 replace by Data3, originally 32 bit offset of lowest order are after a high position, and low level 32 bit 120 of the first shift register is just in idle condition.
Step S12, to described first shift register low level 32 bit input one 32 bits the first data.As shown in Figure 2, after the shifting function of an input clock cycle, the first data DataIn [31:0] of 32 bits can be inputted immediately to described first shift register, and leave described first shift register in and be in low level 32 bit 120 of idle condition, in the process, if there is mistake, then show " not finding Reference source ", it should be noted that, described first data DataIn [31:0] is input in low level 32 bit 120 continuously according to the order from a high position to low level, so in each input clock cycle, the data of the first shift register all can once be shifted renewal.
S2, control clock cycle interval and extraction side-play amount, extract the second data of 67 bits from described first shift register.The data of new input are stored in the first shift register, extract skew control logic just can control to export the clock cycle interval of data and extract side-play amount, make when the number of data bits of all new inputs is more than 67 bit, the second data of 67 corresponding bits can be extracted from the first shift register.In this step, as made a mistake, just show " not finding Reference source ".
Described step S2 is divided into three steps to realize:
S21, setting clock cycle are spaced apart 2 clock cycle, often extract once described second data, and extracting side-play amount increases by 3 bits, extract side-play amount and are increased to 30 bits from 0 bit.Shown in ginseng Fig. 3, in this step, described extraction side-play amount bit wide is 5 bits, and so-called side-play amount of extracting extracts the number of bits of being separated by between the initial address of data and described first shift register highest order.In figure, dotted line closes frame table and shows the second data be extracted, extraction side-play amount, when extracting data, is set to 0 bit, namely from the highest order of described first shift register, extracts 67 Bit datas by first time, after extraction completes after 2 clock cycle of interval, carry out the extraction of second time data; When second time extracts data, extraction side-play amount is added 3 bits on upper basis once, again extract and obtain 67 Bit datas, by that analogy, often extract 67 Bit datas, just can 2 clock cycle of interval, the basis of the extraction side-play amount simultaneously described extraction side-play amount adopted in previous extraction increases by 3 bits, until described extraction side-play amount is increased to 30 bits from 0 bit, after namely having carried out the extraction of 11 secondary data, end step S21.
After described step S21 completes, the data stored in described first shift register only have 2 bits, after needing wait 3 input clock cycles, just to reach in described first shift register data more than the requirement of 67 bits, therefore interval enters step S22 after 3 clock cycle after above-mentioned steps S21 completes.
S22, setting clock cycle are spaced apart 2 clock cycle, often extract once described second data, and extracting side-play amount increases by 3 bits, extract side-play amount and are increased to 31 bits from 1 bit.Shown in ginseng Fig. 3, in this step, when first time extracts data, extraction side-play amount is set to 1 bit, namely from the highest order of described first shift register, extracts 67 Bit datas, after having extracted 2 clock cycle of rear interval, carry out the extraction of second time data; When second time extracts data, extraction side-play amount is added 3 bits on upper basis once, again extract and obtain 67 Bit datas, by that analogy, often extract 67 Bit datas, just can 2 clock cycle of interval, the basis of the extraction side-play amount simultaneously described extraction side-play amount adopted in previous extraction increases by 3 bits, until described extraction side-play amount is increased to 31 bits from 1 bit, after namely having carried out the extraction of 11 secondary data, end step S22.
After described step S22 completes, the data stored in described first shift register only have 1 bit, after needing wait 3 input clock cycles, just to reach in described first shift register data more than the requirement of 67 bits, therefore interval enters step S23 after 3 clock cycle after above-mentioned steps S22 completes.
S23, setting clock cycle are spaced apart 2 clock cycle, often extract once described second data, and extracting side-play amount increases by 3 bits, extract side-play amount and are increased to 29 bits from 2 bits.Shown in ginseng Fig. 3, in this step, when first time extracts data, extraction side-play amount is set to 2 bits, namely from the highest order of described first shift register, extracts 67 Bit datas, after having extracted 2 clock cycle of rear interval, carry out the extraction of second time data; When second time extracts data, extraction side-play amount is added 3 bits on upper basis once, again extract and obtain 67 Bit datas, by that analogy, often extract 67 Bit datas, just can 2 clock cycle of interval, the basis of the extraction side-play amount simultaneously described extraction side-play amount adopted in previous extraction increases by 3 bits, until described extraction side-play amount is increased to 29 bits from 2 bits, after namely having carried out the extraction of 10 secondary data, end step S23.
After described step S23 completes, the data stored in described first shift register only have 3 bits, after needing wait 3 input clock cycles, just to reach in described first shift register data more than the requirement of 67 bits, therefore interval enters step S21 after 3 clock cycle again after above-mentioned steps S23 completes.
Cycling is carried out, until 67 Bit datas extracted meet subscribe requirement according to above-mentioned steps S21, S22, S23.
S3, the second data of double extraction to be stored in the second shift register of one 134 bit bit wides.Particularly, in each input clock cycle, once there be the second data of 67 new bits to produce, second data of 67 bits that so just the last time can be produced are stored in the high 67 of the second shift register, second data of 67 bits of current extraction are stored in the low 67 of described second shift register simultaneously, as shown in Figure 4, such as, the the second data Data N extracted the N time deposits in the high 67 201 of the second shift register, and the second data Data N+1 extracted the N+1 time deposits in the low 67 202 of the second shift register.
S4, determine initial extraction address, from described initial extraction address, from described second shift register, extract the 3rd data of 67 bits, and lock the border of described 3rd data.Wherein, described initial address be edge locking logic from described second shift register extract the address of data.
S41, determine initial extraction address, from described initial extraction address, from described second shift register, extract data continuously
S42, judge the validity of data, if data are effective, then initial extraction address is constant, if data invalid, then initial extraction address increases by 1 bit.Because ensure that 67 Bit datas finally obtained are the valid data meeting 64B/67B coding requirement, so need to guarantee validity by this step, this step is specially:
S421, judge that data are whether effective, according to 64B/67B coding requirement, the bit 65 of each effective 67 Bit datas and bit 64 value of statistical indicant should be " 10 " or " 01 ", in this, as the preliminary basis for estimation to data validity.In the present embodiment, if bit 65 and bit 64 value of statistical indicant should be " 10 " or " 01 ", show that the data extracted are effective, perform step S422; If bit 65 and bit 64 value of statistical indicant should not be " 10 " or " 01 ", show the data invalid extracted, perform step S423.
S422, initial extraction address are constant.If data are effective, according to current initial extraction address, continue extract the data of subsequent extracted and make Effective judgement, require until meet application.
S423, initial extraction address increase by 1 bit.If data invalid, then on existing initial extraction address, increase a bit, extract 67 new Bit datas and carry out Effective judgement ... so carry out data and extract traversal, traversal can search out effective 67 Bit datas for 67 times at most.
As shown in Figure 4, label 21 represents current input clock cycle second shift register state, now described initial extraction address is 15 bits, label 22 represents that the second data of 67 next time new bits produce the state of rear second shift register, if find after effectively judging, data are effective, and the initial extraction address so descending secondary data to extract is still 15 bits; If find data invalid after effectively judging, the initial extraction address so descending secondary data to extract becomes 16 bits, so performs down, until find valid data.
Described 3rd data of S43, extraction acquisition 1 bit, and lock using the initial extraction address of described 3rd data as border.After step S42, can extract multiple the 3rd data meeting 67 bits of 64B/67B coding requirement, the initial extraction address these effective 3rd data of extraction adopted conducts the locking operations as the border of effective 67 Bit datas.
As shown in Figure 5, in the present embodiment, a kind of device of the 64B/67B of realization encoded boundary locking is made up of following unit:
99 bit bit wide shift register cells: in each clock cycle, the first shift register of one 99 bit bit wides is offset 32 bits to a high position, and to described first shift register low level 32 bit input one 32 bits the first data.Here it should be noted that, the clock cycle herein, represent the clock cycle corresponding for 32 Bit data inputs, that is, in each described clock cycle, all can carry out the action of 32 Bit data inputs.
Particularly, data in shift register mentioned in the present invention can in shift pulse effect once shift to right or left by turn, data both can walk abreast input, parallel output, also can serial input, Serial output, can also be walked abreast input, Serial output, serial input, parallel output, this type of register is very flexible, has many uses too.As shown in Figure 2 (in figure, bit represents bit), described first shift register comprises 99 bits, what number in the figure 11 showed is the state of current input clock cycle shift register, this moment, first shift register comprises the data Data0 of 3 bits, the data Data1 being all 32 bits, Data2, Data3, and described data Data0, Data1, Data2, Data3 deposit in the first shift register according to the order from a high position to low level successively; What number in the figure 12 showed is the state of next input clock cycle shift register, in the clock cycle at this moment, a shifting function done by described first shift register, 32 bits are offset to a high position by all data in described first shift register, after being shifted, the last week interim Data0 position replace by Data1, the position of Data1 replace by Data2, the position of Data2 replace by Data3, originally 32 bit offset of lowest order are after a high position, and low level 32 bit 120 of the first shift register is just in idle condition.
This unit is also for the first data of low level 32 bit input one 32 bits to described first shift register.As shown in Figure 2, after the shifting function of an input clock cycle, the first data DataIn [31:0] of 32 bits can be inputted immediately to described first shift register, and leave described first shift register in and be in low level 32 bit 120 of idle condition, in the process, if there is mistake, then show " not finding Reference source ", it should be noted that, described first data DataIn [31:0] is input in low level 32 bit 120 continuously according to the order from a high position to low level, so in each input clock cycle, the data of the first shift register all can once be shifted renewal.
Extract skew control logic unit: for controlling clock cycle interval and extracting side-play amount, extract the second data of 67 bits from described first shift register.
Particularly, this unit, for controlling clock cycle interval and extracting side-play amount, extracts the second data of 67 bits from described first shift register.The data of new input are stored in the first shift register, extract skew control logic just can control to export the clock cycle interval of data and extract side-play amount, make when interval N number of clock cycle, when in first shift register, all amount of bits are more than 67 bit, the second data of 67 corresponding bits can be extracted from the first shift register, wherein N is positive integer, and the second data of double extraction are coherent.As made a mistake in this unit, just show " not finding Reference source ".
This unit is divided into three phases to realize corresponding function:
First stage: the setting clock cycle is spaced apart 2 clock cycle, often extracts once described second data, extracting side-play amount increases by 3 bits, extracts side-play amount and is increased to 30 bits from 0 bit.Shown in ginseng Fig. 3, in this stage, described extraction side-play amount bit wide is 5 bits, and so-called side-play amount of extracting extracts the number of bits of being separated by between the initial address of data and described first shift register highest order.In figure, dotted line closes frame table and shows the second data be extracted, extraction side-play amount, when extracting data, is set to 0 bit, namely from the highest order of described first shift register, extracts 67 Bit datas by first time, after extraction completes after 2 clock cycle of interval, carry out the extraction of second time data; When second time extracts data, extraction side-play amount is added 3 bits on upper basis once, again extract and obtain 67 Bit datas, by that analogy, often extract 67 Bit datas, just can 2 clock cycle of interval, the basis of the extraction side-play amount simultaneously described extraction side-play amount adopted in previous extraction increases by 3 bits, until described extraction side-play amount is increased to 30 bits from 0 bit, after namely having carried out the extraction of 11 secondary data, terminate the described first stage.
After the described first stage completes, the data stored in described first shift register only have 2 bits, after needing wait 3 input clock cycles, just to reach in described first shift register data more than the requirement of 67 bits, therefore interval enters second stage after 3 clock cycle after the above-mentioned first stage completes.
Second stage: the setting clock cycle is spaced apart 2 clock cycle, often extracts once described second data, extracting side-play amount increases by 3 bits, extracts side-play amount and is increased to 31 bits from 1 bit.Shown in ginseng Fig. 3, in this stage, when first time extracts data, extraction side-play amount is set to 1 bit, namely from the highest order of described first shift register, extracts 67 Bit datas, after having extracted 2 clock cycle of rear interval, carry out the extraction of second time data; When second time extracts data, extraction side-play amount is added 3 bits on upper basis once, again extract and obtain 67 Bit datas, by that analogy, often extract 67 Bit datas, just can 2 clock cycle of interval, the basis of the extraction side-play amount simultaneously described extraction side-play amount adopted in previous extraction increases by 3 bits, until described extraction side-play amount is increased to 31 bits from 1 bit, after namely having carried out the extraction of 11 secondary data, terminate described second stage.
After described second stage completes, the data stored in described first shift register only have 1 bit, after needing wait 3 input clock cycles, just to reach in described first shift register data more than the requirement of 67 bits, therefore interval enters the step phase III after 3 clock cycle after above-mentioned second stage completes.
Phase III: the setting clock cycle is spaced apart 2 clock cycle, often extracts once described second data, extracting side-play amount increases by 3 bits, extracts side-play amount and is increased to 29 bits from 2 bits.Shown in ginseng Fig. 3, in this stage, when first time extracts data, extraction side-play amount is set to 2 bits, namely from the highest order of described first shift register, extracts 67 Bit datas, after having extracted 2 clock cycle of rear interval, carry out the extraction of second time data; When second time extracts data, extraction side-play amount is added 3 bits on upper basis once, again extract and obtain 67 Bit datas, by that analogy, often extract 67 Bit datas, just can 2 clock cycle of interval, the basis of the extraction side-play amount simultaneously described extraction side-play amount adopted in previous extraction increases by 3 bits, until described extraction side-play amount is increased to 29 bits from 2 bits, after namely having carried out the extraction of 10 secondary data, terminate the phase III.
After the described phase III completes, the data stored in described first shift register only have 3 bits, after needing wait 3 input clock cycles, just to reach in described first shift register data more than the requirement of 67 bits, therefore interval enters the first stage after 3 clock cycle again after the above-mentioned phase III completes.
Cycling is carried out, until 67 Bit datas extracted meet subscribe requirement according to above-mentioned first stage, first stage, first stage.
134 bit bit wide shift register cells: for the second data of double extraction are stored in the second shift register of one 134 bit bit wides.
For the second data of double extraction are stored in the second shift register of one 134 bit bit wides.Particularly, in each input clock cycle, once there be the second data of 67 new bits to produce, second data of 67 bits that so just the last time can be produced are stored in the high 67 of the second shift register, second data of 67 bits of current extraction are stored in the low 67 of described second shift register simultaneously, as shown in Figure 4, such as, the the second data Data N extracted the N time deposits in the high 67 201 of the second shift register, and the second data Data N+1 extracted the N+1 time deposits in the low 67 202 of the second shift register.
Edge locking control logic unit: for determining initial extraction address, extracts the 3rd data of 67 bits from described initial extraction address from described second shift register, and locks the border of described 3rd data.
Particularly, for determining initial extraction address, from described initial extraction address, from described second shift register, extract the 3rd data of 67 bits, and lock the border of described 3rd data.Wherein, described initial address be edge locking logic from described second shift register extract the address of data.
Particularly, for determining initial extraction address, from described initial extraction address, from described second shift register, extract data continuously.
Particularly, for judging the validity of data, if data are effective, then initial extraction address is constant, if data invalid, then initial extraction address increases by 1 bit.Because ensure that 67 Bit datas finally obtained are the valid data meeting 64B/67B coding requirement, so need to guarantee validity by this step.
Particularly, for judging that whether data are effective, according to 64B/67B coding requirement, the bit 65 of each effective 67 Bit datas and bit 64 value of statistical indicant should be " 10 " or " 01 ", in this, as the preliminary basis for estimation to data validity.In the present embodiment, if bit 65 and bit 64 value of statistical indicant should be " 10 " or " 01 ", show that the data extracted are effective, according to current initial extraction address, continue extract the data of subsequent extracted and make Effective judgement, require until meet application; If bit 65 and bit 64 value of statistical indicant should not be " 10 " or " 01 ", show the data invalid extracted, then on existing initial extraction address, increase a bit, extract 67 new Bit datas and carry out Effective judgement ... so carry out data and extract traversal, traversal can search out effective 67 Bit datas for 67 times at most.
As shown in Figure 4, label 21 represents current input clock cycle second shift register state, now described initial extraction address is 15 bits, label 22 represents that the second data of 67 next time new bits produce the state of rear second shift register, if find after effectively judging, data are effective, and the initial extraction address so descending secondary data to extract is still 15 bits; If find data invalid after effectively judging, the initial extraction address so descending secondary data to extract becomes 16 bits, so performs down, until find valid data.
Particularly, this unit also for extracting described 3rd data of acquisition 1 bit, and locks using the initial extraction address of described 3rd data as border.After step S42, can extract multiple the 3rd data meeting 67 bits of 64B/67B coding requirement, the initial extraction address these effective 3rd data of extraction adopted conducts the locking operations as the border of effective 67 Bit datas.
For convenience of description, various unit is divided into describe respectively with function when describing above device.Certainly, the function of each unit can be realized in same or multiple software and/or hardware when implementing the application.
As seen through the above description of the embodiments, those skilled in the art can be well understood to the mode that the application can add required general hardware platform by software and realizes.Based on such understanding, the technical scheme of the application can embody with the form of software product the part that prior art contributes in essence in other words, this computer software product can be stored in storage medium, as ROM/RAM, magnetic disc, CD etc., comprising some instructions in order to make a computer equipment (can be personal computer, server, or the network equipment etc.) perform the method described in some part of each execution mode of the application or execution mode.
Device embodiments described above is only schematic, the wherein said unit illustrated as separating component or can may not be and physically separates, parts as unit display can be or may not be physical location, namely can be positioned at a place, or also can be distributed in multiple network element.Some or all of module wherein can be selected according to the actual needs to realize the object of present embodiment scheme.Those of ordinary skill in the art, when not paying creative work, are namely appreciated that and implement.
Be to be understood that, although this specification is described according to execution mode, but not each execution mode only comprises an independently technical scheme, this narrating mode of specification is only for clarity sake, those skilled in the art should by specification integrally, technical scheme in each execution mode also through appropriately combined, can form other execution modes that it will be appreciated by those skilled in the art that.
A series of detailed description listed is above only illustrating for feasibility execution mode of the present invention; they are also not used to limit the scope of the invention, all do not depart from the skill of the present invention equivalent implementations done of spirit or change all should be included within protection scope of the present invention.
Claims (10)
1. realize a method for 64B/67B encoded boundary locking, it is characterized in that, the method comprises the following steps:
S1, in each clock cycle, the first shift register of one 99 bit bit wides is offset 32 bits to a high position, and the first data of low level 32 bit input one 32 bits to described first shift register;
S2, control clock cycle interval and extraction side-play amount, make when interval N number of clock cycle, when in described first shift register, data are more than 67 bit, the second data of 67 bits are extracted from described first shift register, wherein, described N is positive integer, and the second data of double extraction are coherent;
S3, the second data of double extraction are stored in the second shift register of one 134 bit bit wides;
S4, determine initial extraction address, from described initial extraction address, from described second shift register, extract the 3rd data of 67 bits, and lock the border of described 3rd data.
2. the method realizing the locking of 64B/67B encoded boundary according to claim 1, it is characterized in that, described step S2 specifically comprises the steps:
S21, setting clock cycle are spaced apart 2 clock cycle, often extract once described second data, and extracting side-play amount increases by 3 bits, extract side-play amount and are increased to 30 bits from 0 bit;
S22, setting clock cycle are spaced apart 2 clock cycle, often extract once described second data, and extracting side-play amount increases by 3 bits, extract side-play amount and are increased to 31 bits from 1 bit;
S23, setting clock cycle are spaced apart 2 clock cycle, often extract once described second data, and extracting side-play amount increases by 3 bits, extract side-play amount and are increased to 29 bits from 2 bits.
3. the method realizing the locking of 64B/67B encoded boundary according to claim 2, it is characterized in that, after described step S21 completes, 3 clock cycle of interval start to perform described step S22, and after described step S22 completes, 3 clock cycle of interval start to perform described step S23.
4. the method realizing the locking of 64B/67B encoded boundary according to claim 1, it is characterized in that, in described step S1, " the first data to low level 32 bit input one 32 bits of described first shift register " specifically comprise: input 32 Bit datas continuously to described low level 32 bit according to the order from a high position to low level.
5. the method realizing the locking of 64B/67B encoded boundary according to claim 1, it is characterized in that, described step S3 is specially: in the second data of double extraction, front the second data once extracted are stored in high 67 bits of described second shift register, by after the second data of once extracting be stored in low 67 bits of described second shift register.
6. the method realizing the locking of 64B/67B encoded boundary according to claim 1, it is characterized in that, described step S4 is specially:
S41, determine initial extraction address, from described initial extraction address, from described second shift register, extract data continuously;
S42, judge the validity of data, if data are effective, then initial extraction address is constant, if data invalid, then initial extraction address increases by 1 bit;
Described 3rd data of S43, extraction acquisition 1 bit, and lock using the initial extraction address of described 3rd data as border.
7. realize a device for 64B/67B encoded boundary locking, it is characterized in that, this device comprises:
99 bit bit wide shift register cells: in each clock cycle, the first shift register of one 99 bit bit wides is offset 32 bits to a high position, and to described first shift register low level 32 bit input one 32 bits the first data;
Extract skew control logic unit: for controlling clock cycle interval and extracting side-play amount, make when interval N number of clock cycle, when in described first shift register, data are more than 67 bit, the second data of 67 bits are extracted from described first shift register, wherein, described N is positive integer, and described second data of double extraction are coherent;
134 bit bit wide shift register cells: for the second data of double extraction being stored in the second shift register of one 134 bit bit wides;
Edge locking control logic unit: for determining initial extraction address, extracts the 3rd data of 67 bits from described initial extraction address from described second shift register, and locks the border of described 3rd data.
8. the device realizing the locking of 64B/67B encoded boundary according to claim 7, is characterized in that, described extraction skew control logic cell operation is in three phases:
First stage: the setting clock cycle is spaced apart 2 clock cycle, often extracts once described second data, extracting side-play amount increases by 3 bits, extracts side-play amount and is increased to 30 bits from 0 bit;
Second stage: the setting clock cycle is spaced apart 2 clock cycle, often extracts once described second data, extracting side-play amount increases by 3 bits, extracts side-play amount and is increased to 31 bits from 1 bit;
Phase III: the setting clock cycle is spaced apart 2 clock cycle, often extracts once described second data, extracting side-play amount increases by 3 bits, extracts side-play amount and is increased to 29 bits from 2 bits.
9. the device realizing the locking of 64B/67B encoded boundary according to claim 8, it is characterized in that, after the described first stage completes, 3 clock cycle of interval start to enter second stage, and after described second stage completes, 3 clock cycle of interval start to enter the phase III.
10. the device realizing the locking of 64B/67B encoded boundary according to claim 7, it is characterized in that, described edge locking control logic unit also comprises a data validity judging unit: for judging the validity of data, if data are effective, then initial extraction address is constant, if data invalid, then initial extraction address increases by 1 bit.
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