CN102956497A - Transistor and forming method thereof - Google Patents
Transistor and forming method thereof Download PDFInfo
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- CN102956497A CN102956497A CN2011102527311A CN201110252731A CN102956497A CN 102956497 A CN102956497 A CN 102956497A CN 2011102527311 A CN2011102527311 A CN 2011102527311A CN 201110252731 A CN201110252731 A CN 201110252731A CN 102956497 A CN102956497 A CN 102956497A
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Abstract
The invention relates to a transistor and a forming method thereof. The forming method comprises the steps of: providing a substrate; patterning the substrate to form a first opening; forming a barrier side wall on the side wall of the first opening, wherein the barrier side wall and the bottom of the first opening are encircled to form a second opening; forming a semiconductor layer in the second opening; forming a stress layer on the semiconductor layer, wherein the lattice constant of the semiconductor layer is greater than that of the stress layer; and forming a grid structure on the stress layer and forming a doping area in the substrate at which the barrier side wall is opposite to one side of the first opening. The transistor comprises the substrate, the grid structure on the substrate, a first barrier side wall and a second barrier side wall in the substrate below the grid structure, the semiconductor layer between the first barrier side wall and the second barrier side wall, the stress layer on the semiconductor layer and the doping area in the substrate outside the first barrier side wall and the second barrier side wall, wherein the lattice constant of the semiconductor layer is greater than that of the stress layer. According to the transistor and the forming method thereof provided by the invention, the performance of the transistor is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, more specifically, the present invention relates to a kind of transistor and forming method thereof.
Background technology
Metal-oxide-semicondutor (MOS) transistor is the most basic device during semiconductor is made, and it is widely used in the various integrated circuits, and the doping type during according to main charge carrier and manufacturing is different, is divided into NMOS and PMOS transistor.
Prior art provides a kind of transistorized formation method.Please refer to Fig. 1 to Fig. 3, be the transistorized formation method cross-sectional view of prior art.
Please refer to Fig. 1, silicon substrate 01 is provided, described silicon substrate 01 is carried out Implantation, and it is heat-treated, form well region 001; Described silicon substrate 01 is carried out Implantation form ion district 002, described ion district 002 is positioned at silicon substrate 01 surface, to carry out the adjusting of threshold voltage; Form grid oxic horizon 02 and grid 03 on the described silicon substrate 01, described grid oxic horizon 02 and grid 03 consist of grid structure.
Then, please refer to Fig. 2, the silicon substrate 01 interior formation light doping section 04 in the grid structure both sides, described light doping section 04 forms by Implantation and heat treatment.
Then, please refer to Fig. 3, form the side wall 05 of grid structure at the silicon substrate 01 of grid structure both sides.Take described side wall 05 as mask, described silicon substrate 01 is carried out source/drain region heavy doping inject (S/D), and it is heat-treated the silicon substrate 100 interior formation source/drain regions 06 in the grid structure both sides.
In being the Chinese patent application of CN101789447A, publication number can find manyly to form transistorized technical information about existing.
Find that in practice in the transistor that existing method forms, the electron mobility of the channel region between source/drain region is lower, thereby affects transistorized performance.
Summary of the invention
The technical problem that the present invention solves provides a kind of transistor that improves transistor performance and forming method thereof.
In order to address the above problem, the invention provides a kind of transistorized formation method, comprising: substrate is provided, and graphical described substrate forms the first opening that is arranged in substrate; Sidewall formation at described the first opening stops side wall, and the described bottom of side wall and the first opening that stops surrounds the second opening; In described the second opening, form semiconductor layer; Form stressor layers at semiconductor layer, the lattice constant of described semiconductor layer is greater than the lattice constant of stressor layers; Form grid structure in stressor layers, stopping that side wall forms doped region in the substrate of a side of the first opening dorsad.
Alternatively, described substrate is silicon substrate, and the material of described semiconductor layer is SiGe.
Alternatively, the material of described stressor layers is identical with the material of described substrate.
Alternatively, the horizontal width of described the first opening is in 0.015～10 micron scope.
Alternatively, the step that graphical described substrate forms the first opening that is arranged in substrate comprises: at the hard mask graph of silicon substrate formation, take described hard mask graph as the described silicon substrate of mask etching, form the first opening.
Alternatively, the material of described hard mask graph is silica, and described step at the hard mask graph of silicon substrate formation comprises: form silicon oxide layer by thermal oxidation on the surface of silicon substrate; The described silicon oxide layer of etching forms hard mask graph.
Alternatively, describedly stop that the material of side wall is silicon nitride, described sidewall at described the first opening forms and stops that the step of side wall comprises: in sidewall and the bottom silicon nitride materials of described the first opening, form silicon nitride layer; Remove the silicon nitride of the first open bottom by etching.
Alternatively, describedly stop that the material of side wall is silica, described sidewall at described the first opening forms and stops that the step of side wall comprises: form silicon oxide layer by thermal oxidation in sidewall and the bottom of the first opening; Remove the silica of the first open bottom by etching.
Alternatively, the described step that forms semiconductor layer in described the second opening comprises: fill SiGe by extensional mode in described the second opening.
Alternatively, fill by extensional mode in the process of SiGe, the concentration of germanium remains unchanged.
Alternatively, fill by extensional mode in the process of SiGe, the concentration that forms successively from bottom to top germanium increases the concentration holding area of district, germanium.
Alternatively, fill by extensional mode in the process of SiGe, form successively from bottom to top the concentration holding area of germanium, the concentration minimizing district of germanium.
Alternatively, fill by extensional mode in the process of SiGe, the concentration that the concentration that forms successively from bottom to top germanium increases the concentration holding area of district, germanium, germanium reduces the district.
Alternatively, described step in semiconductor layer formation stressor layers comprises: form silicon materials by extensional mode, form stressor layers.
Correspondingly, the present invention also provides a kind of transistor, comprising: substrate; Be positioned at the grid structure on the substrate; Be arranged in described grid structure below substrate first stop that side wall, second stops side wall, stop side wall and the second semiconductor layer that stops between the side wall described first; Be positioned at the stressor layers on the described semiconductor layer, the lattice constant of described semiconductor layer is greater than the lattice constant of described stressor layers; Be arranged in first and stop that side wall, second stops the doped region of the substrate outside the side wall.
Alternatively, the material of described stressor layers is identical with the material of described substrate.
Alternatively, the material of described semiconductor layer is SiGe, and the material of described stressor layers is silicon.
Alternatively, the thickness of described semiconductor layer is in the scope of 30～100 nanometers.
Alternatively, the thickness of described stressor layers is in the scope of 30～100 nanometers.
Compared with prior art, the present invention has the following advantages: the lattice constant of semiconductor layer is greater than the lattice constant of stressor layers, the lattice pressure of semiconductor layer is applied on the stressor layers, the lattice of described stressor layers is vertically compressed, the movement rate of electronics in stressor layers improves, described stressor layers has improved the electron mobility of channel region between doped region, thereby improves transistorized performance;
Stop that side wall can stop that semiconductor discharges described lattice pressure layer by layer in the horizontal direction, thereby make the lattice of semiconductor layer further along the direction extension that stops that side wall extends, can further increase the pressure that is applied to the stressor layers on the semiconductor layer, more be conducive to improve the electron mobility of channel region;
Stop that side wall also be used for to intercept doped region, prevent influencing each other between the doped region that the factor such as thermal diffusion causes, thereby improved the stability of transistor performance.
Description of drawings
Fig. 1 to Fig. 3 is the transistorized formation method cross-sectional view of prior art;
Fig. 4 is the schematic flow sheet of Transistor forming method one execution mode of the present invention;
Fig. 5 to Figure 14 is the side structure schematic diagram of Transistor forming method one embodiment of the present invention;
Figure 15 is transistor one example structure schematic diagram of the present invention.
Embodiment
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization in the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public implementation.
Secondly, the present invention utilizes schematic diagram to be described in detail, and when the embodiment of the invention was described in detail in detail, for ease of explanation, described schematic diagram was example, and it should not limit the scope of protection of the invention at this.
In order to solve the problems of the prior art, the invention provides a kind of transistorized formation method, with reference to figure 4, show the schematic flow sheet of Transistor forming method one execution mode of the present invention, described formation method roughly may further comprise the steps:
Step S1 provides substrate, and graphical described substrate forms the first opening that is arranged in substrate;
Step S2 forms at the sidewall of described the first opening and to stop side wall, and the described bottom of side wall and opening that stops surrounds the second opening;
Step S3, filling semiconductor material in described the second opening forms semiconductor layer;
Step S4 forms stressor layers at semiconductor layer, and the lattice constant of described semiconductor layer is greater than the lattice constant of stressor layers;
Step S5 forms grid structure in stressor layers, is stopping that side wall forms doped region in the substrate of a side of the first opening dorsad.
Below in conjunction with specific embodiment each step of the present invention is described further.
To Figure 13, show the side structure schematic diagram of an embodiment of Transistor forming method formation of the present invention with reference to figure 5.Substrate is that silicon substrate, semi-conducting material are SiGe in the present embodiment, but the present invention does not limit this, can also be backing material, the semi-conducting material of other materials.In addition, in the present embodiment, the material of stressor layers and substrate is identical also to be silicon, does not limit but whether counter stress layer of the present invention is identical with backing material, as long as the lattice constant of semiconductor layer is greater than the lattice constant of stressor layers.
With reference to figure 5, provide silicon substrate 100.
Form hard mask layer 101 at described silicon substrate 100, wherein, the material of described hard mask layer 101 can be silicon nitride or silica, but the present invention is not restricted to this.
When the material of hard mask layer 101 is silicon nitride, can Tonghua learns the depositional mode such as vapour deposition and form silicon nitride layer on the surface of silicon substrate 100.
When the material of hard mask layer 101 was silica, the surface of mode silicon oxide substrate 100 that can be by thermal oxidation formed silicon oxide layer, and thermal oxidation technology is simpler than depositing operation, thereby has simplified technique.
Particularly, the material of described silicon oxide layer is between 0.06～0.6 micron, but the present invention is not restricted to this.
In conjunction with reference to figure 6, form the photoresist layer (not shown) at hard mask layer 101, graphical described photoresist layer, form photoetching offset plate figure, the described hard mask layer 101 take described photoetching offset plate figure as mask graphization, the design transfer of described photoetching offset plate figure to hard mask layer 101, is formed hard mask graph 111.
In conjunction with reference to figure 7, take described hard mask graph 111 as the described silicon substrate 100 of mask graphization, form the first opening 102, particularly, can remove the silicon substrate 100 that hard mask graph 111 exposes by doing quarter or wet etching, form the first opening 102.
In the present embodiment, the horizontal width of described the first opening 102 is in 0.015～10 micron scope, but the present invention does not limit this.
In conjunction with reference to figure 8 and Fig. 9, form dielectric material at bottom and the sidewall of the first opening 102, remove the dielectric material that is positioned at the first opening 102 bottoms, the dielectric material that keeps at the first opening 102 sidewalls consists of and stops side wall 103.
Particularly, described dielectric material can be silicon nitride or silica.
When described dielectric material is silicon nitride, by chemical vapour deposition (CVD) silicon nitride materials on the first opening 102 bottoms and sidewall, remove the silicon nitride that is positioned at the first opening 102 bottoms by doing the quarter method, what form the silicon nitride material that is positioned on the first opening 102 sidewalls stops side wall 103.
When described dielectric material is silica, at first, by the silicon of thermal oxidation oxidation the first opening 102 bottoms and sidewall, thereby form one deck silica, thermal oxidation technology is simpler than depositing operation, thereby has simplified technique; Secondly, remove the silica that is positioned at the first opening 102 bottoms by doing the quarter method, what form the silica material that is positioned on the first opening 102 sidewalls stops side wall 103.
The described bottom of side wall 103 and the first opening 102 that stops surrounds the second opening 106.
With reference to Figure 10, in described the second opening 106, fill silicon germanium material, form germanium-silicon layer 104; Particularly, fill silicon germanium material by extensional mode in described the second opening 106, the thickness of final germanium-silicon layer 104 is in the scope of 30～100nm, and described germanium-silicon layer 104 thickness are less than or equal to the degree of depth of the second opening 106.
In the time of can forming described silicon germanium material by extensional mode, particularly, described extensional mode is process for vapor phase epitaxy.In the process that forms silicon germanium material, reacting gas in the vacuum chamber comprises siliceous gas and germanic gas, form in the process of germanium-silicon layer the CONCENTRATION DISTRIBUTION that can regulate the germanium on the second opening 106 direction from bottom to top by regulating the concentration of germanic gas in vacuum chamber at extensional mode.
With reference to figure 10a, show among Figure 10 germanium-silicon layer 104 along the CONCENTRATION DISTRIBUTION schematic diagram of the germanium of B1B2 index line.
Form in the process of germanium-silicon layer 104 at extensional mode, the concentration of described germanium remains unchanged from bottom to top, and present embodiment need not the concentration of germanium is regulated, so technique is simple.
Need to prove, form in the process of germanium-silicon layer 104 at extensional mode, the concentration of described germanium can also be from bottom to top, the concentration that forms first germanium increases the district, the concentration holding area of rear formation germanium, (shown in Figure 10 b), concentration at germanium increases the district, the concentration of germanium is linear growth, concentration at the bottom germanium of the second opening 106 is less like this, the silicon germanium material that is positioned at like this second opening 106 bottoms can have preferably Lattice Matching with the silicon substrate 100 of the second opening 106 bottoms, and along with the concentration of germanium increases gradually, germanium-silicon layer 104 lattice constants also increase gradually, until arrive the concentration holding area of germanium, the concentration of germanium remains unchanged, and germanium-silicon layer 104 lattice constants no longer change, and can produce stress to the follow-up silicon that forms at germanium-silicon layer 104.
In addition, form in the process of germanium-silicon layer 104 at extensional mode, the concentration of described germanium can also be from bottom to top, form first the concentration holding area of germanium, the concentration of rear formation germanium increases few district (shown in Figure 10 c), and when the concentration of germanium increased few district, the concentration of germanium was linear and reduces, the lattice constant of germanium-silicon layer 104 reduces gradually, with the follow-up silicon that forms at germanium-silicon layer 104 preferably Lattice Matching is arranged like this.
Form in the process of germanium-silicon layer 104 at extensional mode, the concentration of described germanium can also be from bottom to top, and the concentration of germanium increases the concentration holding area of district, germanium successively from bottom to top, the concentration of germanium reduces district (shown in Figure 10 d).Like this, germanium-silicon layer 104 can all have well Lattice Matching with the silicon of its lower silicon substrate 100 and follow-up formation.
With reference to Figure 11, form silicon materials at germanium-silicon layer 104, form stressed silicon layer 105; Described stressed silicon layer 105 when forming silicon materials, can form silicon materials as transistorized raceway groove according to the thickness of transistor channel, makes the thickness of the thickness of stressed silicon layer 105 and transistor channel suitable.Particularly, form silicon materials by extensional mode at germanium-silicon layer 104.
Because the lattice constant of germanium-silicon layer 104 is greater than the lattice constant of silicon, germanium-silicon layer 104 can produce pressure to the silicon materials that are located thereon, and the silicon materials lattice constant that is stressed is compressed, forms stressed silicon layer 105.Electronics movement rate in stressed silicon layer 105 is larger, therefore stressed silicon layer 105 has higher electron mobility, described stressed silicon layer 105 is follow-up as transistorized channel region, thereby has improved the electron mobility of transistor channel region, and then has improved transistorized performance;
In addition, stop that side wall 103 can stop that germanium-silicon layer discharges described lattice pressure in the horizontal direction, thereby make the lattice of germanium-silicon layer 104 further along the direction extension that stops that side wall 103 extends, can further increase the pressure that is applied on the germanium-silicon layer 104 stressed silicon layer 105, more be conducive to improve the electron mobility of channel region.
With reference to Figure 12, remove the hard mask graph 111 on the silicon substrate 100, particularly, can remove described hard mask graph 111 by doing quarter or wet etching.
With reference to Figure 13, after removing hard mask graph 111, when stressed silicon layer 105 surfaces are higher than silicon substrate 100 surperficial, preferably, can continue to form silicon materials by extensional mode at silicon substrate 100, until the flush of stressed silicon layer 105 and silicon substrate 100.
After removing die figure 111, when silicon substrate 100 surfaces are higher than stressed silicon layer 105 surface, preferably, can pass through CMP or engraving method attenuate silicon substrate 100, make the flush of silicon substrate 100 and stressed silicon layer 105.
With reference to Figure 14, form grid structure 107 in stressed silicon layer 105, in grid structure 107 both sides, stopping side wall 103 dorsad the silicon substrate 100 of a side of the first opening form doped regions 108, described doped region 108 comprises the source dopant region that lays respectively at grid structure 107 both sides and leaks doped region.
The method of described formation grid structure 107, the method that forms doped region 108 is all same as the prior art, does not repeat them here.
Stop that side wall 103 also is used for the block feeds doped region and leaks doped region, prevent from the source dopant region that the factor such as thermal diffusion causes and leak influencing each other between the doped region, thereby improved the stability of transistor performance.
Correspondingly, the present invention also provides a kind of transistor, with reference to Figure 15, show the side schematic view of transistor one embodiment of the present invention, described transistor comprises: substrate 200, be positioned at the grid structure 207 on the substrate 200, be arranged in described grid structure 207 belows substrate 200 first stop side wall 201, second stops side wall 202, stop that described first side wall 201 and second stops the semiconductor layer 204 between the side wall 202, the lattice constant of described semiconductor layer 204 is greater than the lattice constant of substrate 200, be positioned at the stressor layers 205 on the semiconductor layer 204, described stressor layers 205 is identical with the material of substrate 200, bear the compression of semiconductor layer 204, be arranged in first and stop that side wall 201 second stops the source dopant region 208 of the silicon substrate 100 outside the side wall 202, leak doped region 206.
Particularly, the material of described substrate 200, described stressor layers 205 is silicon, and the thickness of described stressor layers 205 is in the scope of 30～100 nanometers;
The material of described semiconductor layer 204 is SiGe, and semiconductor layer 204 is germanium-silicon layer, and the thickness of described germanium-silicon layer is in the scope of 30～100 nanometers.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (19)
1. a transistorized formation method is characterized in that, comprising: substrate is provided, and graphical described substrate forms the first opening that is arranged in substrate; Sidewall formation at described the first opening stops side wall, and the described bottom of side wall and the first opening that stops surrounds the second opening; In described the second opening, form semiconductor layer; Form stressor layers at semiconductor layer, the lattice constant of described semiconductor layer is greater than the lattice constant of stressor layers; Form grid structure in stressor layers, stopping that side wall forms doped region in the substrate of a side of the first opening dorsad.
2. transistorized formation method as claimed in claim 1 is characterized in that, described substrate is silicon substrate, and the material of described semiconductor layer is SiGe.
3. transistorized formation method as claimed in claim 2 is characterized in that, the material of described stressor layers is identical with the material of described substrate.
4. transistorized formation method as claimed in claim 1 is characterized in that the horizontal width of described the first opening is in 0.015～10 micron scope.
5. transistorized formation method as claimed in claim 2, it is characterized in that, the step that graphical described substrate forms the first opening that is arranged in substrate comprises: form hard mask graph at silicon substrate, take described hard mask graph as the described silicon substrate of mask etching, form the first opening.
6. transistorized formation method as claimed in claim 5 is characterized in that, the material of described hard mask graph is silica, and described step at the hard mask graph of silicon substrate formation comprises: form silicon oxide layer by thermal oxidation on the surface of silicon substrate; The described silicon oxide layer of etching forms hard mask graph.
7. transistorized formation method as claimed in claim 1, it is characterized in that, describedly stop that the material of side wall is silicon nitride, described sidewall at described the first opening forms and stops that the step of side wall comprises: in sidewall and the bottom silicon nitride materials of described the first opening, form silicon nitride layer; Remove the silicon nitride of the first open bottom by etching.
8. transistorized formation method as claimed in claim 2, it is characterized in that, describedly stop that the material of side wall is silica, described sidewall at described the first opening forms and stops that the step of side wall comprises: form silicon oxide layer by thermal oxidation in sidewall and the bottom of the first opening; Remove the silica of the first open bottom by etching.
9. transistorized formation method as claimed in claim 2 is characterized in that, the described step that forms semiconductor layer in described the second opening comprises: fill SiGe by extensional mode in described the second opening.
10. transistorized formation method as claimed in claim 9 is characterized in that, fills by extensional mode in the process of SiGe, and the concentration of germanium remains unchanged.
11. transistorized formation method as claimed in claim 9 is characterized in that, fills by extensional mode in the process of SiGe, the concentration that forms successively from bottom to top germanium increases the concentration holding area of district, germanium.
12. transistorized formation method as claimed in claim 9 is characterized in that, fills by extensional mode in the process of SiGe, forms successively from bottom to top the concentration holding area of germanium, the concentration minimizing district of germanium.
13. transistorized formation method as claimed in claim 9 is characterized in that, fills by extensional mode in the process of SiGe, the concentration that the concentration that forms successively from bottom to top germanium increases the concentration holding area of district, germanium, germanium reduces the district.
14. transistorized formation method as claimed in claim 3 is characterized in that, described step in semiconductor layer formation stressor layers comprises: form silicon materials by extensional mode, form stressor layers.
15. a transistor is characterized in that, comprising:
Substrate;
Be positioned at the grid structure on the substrate;
Be arranged in described grid structure below substrate first stop that side wall, second stops side wall, stop side wall and the second semiconductor layer that stops between the side wall described first;
Be positioned at the stressor layers on the described semiconductor layer, the lattice constant of described semiconductor layer is greater than the lattice constant of described stressor layers;
Be arranged in first and stop that side wall, second stops the doped region of the substrate outside the side wall.
16. transistor as claimed in claim 15 is characterized in that, the material of described stressor layers is identical with the material of described substrate.
17. transistor as claimed in claim 16 is characterized in that, the material of described semiconductor layer is SiGe, and the material of described stressor layers is silicon.
18. transistor as claimed in claim 17 is characterized in that, the thickness of described semiconductor layer is in the scope of 30～100 nanometers.
19. transistor as claimed in claim 17 is characterized in that, the thickness of described stressor layers is in the scope of 30～100 nanometers.
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| CN201110252731.1A CN102956497B (en) | 2011-08-30 | 2011-08-30 | Transistor and forming method thereof |
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| CN1722363A (en) * | 2004-04-22 | 2006-01-18 | 国际商业机器公司 | Method for manufacturing strain silicon mixing underlay and silicon mixing underlay |
| CN1725437A (en) * | 2004-07-23 | 2006-01-25 | 国际商业机器公司 | Patterned strained semiconductor substrate and device |
| US20060226483A1 (en) * | 2005-04-06 | 2006-10-12 | Agency For Science, Technology And Research | Method of fabricating strained channel devices |
| CN1905211A (en) * | 2005-07-26 | 2007-01-31 | 东部电子株式会社 | Strained channel transistor and method of fabricating the same |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1722363A (en) * | 2004-04-22 | 2006-01-18 | 国际商业机器公司 | Method for manufacturing strain silicon mixing underlay and silicon mixing underlay |
| CN1725437A (en) * | 2004-07-23 | 2006-01-25 | 国际商业机器公司 | Patterned strained semiconductor substrate and device |
| US20060226483A1 (en) * | 2005-04-06 | 2006-10-12 | Agency For Science, Technology And Research | Method of fabricating strained channel devices |
| CN1905211A (en) * | 2005-07-26 | 2007-01-31 | 东部电子株式会社 | Strained channel transistor and method of fabricating the same |
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