CN102956464B - A kind of manufacture method of semiconductor device - Google Patents
A kind of manufacture method of semiconductor device Download PDFInfo
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- CN102956464B CN102956464B CN201110239275.7A CN201110239275A CN102956464B CN 102956464 B CN102956464 B CN 102956464B CN 201110239275 A CN201110239275 A CN 201110239275A CN 102956464 B CN102956464 B CN 102956464B
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Abstract
The invention provides a kind of manufacture method of semiconductor device, comprising: semiconductor structure is provided, comprise Semiconductor substrate, high k dielectric layer, soakage layer and sacrificial gate dielectric layer; Form dummy gate structure; The clearance wall structure near described dummy gate structure is formed in the both sides of described dummy gate structure; Remove described sacrificial gate dielectric layer, to form gate groove in the middle of described clearance wall structure; Metal gate is formed in described gate groove.Wherein, the step forming metal gate comprises: form TMAAB in described gate groove, the precursor that described TMAAB fills as metallic aluminium; Annealing in process is carried out to described metallic aluminium precursor.According to the present invention, effectively can improve the ability that application conventional deposition processes realizes metal gate filling, and because metallic aluminium can only grow from bottom to top from the bottom of described gate groove, based on this feature, the method that application the present invention proposes can fill metal alum gate in the gate groove of any structure.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of method improving metal gate filling capacity.
Background technology
In the manufacturing process of integrated circuit of future generation, for the making of the grid of complementary metal oxide semiconductors (CMOS) (CMOS), usually adopt post tensioned unbonded prestressed concrete (gate-last) technique.The process of typical post tensioned unbonded prestressed concrete technique comprises: first, form dummy gate structure on a semiconductor substrate, and described dummy gate structure is made up of boundary layer from bottom to top, high k dielectric layer, cover layer (cappinglayer) and sacrificial gate dielectric layer; Then, form gate pitch wall construction in the both sides of described dummy gate structure, remove the sacrificial gate dielectric layer of described dummy gate structure afterwards, between described gate pitch wall construction, leave a groove; Then, in described groove, deposit workfunction layers (workfunctionmetallayer), barrier layer (barrierlayer) and soakage layer (wettinglayer) successively; Finally carry out the filling of metal gate (being generally aluminium).The transistor arrangement adopting above-mentioned technique to make is commonly referred to high k dielectric layer/metal gate transistor.
In the process forming described metal gate structure, usually adopt depositing operation to form the layers of material of described metal gate structure, comprise ald (ALD), chemical vapor deposition (CVD) and physical vapor deposition (PVD).Wherein, first two depositing operation can form good conformal capping layer in the bottom of described groove and sidewall, but along with depositing the increase of the number of plies, making the open top of described groove more and more less, affecting the filling of subsequent metal grid; Physical gas-phase deposition then can make the layers of material of described metal gate structure only be deposited on the bottom of described groove by controlling relevant parameter, but when filling has the groove of high aspect ratio structure, the atom sputtered is not because scattering effect is when completing bottom deposit, first the open top of described groove is sealed, affect the filling of subsequent metal grid.
Therefore, above-mentioned traditional deposition process can not implement the filling of the metal gate in post tensioned unbonded prestressed concrete technique effectively, needs to propose a kind of method, improves the ability adopting traditional deposition process to form metal gate structure.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprising: semiconductor structure is provided, comprise Semiconductor substrate, high k dielectric layer, soakage layer and sacrificial gate dielectric layer; Form dummy gate structure; The clearance wall structure near described dummy gate structure is formed in the both sides of described dummy gate structure; Remove described sacrificial gate dielectric layer, to form gate groove in the middle of described clearance wall structure; Metal gate is formed in described gate groove.
Further, the step forming dummy gate structure comprises: etching forms described layers of material on the semiconductor substrate.
Further, the step forming metal gate comprises: form TMAAB in described gate groove, the precursor that described TMAAB fills as metallic aluminium; Annealing in process is carried out to described metallic aluminium precursor.
Further, described semiconductor structure also comprises workfunction layers between described high k dielectric layer and soakage layer and cover layer.
Further, atom layer deposition process or physical gas-phase deposition is adopted to form described cover layer.
Further, described tectal material is titanium nitride or tantalum nitride; Described tectal thickness is 10-20 dust.
Further, physical gas-phase deposition is adopted to form described soakage layer.
Further, the material of described soakage layer is the material not containing oxide or nitrogen containing metal.
Further, the material of described soakage layer is titanium or titanium-aluminium alloy.
Further, the thickness of described soakage layer is 30-100 dust.
Further, described semiconductor structure also comprises the boundary layer between described Semiconductor substrate and high k dielectric layer.
Further, chemical vapor deposition method is adopted to form described TMAAB in described gate groove.
Further, described chemical vapor deposition method is carried out under the condition of 40-70 DEG C.
Further, described chemical vapor deposition method is carried out under the condition of 70 DEG C.
Further, the temperature of described annealing in process is 100-500 DEG C.
Further, the time that described annealing in process continues is 100-600s.
Further, described metal gate is metal alum gate.
According to the present invention, the ability that application conventional deposition processes realizes metal gate filling effectively can be improved.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A-Fig. 1 F is the schematic cross sectional view of each step of the method for the raising metal gate filling capacity that the present invention proposes;
Fig. 2 is the flow chart of the method for the raising metal gate filling capacity that the present invention proposes.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to explain the method for the raising metal gate filling capacity that the present invention proposes.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should be understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
Below, the detailed step of the method for the raising metal gate filling capacity that the present invention proposes is described with reference to Figure 1A-Fig. 1 F and Fig. 2.
With reference to Figure 1A-Fig. 1 F, illustrated therein is the schematic cross sectional view of each step of the method for the raising metal gate filling capacity that the present invention proposes.
First, as shown in Figure 1A, provide semiconductor structure 100, described semiconductor structure 100 comprises Semiconductor substrate 101, boundary layer 102, high k dielectric layer 103 and workfunction layers 104.The constituent material of described Semiconductor substrate 101 can adopt unadulterated monocrystalline silicon, monocrystalline silicon, silicon-on-insulator (SOI) etc. doped with impurity.Exemplarily, in the present embodiment, Semiconductor substrate 101 selects single crystal silicon material to form.In Semiconductor substrate 101, be formed with isolation channel, buried regions etc., in order to simplify, be omitted in diagram.
The material of described boundary layer 102 can comprise oxide, as silicon dioxide (SiO
2).The material of described high k dielectric layer 103 can comprise hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide etc., particularly preferably is hafnium oxide, zirconia and aluminium oxide.Described workfunction layers 104 can comprise one or more layers metal, and its constituent material comprises titanium nitride, titanium-aluminium alloy and tungsten nitride.
Then, as shown in Figure 1B, described workfunction layers 104 forms cover layer 105, soakage layer 106 and sacrificial gate dielectric layer 107 successively.
The material of described cover layer 105 comprises titanium nitride and tantalum nitride.Atom layer deposition process or physical gas-phase deposition is adopted to form described cover layer 105.The thickness of described cover layer 105 is 10-20 dust.
The material of described soakage layer 106 comprises titanium, titanium-aluminium alloy and other material containing oxide or nitrogen containing metal.In the present embodiment, adopt titanium or titanium-aluminium alloy as the material of described soakage layer 106, select physical gas-phase deposition to form described soakage layer 106.The thickness of described soakage layer 106 is 30-100 dust.
The material of described sacrificial gate dielectric layer 107 is polysilicon.Low-pressure chemical vapor deposition process (LPCVD) is adopted to form described sacrificial gate dielectric layer 107.
Then, as shown in Figure 1 C, etch the layers of material be formed in described Semiconductor substrate 101, obtain dummy gate structure 108.Described etching process adopts traditional handicraft to carry out, and this technique is well known in the art, is no longer repeated at this.
Then, as shown in figure ip, the clearance wall structure 109 near described dummy gate structure is formed in the both sides of described dummy gate structure 108.Described clearance wall structure 109 can comprise at least one deck oxide skin(coating) and/or at least one deck nitride layer.The method forming described clearance wall structure 109 is well known in the art, is no longer repeated at this.
Next, described Semiconductor substrate 101 depositing interlayer insulating film (for illustrating in figure), afterwards cmp being carried out to expose the top of described dummy gate structure 108 to described interlayer insulating film.Described interlayer insulating film adopts various materials conventional in this area, such as oxide.
Then, as referring to figure 1e, with described clearance wall structure 109 for mask, etch described dummy gate structure, remove the sacrificial gate dielectric layer of the described dummy gate structure the superiors, in the middle of described clearance wall structure 109, form a gate groove 110.Employing traditional handicraft completes the etching to described sacrificial gate dielectric layer, such as dry etching.
Then, as shown in fig. 1f, in described gate groove, metal gate 111 is formed.In described gate groove, fill metallic aluminium, the filling step of described metallic aluminium comprises: first, at 40-70 DEG C, adopts chemical vapor deposition method deposition TMAAB(AlH
2(BH
4): N (CH
3)
3) in described gate groove, TMAAB is the precursor that metallic aluminium is filled; Then, carry out annealing in process to the described metallic aluminium precursor that deposition is formed, the temperature of described annealing in process is 100-500 DEG C, and the duration is 100-600s.
So far, whole processing steps that method is according to an exemplary embodiment of the present invention implemented are completed.Because TMAAB has very poor tack to dielectric layer material and nitrogenous metal material, and the material of the sidewall of the described gate groove formed is dielectric layer material, the material of the soakage layer bottom described gate groove is the material not containing oxide or nitrogen containing metal, so TMAAB can only be formed in the bottom of described gate groove.After an annealing treatment, the Al in TMAAB decomposes out, forms metal alum gate.Therefore, Al can only grow from bottom to top from the bottom of described gate groove, and based on this feature, the method that application the present invention proposes can fill metal alum gate in the gate groove of any structure.
According to the present invention, the ability that application conventional deposition processes realizes metal gate filling effectively can be improved.
With reference to Fig. 2, illustrated therein is the flow chart of the method for the raising metal gate filling capacity that the present invention proposes, for schematically illustrating the flow process of whole manufacturing process.
In step 201, provide semiconductor structure, comprise Semiconductor substrate, high k dielectric layer, soakage layer and sacrificial gate dielectric layer;
In step 202., dummy gate structure is formed;
In step 203, the clearance wall structure near described dummy gate structure is formed in the both sides of described dummy gate structure;
In step 204, remove described sacrificial gate dielectric layer, to form gate groove in the middle of described clearance wall structure;
In step 205, in described gate groove, metal gate is formed.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (15)
1. a manufacture method for semiconductor device, comprising:
There is provided semiconductor structure, comprise Semiconductor substrate, high k dielectric layer, soakage layer and sacrificial gate dielectric layer, the material of described soakage layer is not containing oxide or the material not containing nitrogen containing metal;
Form dummy gate structure;
The clearance wall structure near described dummy gate structure is formed in the both sides of described dummy gate structure;
Remove described sacrificial gate dielectric layer, to form gate groove in the middle of described clearance wall structure;
Metal alum gate is formed in described gate groove, the step forming described metal alum gate comprises: first form TMAAB in the bottom of described gate groove, the precursor that described TMAAB fills as metallic aluminium, again annealing in process is carried out to described metallic aluminium precursor, make the aluminium in described TMAAB decompose out and grow from the bottom of described gate groove from bottom to top.
2. method according to claim 1, is characterized in that, the step forming dummy gate structure comprises: etching forms described layers of material on the semiconductor substrate.
3. method according to claim 1, is characterized in that, described semiconductor structure also comprises workfunction layers between described high k dielectric layer and soakage layer and cover layer.
4. method according to claim 3, is characterized in that, adopts atom layer deposition process or physical gas-phase deposition to form described cover layer.
5. method according to claim 3, is characterized in that, described tectal material is titanium nitride or tantalum nitride.
6. method according to claim 3, is characterized in that, described tectal thickness is 10-20 dust.
7. method according to claim 1, is characterized in that, adopts physical gas-phase deposition to form described soakage layer.
8. method according to claim 1, is characterized in that, the material of described soakage layer is titanium or titanium-aluminium alloy.
9. method according to claim 1, is characterized in that, the thickness of described soakage layer is 30-100 dust.
10. method according to claim 1, is characterized in that, described semiconductor structure also comprises the boundary layer between described Semiconductor substrate and high k dielectric layer.
11. methods according to claim 1, is characterized in that, adopt chemical vapor deposition method to form described TMAAB in described gate groove.
12. methods according to claim 11, is characterized in that, described chemical vapor deposition method is carried out under the condition of 40-70 DEG C.
13. methods according to claim 12, is characterized in that, described chemical vapor deposition method is carried out under the condition of 70 DEG C.
14. methods according to claim 1, is characterized in that, the temperature of described annealing in process is 100-500 DEG C.
15. methods according to claim 1, is characterized in that, the time that described annealing in process continues is 100-600s.
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| CN102956464B true CN102956464B (en) | 2016-03-16 |
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Citations (1)
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| CN101714508A (en) * | 2008-10-06 | 2010-05-26 | 台湾积体电路制造股份有限公司 | Method for fabricating semiconductor device |
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| KR100826651B1 (en) * | 2007-01-26 | 2008-05-06 | 주식회사 하이닉스반도체 | Method for forming contact in semiconductor device |
| KR20080086661A (en) * | 2007-03-23 | 2008-09-26 | 주식회사 하이닉스반도체 | Method for depositing aluminium layer and method for forming contact in semiconductor device using the same |
| KR101634748B1 (en) * | 2009-12-08 | 2016-07-11 | 삼성전자주식회사 | method for manufacturing MOS transistor and forming method of integrated circuit using the sime |
| US8952462B2 (en) * | 2010-02-05 | 2015-02-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus of forming a gate |
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| CN101714508A (en) * | 2008-10-06 | 2010-05-26 | 台湾积体电路制造股份有限公司 | Method for fabricating semiconductor device |
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