CN102956261B - A kind of programmable memory cell circuit for FPGA - Google Patents
A kind of programmable memory cell circuit for FPGA Download PDFInfo
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- CN102956261B CN102956261B CN201110242676.8A CN201110242676A CN102956261B CN 102956261 B CN102956261 B CN 102956261B CN 201110242676 A CN201110242676 A CN 201110242676A CN 102956261 B CN102956261 B CN 102956261B
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Abstract
The present invention discloses a kind of programmable memory cell circuit for FPGA, this storage unit circuit comprise memory location, power supply; Described memory location is connected by the first irreversible programming interface unit with ground; Described memory location is connected by the second irreversible programming interface unit with power supply; After described storage unit circuit is programmed for 0, described memory location is forever connected with ground by irreversible being programmed for by described first irreversible programming interface unit; After described storage unit circuit is programmed for 1, described memory location is forever connected with power supply by irreversible being programmed for by described second irreversible programming interface unit.The present invention, by above technical scheme, solves in prior art for the programmable memory cell circuit safety of FPGA, technical matters that reliability is on the low side.
Description
Technical field
The present invention relates to storage unit circuit, particularly relate to a kind of programmable memory cell circuit for FPGA.
Background technology
FPGA (field programmable gate array) is made up of the logic array of rule, realizes a kind of structure of different Design of Logic Circuits by different configuration datas, and FPGA mainly can be divided three classes by the collocation method of configuration data:
1. based on the FPGA that SRAM (static RAM) technique is configured, refer in a kind of PROM (programmable read only memory) configuration data is first written to outside fpga chip, from PROM, configuration data is read in SRAM again when FPGA starts working, thus makes FPGA realize specific circuit function.Its shortcoming is: after power down, configuration data can be lost, and configuration data need be read SRAM to complete FPGA configuration from PROM during application; When being subject to high energy particle and cosmic rays interference, easily there is single-particle inversion, causing it to store the upset of data, cause storage data to become 1 from 0, or become 0 from 1, thus soft error occurs, cause system crash, therefore, antijamming capability be poor, data reliability and security lower; System power dissipation is comparatively large, chips close degree is poor.
2. based on the FPGA that Flash (quick flashing electrically erasable programmable ROM) technology is configured, refer in quick flashing EEPROM integrated in a kind of fpga chip that configuration data is write direct, use quick flashing EEPROM (electrically erasable programmable ROM) to carry out config memory SRAM again, thus make FPGA realize specific circuit function.Its shortcoming is: power consumption is larger; Easy generation soft error, antijamming capability is poor, data security and reliability lower; Data hold time is of a specified duration not.
3., based on antifuse (programming makes the point originally the do not connected together couple together) FPGA that technology is configured, be in a kind of configuration memory cell that configuration data is write direct in FPGA, thus make FPGA realize particular electrical circuit function.Here the configuration memory cell of FPGA selects disposable programmable (OTP) storer.At present, disposable programmable (OTP) storage unit circuit structure is mainly divided into two kinds:
One is floating gate structure, as not having the PROM of the conventional floating gate structure of transparency window (transparency window chip package top is used for receiving ultraviolet to realize the glass window of data erase), just can not wipe, until data disappear automatically after its write.There are two grids stacked in this MOS (metal-oxide semiconductor (MOS)) pipe, a grid is floating boom below, its principle is by adding certain high voltage between the source electrode and drain electrode of metal-oxide-semiconductor, charge carrier is made to enter on floating boom, after programming terminates, these charge carriers are bound on floating boom, thus change the threshold voltage (grid voltage needed for metal-oxide-semiconductor unlatching) of this metal-oxide-semiconductor, realize data and store.The shortcoming of this structure is being subject to, as during the external environmental interference such as ultraviolet light, high energy particle, microwave, loss of data easily occurs, data security and reliability lower, and, As time goes on, electric charge on floating boom slowly can reduce disappearance automatically, so its data hold time is of a specified duration not.
Two is that grid oxide layer punctures structure; As three pipe OTP memory cell structures; the uppermost metal-oxide-semiconductor for puncturing; middle is protection metal-oxide-semiconductor; nethermost is cell enable pipe; its principle by whether puncturing (load certain voltage at its grid (G) and source-drain electrode (S, D) and make its grid and source-drain electrode break-through, after puncturing, this metal-oxide-semiconductor is just equivalent to the effect of a resistance) uppermost metal-oxide-semiconductor stores to realize data; puncture and then stored data 1, do not punctured and then store data 0.The shortcoming that this cellular construction exists is: after having programmed; middle protection tube is opened; nethermost selection pipe is closed; when storing 0, its memory location (below middle protection tube) is vacant state in fact; although there is not electric charge after giving tacit consent to this position initialization; for data 0; but when suffering as external environmental interference such as ultraviolet light, high energy particle, microwaves; very easily there is soft error; cause data falsification, be not suitable for requiring that the occasion of configuration data high reliability is used as the configuration memory cell of FPGA.
Therefore, all require higher application scenario in data security, reliability, programmable memory cell of the prior art can not well meet the demands; And there is DC channel during programmable memory cell work of the prior art, can quiescent dissipation be produced, be unfavorable for carrying out low power dissipation design.
Summary of the invention
The invention provides a kind of programmable memory cell circuit for FPGA, solve in prior art for the programmable memory cell circuit safety of FPGA, technical matters that reliability is on the low side.
For solving the problems of the technologies described above, the present invention by the following technical solutions:
For a programmable memory cell circuit of FPGA, comprise memory location, power supply; Described memory location is connected by the first irreversible programming interface unit with ground; Described memory location is connected by the second irreversible programming interface unit with power supply; After described storage unit circuit is programmed for 0, described memory location is forever connected with ground by irreversible being programmed for by described first irreversible programming interface unit; After described storage unit circuit is programmed for 1, described memory location is forever connected with power supply by irreversible being programmed for by described second irreversible programming interface unit.
Also be included in described memory location and connect an interconnection box, the current potential of described memory location is for controlling the opening and closing of described interconnection box, and when described memory location is connected to ground, described interconnection box is closed, when described memory location is connected to power supply, described interconnection box is opened.
Described first irreversible programming interface unit comprises: the first PMOS transistor, the first anti-fuse cell and the first nmos pass transistor, the source electrode of described first PMOS transistor connects power supply, the grid of described first PMOS transistor and the grid of described first nmos pass transistor are connected to bit line, a pole ground connection in the source-drain electrode of described first nmos pass transistor, the drain electrode of another pole and described first PMOS transistor is connected to described first anti-fuse cell one end, and the described first anti-fuse cell other end is connected to described memory location.
Described first anti-fuse cell is the metal-oxide-semiconductor that first grid oxygen can puncture, a pole ground connection in the source-drain electrode of described first nmos pass transistor, the drain electrode of another pole and described first PMOS transistor is connected to the metal-oxide-semiconductor grid that described first grid oxygen can puncture, and the source electrode of the metal-oxide-semiconductor that described first grid oxygen can puncture and/or drain electrode are connected to described memory location.
Described second irreversible programming interface unit comprises: the second PMOS transistor and the second anti-fuse cell, the source electrode of described second PMOS transistor connects power supply, the grid of described second PMOS transistor is connected to described bit line by a phase inverter, the drain electrode of described second PMOS transistor is connected to described second anti-fuse cell one end, and the described second anti-fuse cell other end is connected to described memory location.
Described second anti-fuse cell is the metal-oxide-semiconductor that second gate oxygen can puncture, the drain electrode of described second PMOS transistor is connected to the grid of the metal-oxide-semiconductor that described second gate oxygen can puncture, and the source electrode of the metal-oxide-semiconductor that described second gate oxygen can puncture and/or drain electrode are connected to described memory location.
Described programmable memory cell circuit also comprises Read-write Catrol interface circuit, one end of described Read-write Catrol interface circuit connects described bit line, the grid of described first PMOS transistor and the grid of described first nmos pass transistor are connected to the other end of described Read-write Catrol interface circuit, and the grid of described second PMOS transistor is connected to the other end of described Read-write Catrol interface circuit by a phase inverter.
Described Read-write Catrol interface circuit comprises: the 3rd PMOS transistor, the 4th PMOS transistor, the second nmos pass transistor and the 3rd nmos pass transistor, and described 3rd PMOS transistor, the 4th PMOS transistor, the second nmos pass transistor are connected with the grid of the 3rd nmos pass transistor;
The drain electrode of described 3rd PMOS transistor is connected to power supply, source electrode is connected with the source electrode of described second nmos pass transistor, between the source electrode that the grid of described first PMOS transistor and the grid of described first nmos pass transistor are connected to described 3rd PMOS transistor and the source electrode of described second nmos pass transistor, between the source electrode that the grid of described second PMOS transistor is connected to described 3rd PMOS transistor by a phase inverter and the source electrode of described second nmos pass transistor;
The drain electrode of described second nmos pass transistor is connected with the drain electrode of described 4th PMOS transistor, and the drain electrode of described second nmos pass transistor is connected bit line with between the drain electrode of described 4th PMOS transistor;
The source electrode of described 4th PMOS transistor is connected with the drain electrode of described 3rd nmos pass transistor, the source ground of described 3rd nmos pass transistor.
Described second irreversible programming interface unit comprises: the 4th nmos pass transistor and the second anti-fuse cell, the drain electrode of described 4th nmos pass transistor connects power supply, the grid of described 4th nmos pass transistor is connected to described bit line, the source electrode of described 4th nmos pass transistor is connected to described second anti-fuse cell one end, and the described second anti-fuse cell other end is connected to described memory location.
Described programmable memory cell circuit also comprises Read-write Catrol interface circuit, one end of described Read-write Catrol interface circuit is connected to described bit line, the grid of described first PMOS transistor and the grid of described first nmos pass transistor are connected to the other end of described Read-write Catrol interface circuit, and the grid of described 4th nmos pass transistor is connected to the other end of described Read-write Catrol interface circuit.
The invention provides a kind of programmable memory cell circuit for FPGA, this storage unit circuit is after being programmed for 0, and memory location current potential is forever pulled down to ground, and after being programmed for 1, memory location current potential is forever pulled upward to power supply, and the present invention has the following advantages:
1. radioresistance antijamming capability is strong.When being subject to as external environmental interference such as ultraviolet light, high energy particle, microwaves, this storage unit circuit meeting generation current, and this electric current can be absorbed by power supply rapidly, be not easy to make the current potential of memory location to change, cause error in data, therefore, its Flouride-resistani acid phesphatase antijamming capability is strong, not easily cause loss of data, be particularly suitable in all exigent application scenario application of data security, reliability, as aerospace field;
2. there is not DC channel when this storage unit circuit is used as FPGA configuration, therefore, do not have quiescent dissipation, operating power consumption is lower;
3., because after being programmed for 0, memory location current potential is forever pulled down to ground, and after being programmed for 1, memory location current potential is forever pulled upward to power supply, and namely the current potential of data 1 and 0 is all fixing, so data reliability is high;
4. in appearance, the metal-oxide-semiconductor through programming and do not programme, without obvious difference, is easy to encryption, further ensures data security.
Therefore, the present invention is used for the programmable memory cell circuit data security of FPGA, confidentiality, reliability are height, and are reduced power consumption, is particularly useful for the applications that data security, confidentiality, reliability, power consumption requirements are very high.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the programmable memory cell circuit for FPGA of a kind of read-write pattern of the embodiment of the present invention;
Fig. 2 a schematic equivalent circuit that to be a kind of programmable memory cell circuit programming for FPGA of the embodiment of the present invention be after 1;
Fig. 2 b schematic equivalent circuit that to be a kind of programmable memory cell circuit programming for FPGA of the embodiment of the present invention be after 0;
Fig. 3 is the schematic diagram for Read-write Catrol interface circuit in the programmable memory cell circuit of FPGA of a kind of read-write pattern of the embodiment of the present invention;
Fig. 4 is the schematic diagram of the programmable memory cell circuit for FPGA of a kind of read-write pattern of another embodiment of the present invention;
Fig. 5 is the schematic diagram of the programmable memory cell circuit for FPGA of a kind of read-write pattern of another embodiment of the present invention;
Fig. 6 is the schematic diagram of the programmable memory cell circuit for FPGA of a kind of read-write pattern of another embodiment of the present invention;
Fig. 7 is that the embodiment of the present invention is a kind of can not the schematic diagram of the programmable memory cell circuit for FPGA of read-write mode;
Fig. 8 is that another embodiment of the present invention is a kind of can not the schematic diagram of the programmable memory cell circuit for FPGA of read-write mode;
Fig. 9 is that another embodiment of the present invention is a kind of can not the schematic diagram of the programmable memory cell circuit for FPGA of read-write mode;
Figure 10 is that another embodiment of the present invention is a kind of can not the schematic diagram of the programmable memory cell circuit for FPGA of read-write mode.
Embodiment
By reference to the accompanying drawings the present invention is described in further detail below by embodiment.
Embodiment one:
For a programmable memory cell circuit of FPGA, comprise memory location, power supply; Described memory location is connected by the first irreversible programming interface unit with ground; Described memory location is connected by the second irreversible programming interface unit with power supply; After described storage unit circuit is programmed for 0, described memory location is forever connected with ground by irreversible being programmed for by described first irreversible programming interface unit; After described storage unit circuit is programmed for 1, described memory location is forever connected with power supply by irreversible being programmed for by described second irreversible programming interface unit.Namely described storage unit circuit is after being programmed for 0, and memory location current potential is forever pulled down to ground, and after being programmed for 1, memory location current potential is forever pulled upward to power supply.
Fig. 1 is the schematic diagram of the programmable memory cell circuit for FPGA of a kind of read-write pattern of the embodiment of the present invention, please refer to Fig. 1:
Comprise the first PMOS transistor M1, the second PMOS transistor M2, metal-oxide-semiconductor M4, the first nmos pass transistor M5 that metal-oxide-semiconductor M3 that first grid oxygen can puncture, second gate oxygen can puncture, also comprise cell enable pipe and interconnection box, nmos pass transistor M6 and nmos pass transistor M7.
The metal-oxide-semiconductor M3 that in the present embodiment, the first PMOS transistor M1, first grid oxygen can puncture, the first nmos pass transistor M5 form the first irreversible programming interface unit, the metal-oxide-semiconductor M4 that second PMOS transistor M2 and second gate oxygen can puncture forms the second irreversible programming interface unit, PMOS (P type metal-oxide-semiconductor field effect t, the hole of positively charged is as charge carrier, PMOS conducting when grid adds low level 0, turn off when adding high level 1), because in programming process, M1 and M2 needs to bear larger voltage, therefore, it is relatively thick that its gate oxide thickness can be set; M5, M6, M7 be NMOS tube (N-type metal-oxide-semiconductor field effect t, electronegative electronics is as charge carrier; NMOS tube conducting when grid adds high level 1, turns off when adding low level 0; The circuit that simultaneously there is PMOS and NMOS tube is then the circuit of CMOS technology realization); M3, M4 are the metal-oxide-semiconductor that grid oxygen can puncture; In Fig. 1 A with
termination enters to read and write control interface,
hold the opposite signal for A end, when namely A is high level,
for low level, when A is low level,
for high level; B termination enters to read and write control interface.
In the present embodiment, M1, M2, M3, M4, M5, M6 and M7 are the metal-oxide-semiconductor of source-drain electrode equity, M5 is the lower trombone slide that on same bit line, each storage unit is shared, its effect is after programming terminates, the grid potential dragging down the metal-oxide-semiconductor that coupled grid oxygen can puncture arrive (GND), M6 can be cell enable pipe (this unit is selected) be again protection tube (prevent electric current in programming process is excessive burns circuit), so its breadth length ratio should be relatively larger, connect program voltage (generally high than normal power voltage) during the programming of VPP end, when normally working, connect normal power voltage, BL is dual-port bit line, i.e. bidirectional data line, when programming as data input port, when reading as data output, WL is wordline or claims address wire, Ctrl end is memory location, by judging that the current potential of the rear Ctrl end of programming can know the data of storage, as the current potential of Ctrl end is 0 after programming, can know that the data of storage are 0, Ctrl end is also the control end that data store, for controlling the opening and closing of interconnection box pipe M7, when Ctrl end is for high level, M7 opens, when Ctrl end is for low level, M7 closes, the height of M7 grid level controls connection or the disconnection of interconnector that its source-drain electrode connects or circuit module, therefore, programmable memory cell circuit of the present invention not only can be used for the storage of data, also can be used to the open and close controlling interconnection box, thus the connection of control FPGA interconnector whether, programmable memory cell circuit of the present invention is due to after one-time programming, M3 or M4 will be destroyed formation resistance, and is no longer metal-oxide-semiconductor, and therefore, programmable memory cell circuit of the present invention is one-time programming circuit.
The main working process of the programmable memory cell circuit of the present embodiment comprises:
VPP is program voltage, and all data BL on this address wire WL all ready after, WL end adds 1/2VPP voltage, and programmable memory cell circuit starts programming, if BL=1, then M2 opens, and M1 turns off, and M5 opens, and M4 pipe grid oxide layer is breakdown, forms resistance and connects; If BL=0, then M1 opens, and M2 turns off, and M5 turns off, and M3 pipe grid oxide layer is breakdown, forms resistance and connects; The each unit be connected on same WL line completes programming simultaneously, and the wordline WL of other programmable memory cells of not programming in FPGA keeps low level;
After whole unit programming terminates, change VPP into normal power voltage, all wordline WL are set to low level, and now, M2 and M5 opens, M1 and M6 turns off, if be programmed for 1, M4 before this punctured the connection of formation resistance, then Ctrl terminal potential is pulled upward to VPP by the M2 pipe opened, its equivalent electrical circuit as shown in Figure 2 a, Fig. 2 a schematic equivalent circuit that to be a kind of programmable memory cell circuit programming for FPGA of the embodiment of the present invention be after 1; If be programmed for 0 before this, M3 has punctured formation resistance and has connected, then Ctrl terminal potential pulls down to GND by the M5 pipe opened, its equivalent electrical circuit as shown in Figure 2 b, Fig. 2 b schematic equivalent circuit that to be a kind of programmable memory cell circuit programming for FPGA of the embodiment of the present invention be after 0.
Fig. 3 is the schematic diagram for Read-write Catrol interface circuit in the programmable memory cell circuit of FPGA of a kind of read-write pattern of the embodiment of the present invention, please refer to Fig. 3:
The Read-write Catrol interface circuit of the present embodiment comprises the 3rd PMOS transistor M8, the 4th PMOS transistor M9, the second nmos pass transistor M10 and the 3rd nmos pass transistor M11;
3rd PMOS transistor M8, the 4th PMOS transistor M9, the second nmos pass transistor M10 are connected with the grid of the 3rd nmos pass transistor M11;
The drain electrode of the 3rd PMOS transistor M8 is connected to power vd D, source electrode is connected with the source electrode of the second nmos pass transistor M10, the grid of the first PMOS transistor M1 and the grid of the first nmos pass transistor M5 are connected between the source electrode of the 3rd PMOS transistor M8 and the source electrode of the second nmos pass transistor M10, and the grid of the second PMOS transistor M2 is connected between the source electrode of the 3rd PMOS transistor M8 and the source electrode of the second nmos pass transistor M10 by a phase inverter;
The drain electrode of the second nmos pass transistor M10 is connected with the drain electrode of the 4th PMOS transistor M9, is connected bit line BL at the drain electrode M10 of the second nmos pass transistor with between the drain electrode of the 4th PMOS transistor M9;
The source electrode of the 4th PMOS transistor M9 is connected with the drain electrode of the 3rd nmos pass transistor M11, a connection memory location, pole in the source-drain electrode of the second nmos pass transistor, another pole is connected between the source electrode of the 4th PMOS transistor M9 and the drain electrode of the 3rd nmos pass transistor M11, the source ground of the 3rd nmos pass transistor M11.
Its principle of work is, before entering programming state, CE end be set to noble potential, now M8 and M9 close, M10 and M11 opens, data BL by M10 pipe be loaded into A and
end; Meanwhile, the M11 pipe ground connection of B port by opening; Unit enters programming mode.
After unit is all programmed and terminated, CE termination is low level, and now M8 and M9 opens, M10 and M11 closes, and now A port connects power supply by the M8 opened, thus M2 and M5 is opened all the time, and M1 closes all the time, thus realizes the store status that data hold at Ctrl; B port receives BL end by the M9 opened, now, and the upper data that can export corresponding selected storage unit of BL.
The programmable memory cell circuit realiration of the present embodiment data store and by the opening and closing of programming to interconnection box, can ensure after being programmed for 0, memory location current potential is forever pulled down to ground, after being programmed for 1, memory location current potential is forever pulled upward to power supply, therefore radioresistance antijamming capability is strong, and data security, reliability are high; DC channel is there is not, without quiescent dissipation in course of normal operation; In appearance, the metal-oxide-semiconductor through programming and do not programme, without obvious difference, is easy to encryption, further ensures data security.
Embodiment two:
Fig. 4 is the schematic diagram of the programmable memory cell circuit for FPGA of a kind of read-write pattern of another embodiment of the present invention, please refer to Fig. 4:
The present embodiment with the difference of embodiment one is: in embodiment one, the source electrode of M3 and M4 is connected and is connected to memory location, the drain electrode of M3 and M4 is all unsettled, and in the present embodiment, the source electrode of M3 and M4 is connected, drain electrode is connected, the source electrode of M3 and M4 is connected to memory location, and the drain electrode of M3 and M4 is also connected to memory location.
Embodiment three:
Fig. 5 is the schematic diagram of the programmable memory cell circuit for FPGA of a kind of read-write pattern of another embodiment of the present invention, please refer to Fig. 5:
The present embodiment with the difference of embodiment one is: the source electrode of M3 and M4 is connected, and drain electrode is connected, and when the source electrode of M3 and M4 is connected to memory location, the drain electrode of M3 and M4 is connected to WL wordline, together can be connected to wordline WL with the grid of M6.
The present embodiment realizes and while other each embodiment identical functions, can also shorten programming time.In actual application, when can also say that the drain electrode of M3 and M4 is connected to memory location, the source electrode of M3 and M4 is connected to wordline WL.
Embodiment four:
Fig. 6 is the schematic diagram of the programmable memory cell circuit for FPGA of a kind of read-write pattern of another embodiment of the present invention, please refer to Fig. 6:
The difference of the present embodiment and embodiment two is: in embodiment two, M1 and M2 is PMOS, and the source electrode of M1 meets VPP, and grid meets A, and drain electrode connects the grid of M3, and the source electrode of M2 meets VPP, and grid connects
drain electrode connects the grid of M4, and in the present embodiment, change M2 into NMOS tube, the drain electrode of M2 meets VPP, and source electrode connects the grid of M4, and the grid of M1, M2, M5 is all connected to A end, and the present embodiment eliminates
end, M1, M2, M5 are all by the control of A end signal, and during programming, if A end input data are 1, then M2 and M5 opens, and M1 turns off, thus the breakdown formation resistance of M4 connects; If A end input data are 0, then M1 opens, and M2 and M5 turns off, thus the breakdown formation resistance of M3 connects; After programming terminates, A end sets high level, and WL establishes low level.Finally can realize the function that embodiment each with other is identical.
Embodiment five:
Fig. 7 is that the embodiment of the present invention is a kind of can not the schematic diagram of the programmable memory cell circuit for FPGA of read-write mode, please refer to Fig. 7:
Because there is not read port in not read-write programmable memory cell circuit, so data cannot read, improve the security of data, each metal-oxide-semiconductor that the not read-write programmable memory cell circuit of the present embodiment uses is identical with the metal-oxide-semiconductor of the read-write pattern that embodiment one describes, VPP end adds program voltage when programming, and adds normal power voltage during normal work.BL is bit line,
for the opposite signal of bit line, when namely BL is high level,
for low level, when BL is low level,
for high level, be: in the present embodiment with embodiment one difference, the grid of M1 directly meets bit line BL, and the grid of M2 connects anti-phase bit line
the source ground of M6, the present embodiment can not the main working process on programmable memory cell circuit road of read-write mode comprise:
When VPP is program voltage, and all data BL on this address wire WL all ready after, WL end adds 1/2VPP voltage, and this unit starts programming, if BL=1, then M2 opens, and M1 turns off, and M5 opens, and M4 grid oxide layer is breakdown, forms resistance and connects; If BL=0, then M1 opens, M2 and M5 turns off, and M3 grid oxide layer is breakdown, forms resistance and connects; The each unit be connected on same WL line completes programming simultaneously, and the wordline WL of other programmable memory cells of not programming in FPGA keeps low level;
After whole unit programming terminates, change VPP into normal power voltage, all wordline WL are set to low level, all bit line BL are set to high level, now M2 and M5 opens, M1 and M6 turns off, if be programmed for 1 before this, then M4 has punctured the connection of formation resistance, Ctrl terminal potential is pulled upward to VPP by the M2 pipe opened, its equivalent electrical circuit as shown in Figure 2 a, Fig. 2 a schematic equivalent circuit that to be a kind of programmable memory cell circuit programming for FPGA of the embodiment of the present invention be after 1, if be programmed for 0 before this, then M3 has punctured the connection of formation resistance, then Ctrl terminal potential pulls down to GND by the M5 pipe opened, its equivalent electrical circuit as shown in Figure 2 b, Fig. 2 b schematic equivalent circuit that to be a kind of programmable memory cell circuit programming for FPGA of the embodiment of the present invention be after 0, so achieve data storage and the opening and closing by programming Control M7, and there is not DC channel in course of normal operation, without quiescent dissipation.
Embodiment six:
Fig. 8 is that another embodiment of the present invention is a kind of can not the schematic diagram of the programmable memory cell circuit for FPGA of read-write mode, please refer to Fig. 8:
The present embodiment with the difference of embodiment five is: in embodiment five, the source electrode of M3 and M4 is connected and is connected to memory location, the drain electrode of M3 and M4 is all unsettled, and in the present embodiment, the source electrode of M3 and M4 is connected, drain electrode is connected, the source electrode of M3 and M4 is connected to memory location, and the drain electrode of M3 and M4 is also connected to memory location.
Embodiment seven:
Fig. 9 is that another embodiment of the present invention is a kind of can not the schematic diagram of the programmable memory cell circuit for FPGA of read-write mode, please refer to Fig. 9:
The present embodiment with the difference of embodiment five is: the source electrode of M3 and M4 is connected, and drain electrode is connected, and when the source electrode of M3 and M4 is connected to memory location, the drain electrode of M3 and M4 is connected to wordline, also together can be connected to wordline WL with the grid of M6.
The present embodiment realizes and while other each embodiment identical functions, can also shorten programming time.In actual application, the drain electrode of M3 and M4 can also be connected to memory location, the source electrode of M3 and M4 is connected to wordline WL.
Embodiment eight:
Figure 10 is that another embodiment of the present invention is a kind of can not the schematic diagram of the programmable memory cell circuit for FPGA of read-write mode, please refer to Figure 10:
The difference of the present embodiment and embodiment six is: in embodiment five, M1 and M2 is PMOS, and the source electrode of M1 meets VPP, and grid meets BL, and drain electrode connects the grid of M3, and the source electrode of M2 meets VPP, and grid connects
drain electrode connects the grid of M4, and in the present embodiment, change M2 into NMOS tube, the drain electrode of M2 meets VPP, and source electrode connects the grid of M4, and the grid of M1, M2, M5 is all connected to BL, and the present embodiment eliminates
setting, M1, M2, M5 are all by the control of BL signal, and during programming, if BL=1, then M2 and M5 opens, and M1 turns off, thus the breakdown formation resistance of M4 connects; If BL=0, then M1 opens, and M2 and M5 turns off, thus the breakdown formation resistance of M3 connects; After programming terminates, BL sets high level, and WL establishes low level.Finally can realize the function that embodiment each with other is identical.
Above content is in conjunction with concrete embodiment further description made for the present invention, can not assert that specific embodiment of the invention is confined to these explanations.For general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, some simple deduction or replace can also be made, all should be considered as belonging to protection scope of the present invention.
Claims (9)
1., for a programmable memory cell circuit of FPGA, it is characterized in that, comprise memory location, power supply; Described memory location is connected by the first irreversible programming interface unit with ground; Described memory location is connected by the second irreversible programming interface unit with power supply; After described storage unit circuit is programmed for 0, described memory location is forever connected with ground by irreversible being programmed for by described first irreversible programming interface unit; After described storage unit circuit is programmed for 1, described memory location is forever connected with power supply by irreversible being programmed for by described second irreversible programming interface unit; Also be included in described memory location and connect an interconnection box, the current potential of described memory location is for controlling the opening and closing of described interconnection box, and when described memory location is connected to ground, described interconnection box is closed, when described memory location is connected to power supply, described interconnection box is opened.
2. programmable memory cell circuit as claimed in claim 1, it is characterized in that, described first irreversible programming interface unit comprises: the first PMOS transistor, first anti-fuse cell and the first nmos pass transistor, the source electrode of described first PMOS transistor connects power supply, the grid of described first PMOS transistor and the grid of described first nmos pass transistor are connected to bit line, a pole ground connection in the source-drain electrode of described first nmos pass transistor, the drain electrode of another pole and described first PMOS transistor is connected to described first anti-fuse cell one end, the described first anti-fuse cell other end is connected to described memory location.
3. programmable memory cell circuit as claimed in claim 2, it is characterized in that, described first anti-fuse cell is the metal-oxide-semiconductor that first grid oxygen can puncture, a pole ground connection in the source-drain electrode of described first nmos pass transistor, the drain electrode of another pole and described first PMOS transistor is connected to the metal-oxide-semiconductor grid that described first grid oxygen can puncture, and the source electrode of the metal-oxide-semiconductor that described first grid oxygen can puncture and/or drain electrode are connected to described memory location.
4. programmable memory cell circuit as claimed in claim 3, it is characterized in that, described second irreversible programming interface unit comprises: the second PMOS transistor and the second anti-fuse cell, the source electrode of described second PMOS transistor connects power supply, the grid of described second PMOS transistor is connected to described bit line by a phase inverter, the drain electrode of described second PMOS transistor is connected to described second anti-fuse cell one end, and the described second anti-fuse cell other end is connected to described memory location.
5. programmable memory cell circuit as claimed in claim 4, it is characterized in that, described second anti-fuse cell is the metal-oxide-semiconductor that second gate oxygen can puncture, the drain electrode of described second PMOS transistor is connected to the grid of the metal-oxide-semiconductor that described second gate oxygen can puncture, and the source electrode of the metal-oxide-semiconductor that described second gate oxygen can puncture and/or drain electrode are connected to described memory location.
6. programmable memory cell circuit as claimed in claim 5, it is characterized in that, described programmable memory cell circuit also comprises Read-write Catrol interface circuit, one end of described Read-write Catrol interface circuit connects described bit line, the grid of described first PMOS transistor and the grid of described first nmos pass transistor are connected to the other end of described Read-write Catrol interface circuit, and the grid of described second PMOS transistor is connected to the other end of described Read-write Catrol interface circuit by a phase inverter.
7. programmable memory cell circuit as claimed in claim 6, it is characterized in that, described Read-write Catrol interface circuit comprises: the 3rd PMOS transistor, the 4th PMOS transistor, the second nmos pass transistor and the 3rd nmos pass transistor, and described 3rd PMOS transistor, the 4th PMOS transistor, the second nmos pass transistor are connected with the grid of the 3rd nmos pass transistor;
The drain electrode of described 3rd PMOS transistor is connected to power supply, source electrode is connected with the source electrode of described second nmos pass transistor, between the source electrode that the grid of described first PMOS transistor and the grid of described first nmos pass transistor are connected to described 3rd PMOS transistor and the source electrode of described second nmos pass transistor, between the source electrode that the grid of described second PMOS transistor is connected to described 3rd PMOS transistor by a phase inverter and the source electrode of described second nmos pass transistor;
The drain electrode of described second nmos pass transistor is connected with the drain electrode of described 4th PMOS transistor, and the drain electrode of described second nmos pass transistor is connected bit line with between the drain electrode of described 4th PMOS transistor;
The source electrode of described 4th PMOS transistor is connected with the drain electrode of described 3rd nmos pass transistor, the source ground of described 3rd nmos pass transistor.
8. programmable memory cell circuit as claimed in claim 2, it is characterized in that, described second irreversible programming interface unit comprises: the 4th nmos pass transistor and the second anti-fuse cell, the drain electrode of described 4th nmos pass transistor connects power supply, the grid of described 4th nmos pass transistor is connected to described bit line, the source electrode of described 4th nmos pass transistor is connected to described second anti-fuse cell one end, and the described second anti-fuse cell other end is connected to described memory location.
9. programmable memory cell circuit as claimed in claim 8, it is characterized in that, described programmable memory cell circuit also comprises Read-write Catrol interface circuit, one end of described Read-write Catrol interface circuit is connected to described bit line, the grid of described first PMOS transistor and the grid of described first nmos pass transistor are connected to the other end of described Read-write Catrol interface circuit, and the grid of described 4th nmos pass transistor is connected to the other end of described Read-write Catrol interface circuit.
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| CN103761991B (en) * | 2013-12-30 | 2017-02-22 | 深圳市国微电子有限公司 | Lookup table and lookup table circuit for programmable chip |
| CN110968451B (en) * | 2018-09-30 | 2021-09-21 | 华为技术有限公司 | Memory access technology and computer system |
| CN112582013A (en) | 2019-09-29 | 2021-03-30 | 长鑫存储技术有限公司 | Anti-fuse memory cell circuit, array circuit and read-write method thereof |
| CN111723045B (en) * | 2020-06-19 | 2023-05-16 | 成都华微电子科技股份有限公司 | Multifunctional memory circuit and integrated circuit chip |
| CN116566373B (en) * | 2023-07-10 | 2023-09-12 | 中国电子科技集团公司第五十八研究所 | High-reliability anti-radiation anti-fuse switch unit structure |
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