CN102956175B - Display floater and driving device - Google Patents
Display floater and driving device Download PDFInfo
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- CN102956175B CN102956175B CN201110239098.2A CN201110239098A CN102956175B CN 102956175 B CN102956175 B CN 102956175B CN 201110239098 A CN201110239098 A CN 201110239098A CN 102956175 B CN102956175 B CN 102956175B
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Abstract
The invention discloses a kind of driving device, the plural number that its plural number driver element produces sequentially to be enabled according to plural number clock signal drives signal.Each driver element produces at least two driving signals and includes drive circuit, first and second output circuit and holding circuit.Control circuit produces the first control signal and the second control signal.First output circuit produces the first driving signal, and carrys out enable first according to the first control signal and first and second clock signal and drive signal.Second output circuit produces two driving signal, and carrys out enable two driving signal according to the first control signal and the 3rd and the 4th clock signal.First and second drives signal system to be sequentially enabled.
Description
Technical field
Present invention is directed to a kind of driving device, in particular to a kind of configuration driving device on a display panel, the exportable multiple drive power signal of every one-level driver element in this driving device is to array of display.
Background technology
In a liquid crystal display, gate drivers it is generally of to drive display floater show image.In known techniques, it is to drive display floater mostly with one or more grid-driving integrated circuit.Along with the manufacturing cost of display reduces and the demand of production cycle point reduction, develop the integrated gate drivers of non-crystalline silicon (amorphoussilicon (A-Si) integratedgatedriver, ASG).ASG technology system realizes array program (arrayprocess) to be integrated on a display panel by gate drivers with non-crystalline silicon processing procedure, and therefore ASG technology is also referred to as GOP (gatedriveronpanel).
Poly-Si thin film transistor (TFT) (thinfilmtransistor with known grid-driving integrated circuit, TFT) comparing, the A-SiTFT mobility (mobility) (0.5～1cm2/Vs) of GOP technology is only the 1/200～1/300 of Poly-SiTFT mobility (100～300cm2/Vs).Under identical drives ability premise, the size of A-SiTFT have to be larger than the size of Poly-SiTFT, and therefore the parasitic capacitance of A-SiTFT is also relatively big, causes that therefore the power consumption of the A-SiTFT gate driver circuit formed also increases.
Fig. 1 system represents the circuit of each driver element in the grid-driving integrated circuit of known GOP technology.Grid-driving integrated circuit includes the driver element of a plurality of Fig. 1, and each driver element 1 produces a driving signal Dout to a gate line of array of display, and includes control circuit 10, transistor Mb, Mc and MQ and capacitor Cc.Control circuit 10 produces control signal SP and SQ according to clock signal Clock_in and initial signal STV.The output circuit being made up of transistor Mb, Mc and MQ and capacitor Cc then carrys out enable according to control signal SP and SQ and clock signal Clock_in and drives signal Dout.In the driver element 1 of Fig. 1, owing to transistor Mb, Mc and MQ are A-SiTFT, therefore, in order to be able to reach preferably drives ability, the size of these transistors needs to increase so that grid-driving integrated circuit occupies area bigger on display floater.Additionally, the parasitic capacitance of transistor Mb, Mc and MQ is relatively big, cause that the power consumption of grid-driving integrated circuit increases.
Summary of the invention
In order to be able to solve the problem that known techniques causes, the present invention provides a kind of driving device, and it includes plural number driver element.Plural number driver element exports generation plural number according to plural number clock signal CK1～CKj and drives signal D1～Dn.Driving signal D1～Dn to be sequentially enabled, j, n are respectively a positive integer.Clock signal CKi+1 with a unit interval postpone in clock signal CKi, i be a positive integer and 1≤i≤j-1.Each driver element produces to drive at least two driving signal in signal D1～Dn.Each driver element includes drive circuit, the first output circuit, the second output circuit and holding circuit.Control circuit produces one first control signal and one second control signal.First output circuit produces to drive in signal D1～Dn one first to drive signal, and carrys out enable first according to one first clock signal and one second clock signal in the first control signal and clock signal CK1～CKj and drive signal.Second output circuit produces to drive the two driving signal in signal D1～Dn, and carrys out enable two driving signal according to one the 3rd clock signal and one the 4th clock signal in the first control signal and clock signal CK1～CKj.First drives signal and two driving signal to be sequentially enabled.
The present invention separately provides a kind of display floater, and it includes Gate line, plural number source electrode line and plural number driver element.Gate lines G L1～GLn sequentially configures with a first direction, and n is a positive integer.Plural number source electrode line, sequentially configures with a second direction, and is staggered to form an array of display with gate lines G L1～GLn.It is a positive integer that plural number driver element produces to drive signal D1～Dn, j according to plural number clock signal CK1～CKj.Driving signal D1～Dn is provided to gate lines G L1～GLn by these driver elements respectively, and drives signal D1～Dn to be sequentially enabled.Arteries and veins signal CKi+1 with a unit interval postpone in clock signal CKi, i be a positive integer and 1≤i≤j-1.In each generation driving signal D1～Dn in driver element, at least two drive signals and include control circuit, the first output circuit, the second output circuit and holding circuit.Control circuit produces one first control signal and one second control signal.First output circuit produces to drive in signal D1～Dn one first to drive signal, and carrys out enable first according to one first clock signal and one second clock signal in the first control signal and clock signal CK1～CKj and drive signal.Second output circuit produces to drive the two driving signal in signal D1～Dn, and carrys out enable two driving signal according to one the 3rd clock signal and one the 4th clock signal in the first control signal and clock signal CK1～CKj.
In certain embodiments, plural number driver element divides into one first group and one second group.Each driving signal is produced by the first output circuit of the second output circuit of the one in the plural driver element belonging to first group and the one in belonging to the plural driver element of second group.
Accompanying drawing explanation
Fig. 1 represents the known circuit according to driver element each in grid-driving integrated circuit under GOP technology；
Fig. 2 represents display floater according to an embodiment of the invention；
Fig. 3 A and Fig. 3 B represents according to one embodiment of the invention, produces the detailed circuit that continuous print two drives a driver element of signal；
Fig. 4 represents Fig. 3 A, the initial signal of Fig. 3 B, clock signal, control signal and drives the waveform of signal；
Fig. 5 A and Fig. 5 B represents according to one embodiment of the invention, produces the detailed circuit of discrete two each driver elements driving signal；
Fig. 6 represents the driving device producing in display floater according to another embodiment of the present invention with controlling to drive signal；
Fig. 7 A and Fig. 7 B represents according to one embodiment of the invention, produces the detailed circuit that continuous print three drives each driver element of signal；
Fig. 8 represents initial signal in Fig. 7 A, Fig. 7 B, clock signal, control signal and drives the waveform of signal；
Fig. 9 A and Fig. 9 B represents according to one embodiment of the invention, produces the detailed circuit of discrete three each driver elements driving signal；And
Figure 10 represents display floater according to another embodiment of the present invention.
Main element symbol description:
2～display floater；
10～control circuit；
20～array of display；
21,22～driving device；
30～control circuit；
31,32～output circuit；
33～holding circuit；
100～driving device；
Cc, Cc1, Cc2～capacitor；
CK1...CKj, Clock_in～clock signal；
D1...Dn, Dout～drive signal；
DIR30, DIR31～direction；
GL1...GLn～gate line；
LU1...LUh～driver element；
Mb, Mb1, Mb2, Mc, Mc1, Mc2, MQ～transistor；
N20, N21, N22～node；
RU1...RUk～driver element；
SL1...SLm～source electrode line；
SLU～driver element；
STV～initial signal；
VGL～reference ground connection；
Detailed description of the invention
For making the above-mentioned purpose of the present invention, feature and advantage to become apparent, a preferred embodiment cited below particularly, and coordinate institute's accompanying drawings, it is described in detail below.
Fig. 2 system represents display floater according to an embodiment of the invention.Consulting Fig. 2, display floater 2 includes driving device 21 and 22, source electrode line SL1～SLm and gate lines G L1～GLn, and wherein, m, n are respectively a positive integer.Source electrode line SL1-SLm sequentially configures with direction DIR30, and gate lines G L1～GLn sequentially configures towards direction DIR31, and therefore gate lines G L1～GLn is with staggered, to form array of display 20.Driving device 22 is used for controlling SL1～SLm.Driving device 21 is arranged in the side of array of display 20, and to include driver element RU1～RUk, k be a positive integer.Driver element RU1～RUk output drive signal D1～Dn respectively to gate lines G L1～GLn to drive gate lines G L1～GLn, and driver element RU1～RUk carrys out enable according to clock signal CK1～CKj and initial signal STV or renvoi can drive signal D1～Dn, wherein j is a positive integer.Can learning according to Fig. 2, driving signal D1～Dn system is corresponding gate lines G L1～GLn respectively, and each driving signal is equal to the corresponding gate line ordinal number relative to gate line summation relative to the ordinal number driving signal sum.Each driver element produces at least two driving signal Dw and Dw+x, w and is a positive integer and 1≤w≤n-1, x is a positive integer and 1≤x≤n-w.In the embodiment of fig. 2, each driver element produces continuous print two and drives signal, i.e. x=1.For example, driver element RU1 produces two drivings signal D1 and D2 (w=1, x=1) respectively in node N20 and N21；Driver element RU2 produces two drivings signal D3 and D4 (w=3, x=1) respectively in node N20 and N21；Driver element RU3 produces two drivings signal D5 and D6 (w=5, x=1) respectively in node N20 and N21；Driver element RU4 produces two drivings signal D7 and D8 (w=7, x=1) respectively in node N20 and N21.Assuming when k and n is all even number, driver element RUk then produces two drivings signal Dn-1 and Dn (w=n-1, x=1) respectively in node N20 and N21.
The detailed circuit of each driver element of Fig. 3 A and Fig. 3 B system expression Fig. 2.In order to know explanation, Fig. 3 A, Fig. 3 B only represent the detailed circuit of driver element RU1～RU4, and in this embodiment, each driver element has identical circuit framework.Consulting Fig. 3 A, Fig. 3 B, each driver element includes control circuit 30, output circuit 31 and 32 and holding circuit 33.Control circuit 30 produces control signal SP and SQ respectively according to clock signal Clock_in and initial signal STV on node P and Q.Output circuit 31 produces to drive signal Dw to gate lines G L1, and carrys out enable driving signal Dw according to control signal SP and clock signal CK1.Output circuit 32 produces to drive signal Dw+x to gate lines G L2, and carrys out enable driving signal Dw+x according to control signal SP and clock signal CK2.
In this embodiment, it is illustrate with six clock signal CK1～CK6 (j=6).Fig. 4 system represents initial signal STV, clock signal CK1～CK6, control signal SP and SQ in the embodiment of Fig. 3 A, Fig. 3 B and drives the waveform of signal D1 and D2.Consult Fig. 4, clock signal CKi+1 to postpone in previous clock signal CKi mono-unit interval TD, wherein, i is a positive integer and 1≤i≤j-1.This case has six clock signal CK1～CK6.For example, clock signal CK2 (i=1) postpones in previous clock signal CK1 mono-unit interval TD.Additionally, due to the seriality of time, clock signal CK1 postpones in clock signal CK6 mono-unit interval TD, and clock signal CK2 postpones in two unit interval T of clock signal CK6D, by that analogy.Consulting Fig. 3 A, Fig. 3 B and Fig. 4, in each driver element, output circuit 31 includes transistor Mb1 and Mc1 and capacitor CC1.The grid of transistor Mb1 receives control signal SP, and its drain electrode receives a clock signal and its source electrode couple nodes N20.Between the grid of capacitor Cc1 coupling transistors Mb1 and source electrode.The grid of transistor Mc1 receives another clock signal, its couple nodes N20 that drains, and its source electrode couples with reference to ground connection VGL.A relatively low voltage level is provided with reference to ground connection VGL.Signal Dw is driven to result from node N20.Output circuit 32 includes transistor Mb2 and Mc2 and capacitor CC2.The grid of transistor Mb2 receives control signal SP, and its drain electrode receives a clock signal and its source electrode couple nodes N21.Between grid and the source electrode of capacitor Cc2 coupling transistors Mb2.The grid of transistor Mc2 receives another clock signal, its couple nodes N21 that drains, and its source electrode couples with reference to ground connection VGL.Signal Dw+x is driven to result from node N21.
Holding circuit 33 includes transistor MQ.The grid of transistor MQ receives the grid of control signal SQ, its couple nodes N20 that drains, and its source electrode and couples with reference to ground connection VGL.
In this embodiment, the sequential of several clock signals that each driver element receives and its driving signal correction exported connection.About the sequential of the clock signal received of transistor Mb1 and Mb2 in each driver element, in this embodiment, the clock signal that transistor Mb2 receives is with the unit interval T of given amountDPostpone in the transistor Mb1 clock signal received.Consult Fig. 3 A, Fig. 3 B and Fig. 4, for each driver element, when output unit 31 export drive signal be drive the w in signal D1～Dn to drive signal and output unit 32 export to drive signal be the w+x driving signal in driving signal D1～Dn time, given amount is equal to x.For example, in driver element RU1, output unit 31 is output drive signal D1 (w=1), output unit 32 output drive signal D2 (x=1), now, the enable sequential according to control signal D1 and D2, transistor Mb1 receives clock signal CK1, and transistor Mb2 receives clock signal CK2, wherein, clock signal CK2 is with (x=1) unit interval TDPostpone in clock signal CK1.
About the sequential of two clock signals that output unit each in a driver element receives, in embodiments of the present invention, two clock signals that each output unit receives all differ two unit interval TD.Specifically, in the output unit 31 of driver element RU1, clock signal CK3 postpones two unit interval T of clock signal CK1D, and in the output unit 32 of driver element RU1, clock signal CK4 postpones two unit interval T of clock signal CK2D。
In each driver element, the clock signal that the clock signal Clock_in that control circuit 30 receives receives with transistor Mb1 and Mc1 in output circuit 31 is associated.For example, in the output circuit 31 of driver element RU1, the drain electrode system of transistor Mb1 receives clock signal CK1, and transistor Mc1 receives clock signal CK3.Clock signal CK3 postpones two unit interval T of clock signal CK1D.In an embodiment, clock signal Clock_in is probably with two and or four unit interval TDPostpone a clock signal in clock signal CK1 or the combination of multiple clock signal.Therefore, the clock signal Clock_in that control circuit 30 receives in driver element RU1 can be at least both combination in CK1, CK3, CK5 or CK1, CK3 and CK5.In all the other driver elements, the clock signal Clock_in that control circuit 30 receives according to above-mentioned logic to analogize acquisition.
The operation of driver element will be described for driver element RU1 below.All the other driver elements produce respective driving signal through the clock signal of following same operation and correspondence.Consulting Fig. 3 A, Fig. 3 B and Fig. 4, when time point T1, initial signal STV is enabled (being become high levels from low being as the criterion), and the initial signal STV of enable is sent to node P by control circuit 30, and control signal SP now is become LV2 from level LV1.Transistor Mb1 turns on according to the control signal SP with level LV2.But during time point T1 to T2, clock signal CK1 is in anti-enabled status (low level), therefore, transistor Mb1, control signal D1 through conducting are also at anti-enabled status (low level).Additionally, transistor Mb2 turns on also according to the control signal SP with level LV2.But during time point T1 to T2, clock signal CK2 is in anti-enabled status, therefore, transistor Mb2, control signal D2 through conducting are also at anti-enabled status.
When time point T2, clock signal CK1 is enabled (being become high levels from low being as the criterion), due to the capacitance coupling effect that the lock-drain parasitic capacitance (Cgd) of capacitor Cc1 and transistor Mb1 and lock-source electrode parasitic capacitance (Cgs) in output unit 31 cause, it is level LV3 that the high levels of clock signal CK1 causes that control signal SP is raised by level LV2.Transistor Mb1 turns on according to the control signal SP with level LV3.Owing to clock signal CK1 is enabled in time point T2, therefore, transistor Mb1, control signal D1 through conducting are enabled (being become high levels from low level).Additionally, transistor Mb2 turns on also according to the control signal SP with level LV3.But owing to clock signal CK2 is still in anti-enabled status, therefore, through the transistor Mb2, control signal D2 of conducting still in anti-enabled status.
At time point T3, clock signal CK2 is enabled, due to the capacitance coupling effect that the lock-drain parasitic capacitance of capacitor Cc2 and transistor Mb2 and lock-source electrode parasitic capacitance in output unit 32 cause, it is level LV4 that the high levels of clock signal CK2 causes that control signal SP is raised by level LV3.Transistor Mb1 turns on according to the control signal SP with level LV4.Owing to clock signal CK1 is still in the state of being enabled, therefore, through the transistor Mb1, control signal D1 of conducting still in enabled status (high levels).Additionally, transistor Mb2 turns on also according to the control signal SP with level LV4.But owing to clock signal CK2 is enabled at time point T2, therefore, through the transistor Mb2 of conducting, control signal D2 is enabled.
At time point T4, clock signal CK1 is by renvoi energy (being become low level from high levels), the similarly capacitance coupling effect caused by output unit 31 so that control signal SP is reduced to level LV5 along with the clock signal CK1 of renvoi energy by level LV4.In this embodiment, level LV5 is equal to level LV3.Transistor Mb1 turns on according to the control signal SP with level LV5.Due to clock signal CK1 in time point T4 by renvoi energy (becoming low level for high levels), therefore, through the transistor Mb1, control signal D1 of conducting by renvoi energy (being become low level from high levels).It is enabled to turn on transistor Mc1 at time point T4, clock signal CK3, now coupled to reference to ground connection VGL and drive signal D1 to help the renvoi driving signal D1 to operate.Additionally, transistor Mb2 turns on according to the control signal SP with level LV5.Owing to clock signal CK2 is still in the state of being enabled, therefore, through the transistor Mb2 of conducting, control signal D2 is still in enabled status.
At time point T5, clock signal CK2 by renvoi energy, the similarly capacitance coupling effect caused by output unit 32 so that control signal SP is reduced to level LV1 along with the clock signal CK2 of renvoi energy by level LV5.Now, signal D1 is driven to maintain anti-enabled status.Additionally, be enabled to turn on transistor Mc2 at time point T5, clock signal CK4, now it coupled to driving signal D2 with reference to ground connection VGL through the transistor Mc2 turned on so that drive signal D2 by renvoi energy.
After time point T5, clock signal CK1 switches constantly between high levels and low level.Pass through the anti-enabled status of lock-capacitance of drain (Cgd) the coupling effect impact driving signal D1 of transistor Mb1 in order to avoid the high levels of clock signal CK1, therefore control circuit 30 creates control signal SQ.Consulting Fig. 4, after time point T5, control signal SQ and clock signal CK1 simultaneously switches between high levels and low level.Therefore, when clock signal CK1 is in high levels, control signal SQ is also at high levels to turn on transistor MQ, then coupled to driving signal D2 through the transistor MQ of conducting with reference to ground connection VGL so that drive signal D1 to be stably in anti-enabled status (low level).
Embodiment according to Fig. 3 A, Fig. 3 B, each driver element produces continuous print two and drives signal.In each driver element, produce continuous print two and drive signal to include a drive circuit, five transistors and two capacitors.According to Fig. 1 in known techniques, if being intended to produce two to drive signal, needing the driver element of two Fig. 1, there are two drive circuits, six transistors and two capacitors altogether.Therefore, driving device 21 takies the area reduction of display floater 2.Additionally, due to the quantity of transistor reduces so that the power consumption of driving device 21 reduces.
In Fig. 2 and Fig. 3 A embodiment with Fig. 3 B, each driver element system produces continuous print two and drives signal.But, in other embodiments, each driver element can produce and control discontinuous two and drive signal Dw and Dw+x, for instance x=2.For example, driver element RU1 produces two drivings signal D1 and D3 (w=1, x=2)；Driver element RU2 produces to control two drivings signal D2 and D4 (w=2, x=2)；Driver element RU3 produces two drivings signal D5 and D7 (w=5, x=2)；Driver element RU4 produces to control two drivings signal D6 and D8 (w=6, x=2).Assuming when k and n is all even number, driver element RUk then produces two drivings signal Dn-2 and Dn (w=n-2, x=2).In the case, for the sequential of the clock signal received of transistor Mb1 and Mb2 in each driver element, the clock signal that transistor Mb2 receives is with the unit interval T of two (given amount=x=2)DPostpone in the transistor Mb1 clock signal received.Consult Fig. 4 and Fig. 5 A and Fig. 5 B, for example, in driver element RU1, output unit 31 is output drive signal D1 (w=1), output unit 32 output drive signal D3 (x=2), now, enable sequential according to control signal D1 and D3, transistor Mb1 receives clock signal CK1, and transistor Mb2 receives clock signal CK3, wherein, clock signal CK3 is with two (x=2) unit interval TDPostpone in clock signal CK1.About the sequential of two clock signals that output unit single in a driver element receives, two clock signals that each output unit receives still differ two unit interval TD.Specifically, in the output unit 31 of driver element RU1, clock signal CK3 postpones two unit interval T of clock signal CK1D, and in output unit 32, clock signal CK5 postpones two unit interval T of clock signal CK3D。
In the above-described embodiments, it is produce output two driving signal with each driver element.But in other embodiments, each driver element produces three on node N20, N21 and N22 respectively and drives signal Dw, Dw+x and Dw+y, and wherein, w is a positive integer and 1≤w≤n-2, x is a positive integer and 1≤x≤n-w-1, y is a positive integer and 1≤x≤n-w.Consulting Fig. 6, each driver element produces continuous print three and drives signal, i.e. x=1 and y=2.For example, driver element RU1 produces three on node N20, N21 and N22 respectively and drives signal D1, D2 and D3 (w=1, x=1, y=2)；Driver element RU2 produces three on node N20, N21 and N22 respectively and drives signal D4, D5 and D6 (w=4, x=1, y=2)；Driver element RU3 produces three on node N20, N21 and N22 respectively and drives signal D7, D8 and D9 (w=7, x=1, y=2)；Driver element RU4 produces three on node N20, N21 and N22 respectively and drives signal D10, D11 and D12 (w=10, x=1, y=2).When assuming k and the n multiple being all three, driver element RUk then produces three and drives signal Dn-2, Dn-1 and Dn (w=n-2, x=1, y=2).
The detailed circuit of each driver element of Fig. 7 A and Fig. 7 B system expression Fig. 6.In order to know explanation, Fig. 7 A and Fig. 7 B only represents the detailed circuit of driver element RU1～RU4, and in this embodiment, each driver element has identical circuit framework.Consult Fig. 7 A and Fig. 7 B, each driver element except include Fig. 3 A, the control circuit 30 of Fig. 3 B, output circuit 31 and 32 and holding circuit 33 except, driving signal owing to each driver element system produces three, therefore each driver element of Fig. 7 A and Fig. 7 B more includes output circuit 70.Due to control circuit 30, output circuit 31 and 32 and holding circuit 33 be described in the related description of Fig. 3 A, Fig. 3 B, therefore omit at this.Signal Dw is driven to result from the node N20 of output circuit 31.Signal Dw+x is driven to result from the node N21 of output circuit 32.Output circuit 70 includes transistor Mb3 and Mc3 and capacitor CC3.The grid of transistor Mb3 receives control signal SP, and its drain electrode receives a clock signal and its source electrode couple nodes N22.Between grid and the source electrode of capacitor Cc3 coupling transistors Mb3.The grid of transistor Mc3 receives another clock signal, its couple nodes N21 that drains, and its source electrode couples with reference to ground connection VGL.Signal Dw+y is driven to result from node N21.Operation according to above-mentioned output unit 32, output unit 70 also performs identical operation.Therefore omit and do not repeat.
Fig. 8 system represents initial signal STV, clock signal CK1～CK6, control signal SP and SQ in the embodiment of Fig. 7 A, Fig. 7 B and drives the waveform of signal D1～D3.Compared with the control signal SP of Fig. 4, control signal SP maintains the time lengthening of level LV5, for the enable operation driving signal D3.Similarly, clock signal CKi+1 postpones in previous clock signal CKi mono-unit interval TD, wherein, i is a positive integer and 1≤i≤5 (5=j-1, j=6).
In this embodiment, the sequential of several clock signals that each driver element receives and its driving signal correction exported connection.About the sequential of the clock signal that transistor Mb1, Mb2 and Mb3 in each driver element receive, in this embodiment, the clock signal that transistor Mb2 receives is with the unit interval T of the first given amountDPostpone in the transistor Mb1 clock signal received, and the clock signal that receives of crystal Mb3 is with the unit interval T of the second given amountDPostpone in the transistor Mb1 clock signal received.Consult Fig. 7 A, Fig. 7 B and Fig. 8, for each driver element, when output unit 31 export drive signal be drive the w in signal D1～Dn to drive signal, output unit 32 export drive signal be the w+x in driving signal D1～Dn drive that signal and output unit 70 export when to drive signal be the w+y driving signal in driving signal D1～Dn, the first given amount is equal to x and the second given amount is equal to y.For example, in driver element RU1, output unit 31 is that output the 1st drives signal D1 (w=1), output unit 32 exports the 2nd and drives signal D2 (x=1), and output unit 70 exports the 3rd and drives signal D3 (y=2), now, enable sequential according to control signal D1, D2 and D3, transistor Mb1 receives clock signal CK1, transistor Mb2 receives clock signal CK2, and transistor Mb3 receives clock signal CK3, wherein, clock signal CK2 is with a unit interval TD(x=1) postpone in clock signal CK1, and clock signal CK3 is with two unit interval TD(y=1) postpone in clock signal CK1.
About the sequential of two clock signals that single output unit receives, in embodiments of the present invention, two clock signals that each output unit receives all differ two unit interval TD.Specifically, in output unit 31, clock signal CK3 postpones two unit interval T of clock signal CK1D；In output unit 32, clock signal CK4 postpones two unit interval T of clock signal CK2D；In output unit 70, clock signal CK5 postpones two unit interval T of clock signal CK3D。
Fig. 6 and Fig. 7 A, Fig. 7 B embodiment in, each driver element system produce continuous print three drive signal.But, in other embodiments, each driver element can produce and control discontinuous three and drive signal Dw, Dw+x and Dw+y, for instance x=2 and y=4.For example, driver element RU1 produces two drivings signal D1, D3 and D5 (w=1, x=2, y=4)；Driver element RU2 produces to control two drivings signal D2, D4 and D6 (w=2, x=2, y=4)；Driver element RU3 produces two drivings signal D7, D9 and D11 (w=5, x=2, y=4)；Driver element RU4 produces to control two drivings signal D8, D10 and D12 (w=6, x=2, y=4).Assuming when k and n is all even number, driver element RUk then produces three driving signal Dn-4, Dn-2 and Dn (w=n-4, x=2, y=4).In the case, for the sequential of the clock signal that transistor Mb1, Mb2 and Mb3 in each driver element receive, the clock signal that transistor Mb2 receives is with the unit interval T of 2 (the first given amount=x=2)DPostpone in the transistor Mb1 clock signal received, and the clock signal that receives of transistor Mb3 is with the unit interval T of 4 (the second given amount=y=4)DPostpone in the transistor Mb1 clock signal received.Consult Fig. 8 and Fig. 9 A, Fig. 9 B, for example, in driver element RU1, output unit 31 is that output the 1st drives signal D1 (w=1), output unit 32 exports the 3rd and drives signal D3 (x=2), and output unit 70 exports the 3rd and drives signal D5 (y=4), now, enable sequential according to control signal D1, D3 and D5, transistor Mb1 receives clock signal CK1, transistor Mb2 and receives clock signal CK3, and transistor Mb3 receives clock signal CK5, wherein, clock signal CK3 is with 2 (x=2) unit interval TDPostpone in clock signal CK1, and clock signal CK5 is with 4 (y=4) unit interval TDPostpone in clock signal CK1.About the sequential of two clock signals that single output unit receives, two clock signals that each output unit receives still differ two unit interval TD.Specifically, in output unit 31, clock signal CK3 postpones two unit interval T of clock signal CK1D；In output unit 32, clock signal CK5 two unit interval T of slow clock signal CK3D；In output unit 70, clock signal CK1 two unit interval T of slow clock signal CK5D。
In the embodiment of fig. 2, display floater 2 includes the driving device 21 that is arranged in array of display 20 side.And in still other embodiments, display floater 2 can more include driving device 100.As it was previously stated, driver element 21 is arranged in the side of array of display 20, and include driver element RU1～RUk.Driving device 100 is arranged in the opposite side of array of display 20.Driving device 100 includes driver element LU1～LUh and at least one driver element SLU, h are a positive integer.Driver element LU1～LUh output drive signal D1～Dn is respectively to gate lines G L1～GLn.Driver element LU1～LUh and driver element RU1～RUk have identical circuit framework, have control circuit 30, output circuit 31 and 32 and holding circuit 33 equally.
In fig. 2, each driver element produces continuous print two and drives signal Dw and Dw+x (in fig. 2 x=1).Embodiment according to Fig. 3 A, Fig. 3 B, the output circuit 31 of each driver element lies in node N20 and produces to drive signal Dw, and output circuit 32 lies in node N22 and produces to drive signal Dw+x.For each driver element, the intensity of the produced signal Dw of driving of output circuit 31 is more than the produced intensity driving signal Dw+x of output circuit 32, it is possible to can cause the uneven of show image.Therefore, in order to enable on display floater 2 show image equably and maintain display floater 2 well drive degree of stability, drive signal Dw+x can be produced by the output circuit 31 of driver element corresponding in driving device 100 and be controlled simultaneously, and drive signal Dw produced by the output circuit 32 of driver element corresponding in driving device 100 and controlled simultaneously.Similarly, for each driver element in driving device 100, the produced intensity intensity more than the produced driving signal of output circuit 32 driving signal of output circuit 31.Therefore, signal Dw and Dw+x is driven to be produced by an output unit 31 and an output unit and 32 and controlled all simultaneously so that the intensity driving signal Dw and Dw+x is identical.
Additionally, according to above-mentioned, drive signal Dw and Dw+x produced by an output unit 31 and an output unit and 32 and controlled all simultaneously.Therefore, when driving signal Dw/Dw+x by renvoi energy, transistor MQ through the holding circuit 33 being coupled to corresponding output unit 31 maintains anti-enabled status with stabilizing it, and lock-capacitance of drain (Cgd) coupling effect that clock signal passes through corresponding transistor Mb2 thereby can be avoided to affect the level driving signal Dw/Dw+x.
For example, the output circuit 31 of driver element RU2 produces to drive signal D3 in node N20, and output circuit 32 produces to drive signal D4 in node N21.Meanwhile, drive signal D3 system to be produced in node N21 by the output circuit 32 of driver element LU1, and drive signal D4 system to be produced in node N20 by the output circuit 31 of driver element LU2.It should be noted that driving signal D1 now is except being produced by the output circuit 31 of driver element RU1, it is also produced by the driver element SLU in driving device 100.Driver element SLU exports single driving signal, and it can be the driver element 1 of Fig. 1.In this embodiment, the quantity system of driver element SLU determines according to the quantity driving signal.The quantity of driver element SLU is less than or equal to 2, for producing and controlling the one (D1) in driving signal D1～Dn, last one (Dn) or one and last one.Assume that having even number drives signal (namely n is even number), therefore, as shown in Figure 10, drive signal Dn also to be produced by another driver element SLU.
Though the present invention is disclosed above with preferred embodiment; so it is not limited to the scope of the present invention; any art has usually intellectual; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion with the defined person of the claims in the present invention.
Claims (20)
1. a driving device, it is characterised in that described driving device includes:
Plural number driver element, drives signal D1～Dn in order to produce plural number according to plural number clock signal CK1～CKj, and wherein, described driving signal D1～Dn is sequentially enabled, and j, n are respectively a positive integer；
Wherein, described clock signal CKi+1 with a unit interval postpone in described clock signal CKi, i be a positive integer and 1 i j-1；And
Wherein, each described driver element produces at least two driving signal in described driving signal D1～Dn, and each described driver element includes:
One control circuit, in order to produce one first control signal and one second control signal；
One first output circuit, drive signal in order to produce described one first in signal D1～Dn that drives, and carry out the first driving signal described in enable according to one first clock signal and one second clock signal in the first described control signal and described clock signal CK1～CKj；And
One second output circuit, in order to produce the two driving signal in described driving signal D1～Dn, and carry out the two driving signal described in enable according to one the 3rd clock signal and one the 4th clock signal in the first described control signal and described clock signal CK1～CKj, wherein, the first described driving signal and described two driving signal are sequentially enabled；
Wherein, described driver element divides into one first group and one second group；And
Wherein, each described drive the signal the second output circuit described in the one in the driver element belonged to described in described first group and belong to the first output circuit described in the one in the driver element described in described second group and produced.
2. driving device as claimed in claim 1, it is characterised in that the first described output circuit includes:
One the first transistor, has the grid of the first control signal described in receiving, receives the drain electrode of the first described clock signal and couple the source electrode of a primary nodal point；
One capacitor, is coupled between grid and the source electrode of described the first transistor；And
One transistor seconds, the drain electrode there is the grid receiving the second described clock signal, coupling described primary nodal point and couple with reference to the source electrode of ground connection；
Wherein, the first described driving signal results from described primary nodal point.
3. driving device as claimed in claim 2, it is characterised in that the second described output circuit includes:
One third transistor, has the grid of the first control signal described in receiving, receives the drain electrode of the 3rd described clock signal and couple the source electrode of a secondary nodal point；
One capacitor, is coupled between grid and the source electrode of described third transistor；And
One the 4th transistor, has the grid of the 4th clock signal described in receiving, couples the drain electrode of described secondary nodal point and couple the source electrode of described reference ground connection；
Wherein, described two driving signal results from described secondary nodal point.
4. driving device as claimed in claim 3, it is characterized in that, the second described clock signal postpones in the first described clock signal with two described unit interval, two described unit interval of the 4th described clock signal postpone in the 3rd described clock signal, and the 3rd described clock signal postponed in the first described clock signal with the unit interval described in a given amount.
5. driving device as claimed in claim 4, it is characterized in that, when the w in driving signal D1～Dn that the first described driving signal is described drives signal and described two driving signal to be described the w+x the driving signal driven in signal D1～Dn, described given amount is equal to x, w is a positive integer and 1 w n-1, x is a positive integer and 1 x n-w.
6. driving device as claimed in claim 4, it is characterized in that, when the first described control signal turns on described the first transistor, described first drives signal enable according to a pulse wave of the first described clock signal, and when the third transistor that described first control signal conducting is described, the enable according to a pulse wave of the 3rd described clock signal of described two driving signal.
7. driving device as claimed in claim 1, it is characterised in that when each described driver element produces three driving signals in described driving signal D1～Dn, each described driver element more includes:
One the 3rd output circuit, signal is driven in order to produce described the 3rd in signal D1～Dn that drives, and carry out the two driving signal described in enable according to one the 5th clock signal and one the 6th clock signal in the first described control signal and described clock signal CK1～CKj, wherein, described the first driving signal, described two driving signal and the described the 3rd drive signal to be sequentially enabled.
8. driving device as claimed in claim 7, it is characterized in that, the second described clock signal postpones in the first described clock signal with two described unit interval, the 4th described clock signal postpones in the 3rd described clock signal with two described unit interval, the 6th described clock signal postpones in the 5th described clock signal with two described unit interval, the 3rd described clock signal postpones in the first described clock signal with the unit interval described in one first given amount, and the 5th described clock signal postponed in the first described clock signal with the unit interval described in one second given amount.
9. driving device as claimed in claim 8, it is characterized in that, when described first drives the w in signal D1～Dn that drive that signal is described to drive signal, the w+x in signal D1～Dn that drive that described two driving signal is described drives signal, and the described 3rd when to drive signal be described the w+y the driving signal driven in signal D1～Dn, the first described given amount is equal to x, and the second described given amount is equal to y, w is a positive integer and 1 w n-2, x is a positive integer and 1 x n-w-1, y is a positive integer and 2 y n-w.
10. driving device as claimed in claim 7, it is characterized in that, described first drives signal enable according to a pulse wave of the first described clock signal, the enable according to a pulse wave of the 3rd described clock signal of described two driving signal, and the described the 3rd drive signal enable according to a pulse wave of the 5th described clock signal.
11. driving device as claimed in claim 1, it is characterised in that each described driver element more includes:
One holding circuit, couples the first described output circuit, in order to when described first drives signal by renvoi energy, maintains the described first level driving signal according to the second described control signal.
12. driving device as claimed in claim 11, it is characterised in that described holding circuit includes:
One transistor, the drain electrode there is the grid receiving the second described control signal, coupling the first described output circuit and couple with reference to the source electrode of ground connection；
Wherein, when described first drives signal by renvoi energy, described transistor turns on according to the second described control signal, to drive the level of signal to maintain the level of described reference ground connection by described first.
13. a display floater, it is characterised in that described display floater includes:
Gate line GL1～GLn, sequentially configures with a first direction, and n is a positive integer；
Plural number source electrode line, sequentially configures with a second direction, and is staggered to form an array of display with described gate lines G L1～GLn；And
Plural number driver element, is a positive integer in order to produce to drive signal D1～Dn, j according to plural number clock signal CK1～CKj；
Wherein, the described signal D1～Dn that drives is provided to described gate lines G L1～GLn by described driver element respectively, described driving signal D1～Dn is sequentially enabled, and described clock signal CKi+1 with a unit interval postpone in described clock signal CKi, i be a positive integer and 1 i j-1；And
Wherein, in the driving signal D1～Dn described in each generation in described driver element, at least two drive signals and include:
One control circuit, in order to produce one first control signal and one second control signal；
One first output circuit, drive signal in order to produce described one first in signal D1～Dn that drives, and carry out the first driving signal described in enable according to one first clock signal and one second clock signal in the first described control signal and described clock signal CK1～CKj；And
One second output circuit, in order to produce the two driving signal in described driving signal D1～Dn, and carry out the two driving signal described in enable according to one the 3rd clock signal and one the 4th clock signal in the first described control signal and described clock signal CK1～CKj；
Wherein, described driver element divides into one first group and one second group；And
Wherein, each described drive the signal the second output circuit described in the one in the driver element belonged to described in described first group and belong to the first output circuit described in the one in the driver element described in described second group and produced.
14. display floater as claimed in claim 13, it is characterised in that the first described output circuit includes:
One the first transistor, has the grid of the first control signal described in receiving, receives the drain electrode of the first described clock signal and couple the source electrode of a primary nodal point；
One capacitor, couples between the grid and source electrode being connected to described the first transistor；And
One transistor seconds, has the drain electrode of the primary nodal point described in the grid of the second clock signal described in receiving, reception and couples the source electrode of a reference ground connection；
Wherein, the first described driving signal results from described primary nodal point.
15. display floater as claimed in claim 14, it is characterised in that two described output circuits include:
One third transistor, has the grid of the first control signal described in receiving, receives the drain electrode of the 3rd described clock signal and couple the source electrode of a secondary nodal point；
One capacitor, couples between the grid and source electrode being connected to described third transistor；And
One the 4th transistor, has the grid of the 4th clock signal described in receiving, receives the drain electrode of described secondary nodal point and couple the source electrode of described reference ground connection；
Wherein, described two driving signal results from described secondary nodal point.
16. display floater as claimed in claim 15, it is characterized in that, the second described clock signal postpones in the first described clock signal with two described unit interval, two described unit interval of the 4th described clock signal postpone in the 3rd described clock signal, and the 3rd described clock signal postponed in the first described clock signal with the unit interval described in a given amount.
17. display floater as claimed in claim 16, it is characterized in that, when w+x gate line during described first drives signal to be w gate line in described gate lines G L1～GLn and described two driving signal is described gate lines G L1～GLn, described given amount is equal to x, w is a positive integer and 1 w n-1, x is a positive integer and 1 x n-w.
18. display floater as claimed in claim 16, it is characterized in that, when the first described control signal turns on described the first transistor, described first drives signal enable according to a pulse wave of the first described clock signal, and when the third transistor that described first control signal conducting is described, the enable according to a pulse wave of the 3rd described clock signal of described two driving signal.
19. display floater as claimed in claim 13, it is characterised in that the described driver element of described first group is arranged in the side of described array of display, and the described driver element of described second group is arranged in the opposite side of described array of display.
20. display floater as claimed in claim 13, it is characterised in that the described each in driver element includes:
One holding circuit, couples the first described output circuit, in order to when described first drives signal by renvoi energy, maintains the described first signal driving signal according to the second described control signal.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3148151B2 (en) * | 1997-05-27 | 2001-03-19 | 日本電気株式会社 | Method and apparatus for reducing output deviation of liquid crystal driving device |
| CN1581256A (en) * | 2003-08-14 | 2005-02-16 | 三星电子株式会社 | Signal conversion circuit and displaying device |
| CN101783124A (en) * | 2010-02-08 | 2010-07-21 | 北京大学深圳研究生院 | Grid electrode driving circuit unit, a grid electrode driving circuit and a display device |
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| JP3703247B2 (en) * | 1997-03-31 | 2005-10-05 | 三菱電機株式会社 | Plasma display apparatus and plasma display driving method |
| CN101377956B (en) * | 2007-08-31 | 2010-12-29 | 群康科技(深圳)有限公司 | Shift register and LCD |
| US8344989B2 (en) * | 2007-12-31 | 2013-01-01 | Lg Display Co., Ltd. | Shift register |
| JP2010072335A (en) * | 2008-09-18 | 2010-04-02 | Nec Corp | Display and its driving method, and portable terminal |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3148151B2 (en) * | 1997-05-27 | 2001-03-19 | 日本電気株式会社 | Method and apparatus for reducing output deviation of liquid crystal driving device |
| CN1581256A (en) * | 2003-08-14 | 2005-02-16 | 三星电子株式会社 | Signal conversion circuit and displaying device |
| CN101783124A (en) * | 2010-02-08 | 2010-07-21 | 北京大学深圳研究生院 | Grid electrode driving circuit unit, a grid electrode driving circuit and a display device |
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