CN102955425B

CN102955425B - Satellite timing method with highly reliable fixed point position

Info

Publication number: CN102955425B
Application number: CN201210418027.3A
Authority: CN
Inventors: 不公告发明人
Original assignee: CHANGSHA TIANQIONG ELECTRONIC TECHNOLOGY Co Ltd
Current assignee: CHANGSHA TIANQIONG ELECTRONIC TECHNOLOGY Co Ltd
Priority date: 2010-12-10
Filing date: 2010-12-10
Publication date: 2014-08-27
Anticipated expiration: 2030-12-10
Also published as: CN102955425A

Abstract

The invention relates to a satellite timing method with a highly reliable fixed point position. The method comprises a radio frequency processing part, a digital signal processing part and a time delay compensation part, wherein an FPGA (Field Programmable Gate Array) and a DSP (Digital Signal Processor) chip are connected by an EMIF (External Memory Interface) for data exchange. Combined with time of satellites and local frequency standard, correct time can be still output by a numerically controlled oscillator under the existence of several satellite failures, therefore, the fault-tolerance performance of a receiver is effectively improved, so that the satellite timing method with the highly reliable fixed point position has a wide application prospect.

Description

The satellite timing method that a kind of point of fixity position is highly reliable

Technical field

The present invention has introduced the highly reliable satellite timing method in a kind of point of fixity position, the method can realize timing by receiving satellite signal, can be applicable to the synchronous of wide-area distribution type network, as electrical network, 3G digital communication network, by receiving navigation satellite signal, realize the time synchronized of the distributed network that covers extensive region.

Background technology

When satellite, obtain widespread use owing to thering is wide coverage, timing accuracy advantages of higher.Time reference when satellite is from satellite, and due to the spacecraft that satellite is long-time running, its operation needs the monitoring of ground monitoring station.When satellite long-play, slowly offset track, therefore needs regularly to adjust rail.During satellite is adjusted rail, its running orbit moves not according to predetermined kinetic model, and its track departs from larger.In timing application, need to know that accurate satellite position is convenient to calculate the propagation delay time of satellite-signal, therefore departing from of position will be caused larger timing error.And departing from of position is to forecast in the descending text of satellite, therefore user cannot know satellitosis now completely, cannot know now whether the time of output meets accuracy requirement.If output time departs from large and cannot learn, will give and need synchronous system to bring harm, when serious, can cause system crash.Cause adopting the cdma network of gps satellite timing to break down as once there is gps satellite fault, caused the situation that in certain limit, CDMA cellphone subscriber cannot converse.

Satellite timer generally has two kinds of timing modes, and one is positioning timing, is suitable for dynamic subscriber, generally need to receive 4 above satellites ability positioning timings; Another kind is the timing of point of fixity position, also claims position Holdover mode, is suitable for static subscriber, and receiving a satellite can timing.Under the timing mode of point of fixity position, if receive a fault satellites, just may cause and there is the time output departing from more greatly, jeopardize the safety of network system.

Summary of the invention

For addressing the above problem, the present invention proposes the highly reliable satellite timing method in a kind of point of fixity position, the device of the method comprises Radio frequency Processing Unit, RF Processing Unit, signal process part and delay compensation part, wherein: FPGA adopts EMIF interface to be connected with dsp chip, realizes exchanges data; AD sampling A/D chip is given in the output of radio-frequency module, after AD sampling A/D chip AD sampling A/D chip is converted to digital signal, sends into FPGA; Configuring chip is connected with FPGA, storage FPGA program; Nonvolatile memory is connected with FPGA, storage DSP program; When electrifying startup, FPGA, from nonvolatile memory reading out data, is DSP loading procedure by EMIF interface; The output of local oscillator connects radio-frequency module, FPGA and DSP; Linear power supply module is converted to input power the various voltages of FPGA and DSP needs.

The method is specially: time block obtains by catching markers the time of determining, first, in FPGA, define the register of group more than, data after the decoding verification register shift of often coming in just to allow, and carry out XOR comparison with Barker code, if the value in judgement register is identical with Barker code or contrary, draw high mode bit, all the other situations are dragged down; By judging the height situation of mode bit, express FPGA and whether search the Barker code in data; In FPGA, normal searching is after Barker code, and the output of mode bit will be rendered as a pulse waveform, and last position of rising edge and Barker code is neat; Utilize this pulse in conjunction with point frame number calculating in text, a point frame number of choosing whole second place is reference, can go out pps pulse per second signal from local recovery, i.e. markers; Obtaining after markers, time block is navigation message via satellite, can calculate signal and transmit overall delay, and the markers of this satellite is compensated, and can obtain the standard time of this satellite.

Radiofrequency signal is downconverted to intermediate frequency by Radio frequency Processing Unit, RF Processing Unit, signal process part obtains catching markers and demodulates text carrying out acquisition and tracking after intermediate-freuqncy signal AD sampling, delay compensation part calculates transmission delay according to text, according to catching markers, time delay is compensated, obtain standard time output.

The present invention proposes to catch multi-satellite signal simultaneously, obtains the standard time output of many stars.In conjunction with local frequency reference, the correctness of time is differentiated.The present invention proposes digital controlled oscillator technology, makes the differentiation of time change digital differentiation into, is easy at digital circuit.

The advantage of this invention is to utilize digital controlled oscillator, in conjunction with the time of multi-satellite and local frequency reference, can have under some satellite failures still exportable orthochronous, has effectively improved the fault freedom of receiver, is with a wide range of applications.

Brief description of the drawings

Fig. 1 is Barker code search routine figure,

Fig. 2 is output time selection figure,

Fig. 3 is signal processing flow figure,

Fig. 4 is timing device structural drawing.

Embodiment

The navigation message of satellite comprises the information such as ephemeris, time and satellitosis.Navigation message is generally modulated by spreading code, then is modulated to RF spot, launches through satellite antenna.According to the coded format of satellite message, the flag of frame of text indicates this frame to start, and is made up of bar trellis code, and Barker code is this frame reference time scale along corresponding pulse behind last position ' 1 '.

The modulated time of specific frame head of navigation message is definite time, is called markers.Timing device obtains by catching markers the time of determining.Target acquisition procedure when Fig. 1 is.The process of search Barker code realizes in FPGA.First, in FPGA, define more than one the register of group, the register shift of often coming in just to allow of the data after decoding verification, and carry out XOR comparison with Barker code, if the value in judgement register is identical with Barker code or contrary, draw high mode bit, all the other situations are dragged down.By judging the height situation of mode bit, to express FPGA and whether search the Barker code in data, flow process is as shown in Figure 1.In FPGA, normal searching is after Barker code, and the output of mode bit will be rendered as a pulse waveform, and last position of rising edge and Barker code is neat.Utilize this pulse in conjunction with point frame number calculating in text, a point frame number of choosing whole second place is reference, can go out pps pulse per second signal from local recovery, i.e. markers.

Obtaining after markers, timing device is navigation message via satellite, can calculate signal and transmit overall delay, and the markers of this satellite is compensated, and can obtain the standard time of this satellite.

Can obtain the standard time of multi-satellite by method shown in Fig. 1.Because timing device has local oscillator as crystal oscillator, local oscillator can generate local zone time, produces a second counting.According to next second confidence region of determine precision of local oscillator.

If the frequency of local oscillator is f, be t oscillation period, and the degree of stability of frequency is a, and next second region is

[(1-a)f·t,?(1+a)f·t]

As shown in Figure 2.Utilize confidence region to differentiate the validity of satellite time.Drop in this region when the standard time of satellite, this satellite time is effective, otherwise this satellite time is invalid.Obtaining after many effective satellite standard time, selecting the output of higher standard time of consistance as time block.

Specifically treatment scheme is as shown in Figure 3:

1, multi-satellite signal capture and tracking;

2, obtain catching markers and calculate time delay;

3, obtain the standard time of multi-satellite, calculate the fiducial interval of local frequency reference;

4, obtain multiple effective satellite standard time;

5, select the output of most homogeneous markers.

As shown in Figure 4, FPGA adopts EMIF interface to be connected with dsp chip to the structure of timing device, realizes exchanges data; AD sampling A/D chip is given in the output of radio-frequency module, sends into FPGA after being converted to digital signal; Configuring chip is connected with FPGA, storage FPGA program; Nonvolatile memory is connected with FPGA, storage DSP program; When electrifying startup, FPGA, from nonvolatile memory reading out data, is DSP loading procedure by EMIF interface; The output of local oscillator connects radio-frequency module, FPGA and DSP; Linear power supply module is converted to input power the various voltages of FPGA and DSP needs.

The main division of labor of FPGA and DSP is as follows: FPGA is responsible for catching, following the tracks of of signal, produces and catches markers, and DSP is responsible for time-delay calculation, and gives FPGA by the time delay calculating; FPGA recovers the final time of multi-satellite, and carries out confidence region differentiation, and selects the highest consistance time output.

Claims

1. the satellite timing method that point of fixity position is highly reliable, it is characterized in that, time block obtains by catching markers the time of determining, first, in FPGA, define more than one the register of group, the register shift of often coming in just to allow of the data after decoding verification, and carry out XOR comparison with Barker code, if the value in judgement register is identical with Barker code or contrary, draw high mode bit, all the other situations are dragged down; By judging the height situation of mode bit, express FPGA and whether search the Barker code in data; In FPGA, normal searching is after Barker code, and the output of mode bit will be rendered as a pulse waveform, and last position of rising edge and Barker code is neat; Utilize this pulse in conjunction with point frame number calculating in text, a point frame number of choosing whole second place is reference, goes out pps pulse per second signal, i.e. markers from local recovery; Obtaining after markers, time block is navigation message via satellite, calculates signal and transmits overall delay, and the markers of this satellite is compensated, and obtains the standard time of this satellite.

2. the highly reliable satellite timing method in a kind of point of fixity according to claim 1 position, it is characterized in that, obtaining after many effective satellite standard time, selecting the output of higher standard time of consistance as timing device, concrete treatment scheme is as follows:

(1) multi-satellite signal capture and tracking;

(2) obtain catching markers and calculate time delay;

(3) obtain standard time of multi-satellite, calculate the fiducial interval of local frequency reference;

(4) obtain multiple effective satellite standard time;

(5) select the output of most homogeneous markers.

3. the highly reliable satellite timing method in a kind of point of fixity according to claim 1 position, it is characterized in that, according to next second confidence region of determine precision of local oscillator, if the frequency of local oscillator is f, be t oscillation period, the degree of stability of frequency is a, and next second region is [(1-a) ft, (1+a) ft].