CN102955425A

CN102955425A - Satellite timing method with highly reliable fixed point position

Info

Publication number: CN102955425A
Application number: CN2012104180273A
Authority: CN
Inventors: 不公告发明人
Original assignee: CHANGSHA TIANQIONG ELECTRONIC TECHNOLOGY Co Ltd
Current assignee: CHANGSHA TIANQIONG ELECTRONIC TECHNOLOGY Co Ltd
Priority date: 2010-12-10
Filing date: 2010-12-10
Publication date: 2013-03-06
Anticipated expiration: 2030-12-10
Also published as: CN102955425B

Abstract

The invention relates to a satellite timing method with a highly reliable fixed point position. The method comprises a radio frequency processing part, a digital signal processing part and a time delay compensation part, wherein an FPGA (Field Programmable Gate Array) and a DSP (Digital Signal Processor) chip are connected by an EMIF (External Memory Interface) for data exchange. Combined with time of satellites and local frequency standard, correct time can be still output by a numerically controlled oscillator under the existence of several satellite failures, therefore, the fault-tolerance performance of a receiver is effectively improved, so that the satellite timing method with the highly reliable fixed point position has a wide application prospect.

Description

The satellite timing method that a kind of point of fixity position is highly reliable

Technical field

The present invention has introduced the highly reliable satellite timing method in a kind of point of fixity position, but the method receiving satellite signal is realized regularly, can be applicable to the synchronous of wide-area distribution type network, such as electrical network, 3G digital communication network, by receiving navigation satellite signal, realize the time synchronized of the distributed network of covering extensive region.

Background technology

Obtain widespread use owing to having wide coverage, timing accuracy advantages of higher during satellite.Time reference during satellite is from satellite, because satellite is the spacecraft of long-time running, its operation needs the monitoring of ground monitoring station.During the satellite long-play, slowly therefore offset track needs regularly to transfer rail.Satellite is transferred during the rail, and its running orbit moves not according to predetermined kinetic model, and its track departs from larger.In regularly using, need to know that accurate satellite position is convenient to the propagation delay time of Calculation of Satellite signal, so departing from of position will be caused larger timing error.And departing from of position is to forecast in the descending text of satellite, so the user can't know the satellitosis of this moment fully, can't know whether the time of this moment output satisfies accuracy requirement.If output time departs from large and can't learn, will give needs synchronous system to bring harm, can cause system crash when serious.Cause adopting gps satellite cdma network regularly to break down as the gps satellite fault once occurs, caused the situation that the CDMA cellphone subscriber can't converse in the certain limit.

The satellite timer generally has two kinds of timing modes, and a kind of is positioning timing, is suitable for the dynamic subscriber, generally need to receive the satellite ability positioning timing more than 4; Another kind is the timing of point of fixity position, also claims the position Holdover mode, is suitable for the static subscriber, and receiving a satellite can be regularly.Under the timing mode of point of fixity position, if receive a fault satellites, then just may cause to have the time output that departs from more greatly, jeopardize the safety of network system.

Summary of the invention

For addressing the above problem, the present invention proposes the highly reliable satellite timing method in a kind of point of fixity position, the device of the method comprises Radio frequency Processing Unit, RF Processing Unit, signal process part and delay compensation part, and wherein: FPGA is connected the EMIF interface to connect with dsp chip, realize exchanges data; The AD sampling A/D chip is given in the output of radio-frequency module, sends into FPGA after AD sampling A/D chip AD sampling A/D chip is converted to digital signal; Configuring chip links to each other with FPGA, storage FPGA program; Nonvolatile memory links to each other with FPGA, storage DSP program; FPGA is the DSP loading procedure from the nonvolatile memory reading out data by the EMIF interface during electrifying startup; The output of local oscillator connects radio-frequency module, FPGA and DSP; Linear power supply module is converted to input power the various voltages of FPGA and DSP needs.

The method is specially: time block obtains the time of determining by catching markers, at first, the register of definition group more than in FPGA, the data of decoding after the verification register shift of whenever coming in just to allow, and carry out XOR with Barker code and compare, if judge that the value in the register is identical with Barker code or opposite, then draw high mode bit, all the other situations drag down it; By judging the height situation of mode bit, whether expression FPGA searches the Barker code in the data; Normal searching is behind Barker code in FPGA, and the output of mode bit will be rendered as a pulse waveform, and last position of rising edge and Barker code is neat; Utilize this pulse in conjunction with minute frame number that calculates in the text, a minute frame number of choosing whole second place is reference, can go out pps pulse per second signal from local recovery, i.e. markers; After obtaining markers, time block is navigation message via satellite, can calculate signal and transmit overall delay, and the markers of this satellite is compensated, and can obtain the standard time of this satellite.

Radio frequency Processing Unit, RF Processing Unit downconverts to intermediate frequency with radiofrequency signal, carrying out acquisition and tracking after signal process part is sampled intermediate-freuqncy signal AD obtains catching markers and demodulates text, the delay compensation part calculates transmission delay according to text, according to catching markers time delay is compensated, obtain standard time output.

The present invention proposes to catch simultaneously the multi-satellite signal, obtains the standard time output of many stars.In conjunction with local frequency reference, the correctness of time is differentiated.The present invention proposes the digital controlled oscillator technology, so that the differentiation of time changes the differentiation of numeral into, is easy at digital circuit.

The advantage of this invention is to utilize digital controlled oscillator, in conjunction with the time of multi-satellite and local frequency reference, can still exportable orthochronous arranged under some satellite failures, Effective Raise the fault freedom of receiver, be with a wide range of applications.

Description of drawings

Fig. 1 is Barker code search routine figure,

Fig. 2 is output time selection figure,

Fig. 3 is signal processing flow figure,

Fig. 4 is the timing device structural drawing.

Embodiment

The navigation message of satellite comprises the information such as ephemeris, time and satellitosis.Navigation message is generally modulated by spreading code, is modulated to RF spot again, launches through satellite antenna.According to the coded format of satellite message, the flag of frame of text indicates this frame to begin, and is comprised of the bar trellis code, and last position ' 1 ' of Barker code is this frame reference time scale along corresponding pulse afterwards.

The time of time for determining that the specific frame head of navigation message is modulated, be called markers.Timing device obtains the time of determining by catching markers.Target acquisition procedure when Fig. 1 is.The process of search Barker code realizes in FPGA.At first, the register of definition group more than one in FPGA, the decoding verification data afterwards register shift of whenever coming in just to allow, and carry out XOR with Barker code and compare, if judge that the value in the register is identical with Barker code or opposite, then draw high mode bit, all the other situations drag down it.By judging the height situation of mode bit, whether expression FPGA searches the Barker code in the data, and flow process as shown in Figure 1.Normal searching is behind Barker code in FPGA, and the output of mode bit will be rendered as a pulse waveform, and last position of rising edge and Barker code is neat.Utilize this pulse in conjunction with minute frame number that calculates in the text, a minute frame number of choosing whole second place is reference, can go out pps pulse per second signal from local recovery, i.e. markers.

After obtaining markers, timing device is navigation message via satellite, can calculate signal and transmit overall delay, and the markers of this satellite is compensated, and can obtain the standard time of this satellite.

Can obtain the standard time of multi-satellite by method shown in Figure 1.Because timing device has local oscillator such as crystal oscillator, local oscillator can generate local zone time, produces a second counting.Determine precision next second confidence region according to local oscillator.

If the frequency of local oscillator is f, be t oscillation period, and the degree of stability of frequency is a, and then the region is next second

[(1-a)f·t,?(1+a)f·t]

As shown in Figure 2.Utilize the confidence region that the validity of satellite time is differentiated.Drop in this zone when the standard time of satellite, then this satellite time is effective, otherwise this satellite time is invalid.Obtain many effective satellites after the standard time, selecting the higher standard time of consistance as the output of time block.

Specifically treatment scheme is as shown in Figure 3:

1, multi-satellite signal capture and tracking;

2, obtain catching markers and calculate time delay;

3, obtain the standard time of multi-satellite, calculate the fiducial interval of local frequency reference;

4, obtain a plurality of effective satellite standard time;

5, select the output of most homogeneous markers.

The structure of timing device as shown in Figure 4, FPGA is connected the EMIF interface to connect with dsp chip, realize exchanges data; The AD sampling A/D chip is given in the output of radio-frequency module, sends into FPGA after being converted to digital signal; Configuring chip links to each other with FPGA, storage FPGA program; Nonvolatile memory links to each other with FPGA, storage DSP program; FPGA is the DSP loading procedure from the nonvolatile memory reading out data by the EMIF interface during electrifying startup; The output of local oscillator connects radio-frequency module, FPGA and DSP; Linear power supply module is converted to input power the various voltages of FPGA and DSP needs.

The main division of labor of FPGA and DSP is as follows: FPGA is responsible for catching, following the tracks of of signal, produces to catch markers, and DSP then is responsible for time-delay calculation, and gives FPGA with the time delay that calculates; FPGA recovers the final time of multi-satellite, and carries out the confidence region and differentiate, and selects the highest consistance time output.

Claims

1. satellite timing method that the point of fixity position is highly reliable, it is characterized in that, time block obtains the time of determining by catching markers, at first, the register of definition group more than one in FPGA, the decoding verification data afterwards register shift of whenever coming in just to allow, and carry out XOR with Barker code and compare, if judge that the value in the register is identical with Barker code or opposite, then draw high mode bit, all the other situations drag down it; By judging the height situation of mode bit, whether expression FPGA searches the Barker code in the data; Normal searching is behind Barker code in FPGA, and the output of mode bit will be rendered as a pulse waveform, and last position of rising edge and Barker code is neat; Utilize this pulse in conjunction with minute frame number that calculates in the text, a minute frame number of choosing whole second place is reference, can go out pps pulse per second signal from local recovery, i.e. markers; After obtaining markers, time block is navigation message via satellite, can calculate signal and transmit overall delay, and the markers of this satellite is compensated, and can obtain the standard time of this satellite.

2. the highly reliable satellite timing method in a kind of point of fixity position according to claim 1, it is characterized in that, obtaining many effective satellites after the standard time, selecting the higher standard time of consistance as the output of timing device, concrete treatment scheme is as follows:

(1) multi-satellite signal capture and tracking;

(2) obtain catching markers and calculate time delay;

(3) obtain standard time of multi-satellite, calculate the fiducial interval of local frequency reference;

(4) obtain a plurality of effective satellite standard time;

(5) select the output of most homogeneous markers.

3. the highly reliable satellite timer in a kind of point of fixity position according to claim 1, it is characterized in that, determine precision next second confidence region according to local oscillator, if the frequency of local oscillator is f, be t oscillation period, the degree of stability of frequency is a, and then the region is [(1-a) ft, (1+a) ft] next second.