CN102931219A - Semiconductor device and production method thereof - Google Patents
Semiconductor device and production method thereof Download PDFInfo
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- CN102931219A CN102931219A CN2012104446629A CN201210444662A CN102931219A CN 102931219 A CN102931219 A CN 102931219A CN 2012104446629 A CN2012104446629 A CN 2012104446629A CN 201210444662 A CN201210444662 A CN 201210444662A CN 102931219 A CN102931219 A CN 102931219A
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Abstract
The invention discloses a semiconductor device and a production method thereof. The device comprises a substrate, a barrier layer, a protective layer, a middle layer and an epitaxial layer, wherein the substrate comprises at least one first buried layer window and one second buried layer window; the barrier layer is located on the first buried layer window; the protective layer is located on the substrate on the side of the barrier layer; the middle layer is located on a first epitaxial layer, and a contact position of an upper surface of the protective layer and an upper surface of the barrier layer is provided with a first step difference, and the first step difference forms a comparison window; and the epitaxial layer is located on the substrate which is located outside the barrier layer and the protective layer and is provided with an epitaxial window which is formed through epitaxial growth of the second buried layer window. The invention also discloses a production method of the semiconductor device, According to the method, the epitaxial drift capacity and the epitaxial distortion capacity are measured through the semiconductor device, the measuring accuracy is high, and the steps are simple.
Description
Technical field
The present invention relates to semiconductor semiconductor device and semiconductor process techniques field, particularly relate to a kind of semiconductor device and preparation method thereof.
Background technology
Integrated circuit is made in the epitaxial deposition process, the plane opposite sex according to the crystallographic plane growth, the generally speaking monocrystalline of the new growth growth of can strictly sorting successively along original crystal orientation of substrate, but in the semiconductor fabrication processes of reality, extension is front because the formation of step between figure, it is not fully smooth making the front surface of extension, the atomic arrangement of whole substrate surface is not continuous, according to the epitaxial growth characteristic, this surperficial discrete state can upwards be propagated when epitaxial diposition, the displacement of figure can occur in the figure on the extension (Pattern), and this figure displacement is called extension drift (Pattern Shift); Simultaneously, because this surface discontinuity, the distortion of figure also can occur in the figure on the extension, and this figure deformation is called extension distortion (Pattern distortion).For＜111〉for the crystal orientation, the extension drift mainly occurs in the directions X parallel with gulde edge, and the extension distortion then mainly occurs in the Y-direction vertical with gulde edge.
For example, in epitaxially grown front road technique, the surperficial discrete state that causes because of oxidation in the buried regions annealing process propagation that also can when epitaxial diposition, make progress, lateral displacement occurs in the discontinuous position of buried regions that epitaxial diposition is finished under the relative extension in discontinuous position that the rear surface occurs, and this figure deformation is called the extension drift.Stay the mark of follow-up level contraposition during buried regions, drift has also occured in mark in epitaxy technique, simultaneously, the surperficial discrete state that causes because of oxidation in the buried regions annealing process propagation that also can when epitaxial diposition, make progress, figure deformation occurs in the discontinuous position of buried regions that epitaxial diposition is finished under the relative extension in discontinuous position that the rear surface occurs, and this figure deformation is called the extension distortion.Stay the mark of follow-up level contraposition during buried regions, distortion has also occured in mark in epitaxy technique, the alignment mark that need to find front road to stay during follow-up level contraposition, if the extension amount of distortion is very large, marker graphic will diminish in serious contraction, and photoetching just is difficult to find the contraposition signal, and the aligning accuracy of photoetching will be difficult to guarantee even can't contraposition, in sum, research extension amount of distortion and drift value can solve the problem of extension front and back level photoetching aligning accuracy.
At present, the computational methods of traditional extension drift value are, after epitaxial growth steps, central authorities at two adjacent buried regions prepare an isolation, after the annealing semiconductor device is cut into slices, adopt chromic acid corrosion liquid that the section of section is carried out corrosion about 30 seconds, as shown in Figure 1, testing a buried regions 11 with testing equipments such as high resolution optical microscope or scanning electron microscopy (SEM) is a to the distance of described isolation, another buried regions 12 is b to the distance of described isolation 130, measure the thickness c of epitaxial loayer 120, then the extension drift value is (a-b)/2c again.But the method needs section, and depend on corrosive liquid to substrate 110, epitaxial loayer 120, isolation 130 corrosion rates and etching time control requirement, and the process of measuring is loaded down with trivial details, especially for adopting epitaxial loayer 120 rear processing isolation 130 to do the process of contrast, technological process is complicated, process when isolation 130 is rear confirms that just the extension drift values are unusual, epitaxial device has been processed the unusual product of many heats extension drift, monitoring efficiency and having little significance.
At present, the computational methods of traditional extension amount of distortion are before epitaxial growth steps chip to be cut into slices, with testing equipment test badge buried regions window size c such as high resolution optical microscope or scanning electron microscopy (SEM), then, after epitaxial growth steps, chip is cut into slices, with high resolution optical microscope or SEM test badge extension window size d, both differences are exactly the extension amount of distortion.As shown in Figure 2, has mark buried regions window 111 on the substrate 110, mark buried regions window 111 is of a size of c, at substrate 110 growing epitaxial layers 120, because the existence of mark buried regions window 111, so that can produce mark extension window 121 during epitaxial loayer 120 growth, mark extension window 121 is of a size of d, and then amount of distortion is (c-d).But the method step is numerous and diverse, because twice section in front and back is not on the same position of same chip, so be subjected to the influence of fluctuations of chip chamber processing technology larger, all have certain difference between the size c of the mark buried regions window 111 of different chips and between the size d of mark extension window 121, and the method need to be tested the impact of tested equipment state fluctuation at twice in testing equipment, has larger test error, therefore, adopt the precision of this conventional method not good, and complex steps.
Therefore, how to provide a kind of semiconductor device and preparation method thereof, make that the measuring accuracy of extension drift value and extension amount of distortion is high and step is simple, become the problem that those skilled in the art need to solve.
Summary of the invention
The object of the invention is to, a kind of semiconductor device and preparation method thereof is provided, adopt the preparation method of semiconductor device of the present invention to measure the extension drift value, measuring accuracy is high and step is simple.
For solving the problems of the technologies described above, the invention provides a kind of semiconductor device, comprising:
Substrate, described substrate have at least one the first buried regions window and at least one the second buried regions window;
The barrier layer is positioned on described the first buried regions window;
Protective layer is positioned on the other described substrate in described barrier layer;
The intermediate layer is positioned on described the first epitaxial loayer, and the joint of the upper surface of described protective layer and the upper surface on described barrier layer has a First jump, and described First jump forms a contrast window;
Epitaxial loayer is positioned on described barrier layer and the described protective layer described substrate in addition, and described epitaxial loayer has the extension window of described the second buried regions window after epitaxial growth.
Further, described substrate also has by described the first buried regions window is carried out the first buried regions district that Implantation forms, and by described the second buried regions window is carried out the second buried regions district that Implantation forms.
Further, the ion of described Implantation is antimony or arsenic, and the dosage of Implantation is 1E14～1E16.
Further, the material of described protective layer is oxide, nitride, nitrogen oxide or polysilicon, and the thickness of described protective layer is
Further, the thickness on described barrier layer is
Further, the thickness of described epitaxial loayer is 1 μ m～100 μ m.
Further, the edge of described the first buried regions window is to the spacing at the edge of the described epitaxial loayer thickness greater than described epitaxial loayer.
Further, the edge of described the first buried regions window is more than 1.5 times of thickness of described epitaxial loayer to the spacing at the edge of described epitaxial loayer.
Further, described the first buried regions window is identical with the size and shape of the second buried regions window.
Further, the present invention also provides a kind of preparation method of semiconductor device, comprising:
Substrate is provided;
Upper surface growth protecting layer at described substrate;
The described protective layer of selective removal, the described substrate of expose portion is to form at least one the first buried regions zone and at least one the second buried regions zone at described substrate;
Described substrate is carried out PROCESS FOR TREATMENT, form the barrier layer with the described substrate in described the first buried regions zone and the exposure of described the second buried regions zone, simultaneously between described substrate and remaining described protective layer, form the intermediate layer, wherein, the joint of the upper surface of the described protective layer in described the first buried regions zone and the upper surface on described barrier layer has a First jump, described First jump forms a contrast window, it is poor that the joint of the lower surface in described intermediate layer and the lower surface on described barrier layer has a second step, the poor formation one first buried regions window of the described second step in described the first buried regions zone, the poor formation one second buried regions window of the described second step in described the second buried regions zone;
The described protective layer of selective removal, intermediate layer and barrier layer keep described contrast window, and expose described the second buried regions window;
At described the second buried regions window preparation one epitaxial loayer, described epitaxial loayer has the extension window of described the second buried regions window after epitaxial growth.
Further; in the described protective layer step of described selective removal with described described substrate is being carried out between the PROCESS FOR TREATMENT step; also comprise: Implantation is carried out in described the first buried regions zone and the second buried regions zone, to form respectively the first buried regions district and the second buried regions district in the described substrate in described the first buried regions window and the second buried regions window.
Further, the ion of described Implantation is antimony or arsenic, and the dosage of Implantation is 1E14～1E16.
Further, adopt annealing process to form the barrier layer in the described Semiconductor substrate of the first buried regions window and the exposure of the second buried regions window, between described substrate and remaining described protective layer, form the intermediate layer simultaneously.
Further, excavating technology is treated to thermal oxidation technology, hot nitriding process or hot carbonization technique.
Further, the thickness on described barrier layer is
Further, the thickness of described epitaxial loayer is 1 μ m～100 μ m.
Further, the material of described protective layer is oxide, nitride, nitrogen oxide or polysilicon, and the thickness of described protective layer is
Further, the edge of described the first buried regions window is to the spacing at the edge of the described epitaxial loayer thickness greater than described epitaxial loayer.
Further, the edge of described the first buried regions window is more than 1.5 times of thickness of described epitaxial loayer to the spacing at the edge of described epitaxial loayer.
Further, described the first buried regions window is identical with the size and shape of the second buried regions window.
Further, the method of measurement that also comprises the extension drift value of semiconductor device, the method of measurement of described extension drift value comprises: by the distance of more described the first buried regions window and described the second buried regions window and the distance of described the first buried regions window and described extension window, calculate the extension drift value in the epitaxial growth.
Further, the distance of described the first buried regions window and extension window is that the distance of the distance at center of the center of described the first buried regions window and described extension window and described the first buried regions window and the second buried regions window is the distance at the center of the center of described the first buried regions window and described the second buried regions window.
Further, the distance of the distance of described the first buried regions window and described the second buried regions window and described the first buried regions window and described extension window, adopt light microscope or electron microscope to take pictures, then process through image and accurately measure, or adopt step instrument to measure.
Further, also comprise the method for measurement of the extension amount of distortion of semiconductor device, the method for measurement of described extension amount of distortion comprises: by the width of more described the first buried regions window and the width of described extension window, calculate the extension amount of distortion in the epitaxial growth.
Further, the width of the width of described the first buried regions window and described extension window adopts light microscope or electron microscope to take pictures, and then processes through image and accurately measures, or adopt step instrument to measure.
Compared with prior art, semiconductor device provided by the invention and preparation method thereof has the following advantages:
1, semiconductor device provided by the invention and preparation method thereof, by preparing without the contrast window of extension drift and the extension window of extension drift, obtain the extension drift value by the distance that relatively contrasts window and extension window, and obtain extension drift value and extension amount of distortion by relatively contrasting window and extension window, compared with prior art, this method of measurement directly directly can observe by light microscope or electron microscope, need not cut into slices, save cost, and reach the effect of timely monitoring; The present invention can be on the same position of semiconductor device property testing once, be not subjected to the impact of processing technology and the fluctuation of testing equipment state between semiconductor device, have good measuring accuracy; And the preparation flow of method of the present invention and semiconductor device matches, and does not need section, so that this method can combine with the preparation of product sheet, need not special preparation test semiconductor device, saves cost; Method of the present invention can record extension drift value and extension amount of distortion simultaneously by a structure, and is simple and convenient.
2, semiconductor device provided by the invention and preparation method thereof; in the step on the described protective layer of selective removal, intermediate layer and barrier layer; described contrast window is kept; the distance of described contrast window and extension window is the distance at the center of the center of described contrast window and described extension window; can avoid described substrate is carried out epitaxy technique with the process of grown epitaxial layer in extension distortion the size of described contrast window and extension window is exerted an influence, thereby the distance of further avoiding extension to distort to described contrast window and extension window exerts an influence.
3, semiconductor device provided by the invention and preparation method thereof, Implantation is carried out in described the first buried regions zone and the second buried regions zone, the truth of the semiconductor device of die region be can simulate really, extension drift value and extension amount of distortion in the semiconductor device reflected really.
4, semiconductor device provided by the invention and preparation method thereof; the edge of described the first buried regions window is to the spacing at the edge of the described epitaxial loayer thickness greater than described epitaxial loayer; can avoid when the described epitaxial loayer of growth; the gathering of polycrystalline can appear in described contrast window edge; the polycrystalline of avoiding further assembling can accumulate to the expansion of contrast window, thereby protection contrast window is not covered.
5, semiconductor device provided by the invention and preparation method thereof, described the first buried regions window is identical with the size and shape of the second buried regions window, make semiconductor device in preparation process, it is minimum that described the first buried regions window and the second buried regions window are affected by shape etc. to be down to, to reduce error, make under identical process conditions, to possess best contrast and accuracy.
Description of drawings
Fig. 1 is the schematic diagram of measuring extension drift value method in the prior art;
Fig. 2 is the schematic diagram of measuring extension amount of distortion method in the prior art;
Fig. 3 is the flow chart of the preparation method of semiconductor device in one embodiment of the invention;
Fig. 4 a-Fig. 4 i is the schematic diagram of the preparation method of semiconductor device in one embodiment of the invention;
Fig. 5 is the schematic diagram of the preparation method of semiconductor device in further embodiment of this invention.
Embodiment
Below in conjunction with schematic diagram semiconductor device of the present invention and preparation method thereof is described in more detail, the preferred embodiments of the present invention have wherein been represented, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.In the following description, be not described in detail known function and structure, the confusion because they can make the present invention owing to unnecessary details.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details to realize developer's specific objective, for example according to relevant system or relevant commercial restriction, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but only be routine work to those skilled in the art.
In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-accurately ratio, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
Core concept of the present invention is, a kind of semiconductor device is provided, and comprises substrate, and described substrate has at least one the first buried regions window and at least one the second buried regions window; The barrier layer is positioned on described the first buried regions window; Protective layer is positioned at intermediate layer on the other described substrate in described barrier layer, is positioned on described the first epitaxial loayer, and the joint of the upper surface of described protective layer and the upper surface on described barrier layer has a First jump, and described First jump forms a contrast window; Epitaxial loayer; be positioned on described barrier layer and the described protective layer described substrate in addition; described epitaxial loayer has the extension window of described the second buried regions window after epitaxial growth, thus the described contrast window that obtains having the described extension window of extension deformation and do not have extension deformation.
Further, in conjunction with above-mentioned semiconductor device, the present invention also provides a kind of preparation method of semiconductor device, comprising:
Step S01 provides substrate;
Step S02 is at the upper surface growth protecting layer of described substrate;
Step S03, the described protective layer of selective removal, the described substrate of expose portion is to form at least one the first buried regions zone and at least one the second buried regions zone at described substrate;
Step S04, described substrate is carried out PROCESS FOR TREATMENT, form the barrier layer with the described substrate in described the first buried regions zone and the exposure of described the second buried regions zone, simultaneously between described substrate and remaining described protective layer, form the intermediate layer, wherein, the joint of the upper surface of described protective layer and the upper surface on described barrier layer has a First jump, described First jump forms a contrast window, it is poor that the joint of the lower surface in described intermediate layer and the lower surface on described barrier layer has a second step, the poor formation one first buried regions window of the described second step in described the first buried regions zone, the poor formation one second buried regions window of the described second step in described the second buried regions zone;
Step S05, the described protective layer of selective removal, intermediate layer and barrier layer keep described contrast window, and expose described the second buried regions window;
Step S06, at described the second buried regions window preparation one epitaxial loayer, described epitaxial loayer has the extension window of described the second buried regions window after epitaxial growth.
Below enumerate several embodiment of described semiconductor device and preparation method thereof, to clearly demonstrate content of the present invention, will be clear that, content of the present invention is not restricted to following examples, and the improvement of other routine techniques means by those of ordinary skills is also within thought range of the present invention.
Below in conjunction with Fig. 3 and Fig. 4 a-Fig. 4 i specify in the present embodiment semiconductor device with and preparation method thereof.Wherein, Fig. 3 is the flow chart of the preparation method of semiconductor device in one embodiment of the invention; Fig. 4 a-Fig. 4 i is the schematic diagram of the preparation method of semiconductor device in one embodiment of the invention.
At first, carry out step S01, substrate 210 is provided, in the present embodiment, described substrate 210 has at least one the first graph area 211 and at least one second graph district 212, such as Fig. 4 a, described substrate 210 is divided into described the first graph area 211 and described second graph district 212, conveniently in step S03, only described the second buried regions window is carried out epitaxial growth.Wherein, the material of substrate 210 can be silicon, germanium, III-V group element compound substrate or well known to a person skilled in the art other semiconductive material substrate, what adopt in the present embodiment is silicon substrate, can be formed with the function elements such as MOS field-effect transistor, bipolar transistor in the substrate 210 that adopts in the present embodiment.For bipolarity product substrate mainly take P (111) crystal orientation as main.
Then, carry out step S02, at the upper surface growth protecting layer 221 of described substrate 210.
In the present embodiment; described substrate 210 has at least one the first graph area 211 and at least one second graph district 212; so better; at the first graph area 211 of described substrate 210 and the upper surface growth protecting floor 221 in second graph district 212; such as Fig. 4 b; protective layer 221 both can play a part to limit shape when preparation the first buried regions window and the second buried regions window, can protect the first buried regions window 251 not covered by epitaxial loayer when step S03 again.The material of described protective layer 221 is oxide, nitride, nitrogen oxide or polysilicon; what adopt in the present embodiment is silica; because silica can protect the shape of contrast window can not change in step S06 effectively; but the material of protective layer 221 is not limited to silica; material such as protective layer 221 is silicon nitride, silicon oxynitride, polysilicon, also within thought range of the present invention.What the thickness of described protective layer 221 was better is
Preferably
If protective layer 221 thickness are partially thin, the step of the contrast window 251 that forms in step S04 can be on the low side, can cause follow-up test can not tell the pattern of contrast window.
Then, carry out step S03, the described protective layer 221 of selective removal, the described protective layer of selective removal is to form at least one the first buried regions zone 241 and at least one the second buried regions zone 242 at described substrate 221.Because in the present embodiment, described substrate 210 has at least one the first graph area 211 and at least one second graph district 212, so form the first buried regions zone 241 in described the first graph area 211, and 212 form the second buried regions zone 242 in described second graph district, shown in Fig. 4 c.Better, adopt the described protective layer 221 of method selective removal of dry etching, with dry etching so that the step gradient in the 241 and second buried regions zone 242, described the first buried regions zone is precipitous.
Better, the 241 and second buried regions zone 242, described the first buried regions zone is positioned at the non-die region of described substrate 210, such as scribing road or monitored space, and is independent one photoetching level, do not affect tube core processing and service behaviour, and the epitaxially grown extension drift value of reflection that can be strictly according to the facts.
In the present embodiment, between step S03 and step S04, also comprise: Implantation is carried out in the 241 and second buried regions zone 242, described the first buried regions zone, with described substrate 210 interior the first buried regions district 213 and the second buried regions districts 214 of forming respectively in the 241 and second buried regions zone 242, the first buried regions zone, shown in Fig. 4 d, Implantation is carried out in the 241 and second buried regions zone 242, described the first buried regions zone can simulate really the truth of the semiconductor device of die region, reflect really the extension drift value in the semiconductor device.Wherein, the kind of the ion of described Implantation and implantation dosage be not for to do concrete restriction, according to concrete technology establishment.Better, ion is antimony or arsenic, implantation dosage is 1E14～1E16.Wherein ion is that antimony or arsenic belong to sluggish donor impurity, can guarantee in the follow-up high-temperature technology, the impurity in the first buried regions district 213 and the second buried regions district 214 can not spread active, can not cause the first buried regions district 213 and the second buried regions district 214 concentration partially light, cause other device architecture contaminations, transoid.Wherein dosage is at 1E14～1E16, and the partially dense meeting of dosage causes annealing insufficient, occurs buried regions dyeing when the first buried regions district 213 and 214 annealing of the second buried regions district.
Then; carry out step S04; described substrate 210 is carried out PROCESS FOR TREATMENT; form barrier layer 222 with the described substrate that exposes in the 241 and second buried regions zone, the first buried regions zone 242; between described substrate 210 and remaining described protective layer 221, form simultaneously intermediate layer 223; wherein; the joint of the upper surface of the described protective layer 221 in described the first buried regions zone 241 and the upper surface on described barrier layer 222 has a First jump; described First jump forms a contrast window 261; it is poor that the joint of the lower surface on the lower surface in described intermediate layer 223 and described barrier layer 222 has a second step; the poor formation one first buried regions window 251 of the described second step in described the first buried regions zone 241; the poor formation one second buried regions window 252 of the described second step in described the second buried regions zone 242; shown in Fig. 4 e; adopt the method on the barrier layer 222 of the present embodiment in step S06, effectively to protect contrast window 261 not covered by epitaxial loayer 232.
Better, adopt thermochemical processes, for example thermal oxidation technology, hot nitriding process or hot carbonization technique.What adopt in the present embodiment is thermal oxidation technology, so the formed barrier layer 222 of the present embodiment and intermediate layer 223 are oxide layer, but forms nitration case by hot nitriding process, also within thought range of the present invention.Better, the thickness on described barrier layer is
Preferably
So that the first buried regions window 251, the second buried regions window 252 and contrast window all have obvious shoulder height.
In the present embodiment, owing to having increased the step of the 241 and second buried regions zone 242, described the first buried regions zone being carried out Implantation, so the thermochemical processes of the present embodiment is thermal anneal process, but also can be after the thermal anneal process independent step thermochemical processes that adds.
Because the substrate 210 in the present embodiment is silicon, so when carrying out thermochemical processes, when passing into oxygen, the first buried regions district 213 and the second buried regions district 214 are directly exposed in the atmosphere of oxygen, the silicon in the first buried regions district 213 and the second buried regions district 214 directly and oxygen react and be grown to barrier layer 222, thereby react away a part of silicon in the first buried regions district 213 and the second buried regions district 214, and to outgrowth part oxide layer.Shown in Fig. 4 d, barrier layer 222 is divided into two parts: downwards reactive moieties 222a and upwards growth part 222b.The thickness on barrier layer 222 is T1, then according to thermal oxidation technology, needs the silicon of reaction 0.46 * T1 thickness, and namely the thickness of reactive moieties 222a is 0.46T1 downwards.Simultaneously; in the first buried regions district 213 and the zone beyond the second buried regions district 214 of described substrate 210; because matcoveredn 221 covers described substrate 210; so the silicon that can react less generates thinner intermediate layer 223; in like manner, intermediate layer 223 also is divided into two parts: downwards reactive moieties 223a and upwards growth part 223b.The thickness in intermediate layer 223 is T2, needs the silicon of reaction 0.46 * T2 thickness.
Concrete, because barrier layer 222 is different with the thickness in intermediate layer 223, so the silicon thickness that react corresponding below is also different, the lower reactive moieties 222a on barrier layer and the lower reactive moieties 223a in intermediate layer form a step appearance, thereby keep the first buried regions window 251 and the second buried regions window 252.Owing to the upwards different step differences that form of the height from protective layer 221 of growth part 222b on barrier layer, contrast window 261 thereby form again, utilize just this step to form each alignment mark in the semiconductor technology.Deformation does not occur in size, shape and position that contrast window 261 has kept the first buried regions window 251.For example, the thickness of the protective layer 221 of preparation is in the present embodiment
The thickness on barrier layer 222 is
Then the thickness of the lower reactive moieties 222a on barrier layer 222 is
The upwards thickness of growth part 222b on barrier layer is
Because the very thin thickness in intermediate layer 223 can be ignored with respect to barrier layer 222, so the shoulder height of the first buried regions window 251 and the second buried regions window 252 is
The shoulder height of contrast window 261 is
Be easy to differentiate.
Since in the described protective layer step of selective removal with dry etching so that the step gradient of described the first buried regions window 251 and the second buried regions window 252 is precipitous; so that the step gradient of described the first buried regions window 251 among this step S04, the second buried regions window 252 and contrast window 261 is precipitous, be beneficial to shape, position and the width of the described contrast window 261 of follow-up resolution and extension window 262.
Subsequently; carry out step S05; in the present embodiment; remove described protective layer 221, barrier layer 222 and intermediate layer 223 in the described second graph district 212; so that the first buried regions window 251 edges have protective layer 221 and intermediate layer 223, thereby keep contrast window 261, and when grown epitaxial layer; protective layer 221 and intermediate layer 223 can protect contrast window 261 not covered by epitaxial loayer effectively, shown in Fig. 4 f.
At last, carry out step S06, adopt conventional epitaxy technique, at described substrate top surface grown epitaxial layer 232, because epitaxially grown character, epitaxial loayer 232 can copy the shape of the second buried regions window 252 but can drift about, to produce extension window 262, shown in 4g.General, the thickness of described epitaxial loayer 232 is 1 μ m～100 μ m, such as 5 μ m, 10 μ m, 20 μ m, 50 μ m, 80 μ m, but is not limited to this scope.Again because in the present embodiment; does not remove in step S05 in described protective layer 221 on described the first graph area 211, barrier layer 222 and intermediate layer 223; so the described protective layer 221 that is retained, barrier layer 222 and intermediate layer 223 when carrying out epitaxy technique as protection; 232 of described epitaxial loayers are formed on the described substrate in described second graph district 212, so described contrast window 261 is retained.In the present embodiment, carry out among the step S06, because epitaxially grown character, extension drift and extension distortion occur in the meeting of the second buried regions window 252 simultaneously, the deformation major embodiment of directions X is the extension drift, and the deformation major embodiment of Y-direction is the extension distortion, shown in Fig. 4 h.
In the present embodiment, the preparation method of described semiconductor device also comprises the method for measurement of the extension drift value of described semiconductor device.
At first, between step S04 and step S05, measure the distance of described the first buried regions window 213 and the second buried regions window 214.Better, the distance of described the first buried regions window 213 and the second buried regions window 214 can be the distance at the center of the center of described the first buried regions window 213 and the second buried regions window 214, avoiding the impact that in step S06 polycrystalline is assembled and extension distorts, but the distance of described the first buried regions window 213 and the second buried regions window 214 can be the distance at the center of the center of described the first buried regions window 213 and the second buried regions window 214.In the method for measurement to the extension drift value, do not need to satisfy described the first buried regions window 251 identical with the size and shape of the second buried regions window 252, because the key of the measurement of extension drift value is a contrast points (center of described the first buried regions window 213) and a shift point (center of described the second buried regions window 214), do not need the size and shape of described the first buried regions window 251 and the second buried regions window 252 is limited.And contrast points and shift point is the center of described the first buried regions window 213 and the center of described the second buried regions window 214 not necessarily, the high order end of the first buried regions window 213 as described in such as contrast points among Fig. 4 g being, shift point is the high order end of described the second buried regions window 214, the distance of stating the first buried regions window 213 and the second buried regions window 214 can be for the distance of the high order end of the high order end of described the first buried regions window 213 and the second buried regions window 214, also within thought range of the present invention.
Better, adopt light microscope or electron microscope to take pictures, then process through image and accurately measure, also can adopt step instrument to measure.In this step, in the photo of shooting, because the poor existence of second step, contrast window 261 and the second buried regions window 252 can be directly seen, the distance at the center of the center of described the first buried regions window 213 and the second buried regions window 214 can be determined.Shown in Fig. 4 e, the width of described the first buried regions window 213 is X1, the width of described the second buried regions window 214 is X2, the edge of described the first buried regions window 213 is X3 to the distance at the edge of the second buried regions window 214, then the center of the center of described the first buried regions window 213 and the second buried regions window 214 apart from S1=(X1+X2)/2+X3.In the present embodiment, the distance of measuring the center of the center of described the first buried regions window 213 and the second buried regions window 214 can also be located between step S03 and the step S04, also can measure the distance at the center of the center of described the first buried regions window 213 and the second buried regions window 214.
Then, measure the distance of described the first buried regions window 213 and described extension window 262.Polycrystalline is assembled and the impact of extension distortion in the step S06, and the distance of described the first buried regions window 213 and extension window 262 can be the distance at the center of the center of described the first buried regions window 213 and extension window 262.Better, adopt light microscope or electron microscope to take pictures, then process through image and accurately measure, also can adopt step instrument to measure.In the present embodiment, owing to having the contrast window 261 that extension deformation does not occur on described the first buried regions window 213, reach original position that contrast window 261 has kept described the first buried regions window 213, so in this step, because the poor existence of second step, can directly see contrast window 261 and extension window 262 in the photo of taking, shown in Fig. 4 g, the distance of contrast window 261 and extension window 262 is the distance of described the first buried regions window 213 and described extension window 262.The width of described contrast window 261 is X4, the width of described extension window 262 is X5, the edge of described contrast window 261 is X6 to the distance at the edge of extension window 262, then the center of the center of described contrast window 261 and extension window 262 apart from S2=(X4+X5)/2+X6.
At last, calculate the extension drift value in the epitaxial growth, in the present embodiment, the extension drift does not occur in described contrast window 261, and extension drift, then extension drift value occur described extension window 262
Wherein H is the thickness of epitaxial loayer 232, and the thickness H of epitaxial loayer 232 can adopt conventional method to record.The direction of the positive negative indication of extension drift value S drift wherein, when extension drift value S for just, the drift of extension be described along the positive direction of X-axis, when extension drift value S bears, the drift of extension is described along the negative direction of X-axis, shown in Fig. 4 g.
In the present embodiment, the preparation method of described semiconductor device also comprises the method for measurement of the extension amount of distortion of described semiconductor device.
Described substrate is carried out epitaxy technique with the grown epitaxial layer step after, measure the width X9 of described contrast window 261 and the width X10 of extension window 262, obtain amount of distortion in the epitaxial growth through contrast, shown in Fig. 4 h and Fig. 4 i, wherein Fig. 4 h is the vertical view of Fig. 4 g, and Fig. 4 i is the cutaway view of described semiconductor device on Y-direction.Better, adopt light microscope or electron microscope to take pictures, then process through image and accurately measure, also can adopt step instrument to measure.In the present embodiment, the width of the width of the first buried regions window 251 and the second buried regions window 252 big or small the same, again because the width of the first buried regions window 251 is the same with the width of contrast window 261, so the width of the contrast width of window 261 and the first buried regions window 251 and the second buried regions window 252 is big or small the same, the difference that namely contrasts the width X10 of the width X9 of window 261 and extension window 262 is amount of distortion.In the method for measurement of the extension amount of distortion of the present embodiment, described the first buried regions window 251 is identical with the size and shape of the second buried regions window 252, make semiconductor device in preparation process, reducing described contrast window 261 and extension window 262 affected by shape etc. to be down to minimum, to reduce error, make under identical process conditions, to possess best contrast and accuracy.When the size and shape of described the first buried regions window 251 and the second buried regions window 252 was identical, described amount of distortion was width poor of the width of described contrast window 261 and extension window 262.
Because in the present embodiment; in step S03; removed the described protective layer 221 in the described second graph district 212; barrier layer 222 and intermediate layer 223; and kept described protective layer 221 on described the first graph area 211; barrier layer 222 and intermediate layer 223; when carrying out that described substrate carried out epitaxy technique with the grown epitaxial layer step; the gathering of polycrystalline can occur in epitaxial loayer 232 and the edge that described protective layer 221 contacts with intermediate layer 223; the gathering of polycrystalline can be by covering described protective layer 221 to 211 interior expansions of described second graph district; if the edge of described the first buried regions window 251 is too small to the spacing at the edge of described epitaxial loayer 232; epitaxial loayer 232 can cover described protective layer 221 fully, thereby may cover described contrast window 231.In the present embodiment, for preventing in step S06, the growth of epitaxial loayer 232 can cover described contrast window 231 and change the size of described contrast window 231, and the edge of described the first buried regions window 251 is to the spacing at the edge of described epitaxial loayer 232 thickness greater than described epitaxial loayer 232.Preferably, the edge of described the first buried regions window 251 is more than 1.5 times of thickness of described epitaxial loayer 232 to the spacing at the edge of described epitaxial loayer 232.When the edge of described the first buried regions window 251 to the spacing at the edge of described epitaxial loayer 232 be described epitaxial loayer 232 thickness more than 1.5 times the time, can avoid better the growth of epitaxial loayer 232 to cover described contrast window 231, to keep the big or small constant of described contrast window 231.
Because in the present embodiment, the edge of described the first buried regions window 251 is to the spacing at the edge of described epitaxial loayer 232 thickness greater than described epitaxial loayer 232, the growth of epitaxial loayer 232 can not cover described contrast window 231, so, in the present invention, the distance of described the first buried regions window 213 and the second buried regions window 214 also can be the distance at the edge of the edge of described the first buried regions window 213 and the second buried regions window 214, corresponding, the distance of described contrast window 261 and extension window 262 is the distance at the edge of the edge of described contrast window 261 and extension window 262.
In the present embodiment, the width of described the second buried regions window 252 (Y-direction) is greater than the thickness H of described epitaxial loayer 232, can prevent in step S06, described extension window 262 in the epitaxial loayer 232 is submerged owing to the extension distortion occuring, thereby can't detect, as when as described in the width of the second buried regions window 252 be as described in epitaxial loayer 232 thickness H more than 1.5 times the time, can avoid better described extension window 262 to be submerged.But the width X2 of described the second buried regions window 252 does not need certain condition that satisfies greater than the thickness H of described epitaxial loayer 232, as long as the width X2 of described the second buried regions window 252 of energy guarantees that described extension window 262 is submerged.In the present embodiment, the width of described the first buried regions window 251 equals the width of described the second buried regions window 252, so the width of described the first buried regions window 251 is also greater than the thickness H of described epitaxial loayer 232.
Adopt structure such as Fig. 4 g of the semiconductor device of the present embodiment preparation, substrate 210, described substrate 210 has at least one the first graph area 211 and at least one second graph district 212, have the first buried regions window 251 in described the first graph area 211, have the second buried regions window 252 in the described second graph district 212; The first graph area epitaxial loayer, be positioned on the first graph area 211 of described substrate, described the first graph area epitaxial loayer comprises protective layer 221, barrier layer 222, and intermediate layer 223, described barrier layer 222 is positioned on described the first buried regions window 251, described intermediate layer 223 is positioned on described the first buried regions window 251 described the first graph area 211 in addition, described protective layer 221 is positioned on the described intermediate layer 223, has contrast window 261 on the described barrier layer 222, size, the consistent size of described contrast window 261 and described the first buried regions window 213; Epitaxial loayer 262 is positioned in the second graph district 212 of described substrate 210, and described epitaxial loayer 232 has the extension window 262 of described the second buried regions window 252 after epitaxial growth.
In the present embodiment; also can be among step S05; remove the described protective layer of part and the described intermediate layer of part on described the first graph area; remove simultaneously described protective layer, protective layer and intermediate layer in the described second graph district; can when step S06, keep described contrast window 261 equally; can be used for the measurement to extension drift value and extension amount of distortion, as shown in Figure 5, also within thought range of the present invention.
In the present embodiment, the number in the first graph area 211 and second graph district 212, Rankine-Hugoniot relations are not subjected to concrete restriction.Those skilled in the art should be understandable that, in actual applications, can select as required suitable size, number and spacing.Can be pointed out that, select more size, number and spacing, and by the present embodiment method correlated phenomena such as extension drift value in the more data research epitaxy technique can be arranged.Semiconductor device of the present invention can also comprise the function element that some need to prepare, such as CMOS pipe, diode etc., when needs detect the extension drift value of this semiconductor device, this semiconductor device is positioned over testing equipment to be tested, if the extension drift value of this semiconductor device meets the requirements, this semiconductor device can be proceeded next step technological process, the preparation of continue function device, need not section, scrap, save cost.
The present invention is not limited to above-described embodiment, as as described in the step of substrate preparation one epitaxial loayer, the first buried regions window 251 is covered with photoresist, then at substrate 210 growing epitaxial layers 232, because epitaxially grown characteristic, described epitaxial loayer 232 has the extension window 262 of described the second buried regions window 252 after epitaxial growth, by oxidation technology the photoresist on the first buried regions window 251 is removed again, expose the first buried regions window 251, same directly by contrasting width or the distance of the first buried regions window 251 and extension window 262, obtain extension amount of distortion or extension drift value, also within thought range of the present invention.
In sum, the invention provides a kind of semiconductor device, comprise substrate, described substrate has at least one the first graph area and at least one second graph district, has the first buried regions window in described the first graph area, has the second buried regions window in the described second graph district; The barrier layer is positioned on described the first buried regions window, has the contrast window on the described barrier layer, size, the consistent size of described contrast window and described the first buried regions window; Epitaxial loayer is positioned in the second graph district of described substrate, and described epitaxial loayer has the extension window of described the second buried regions window after epitaxial growth.Compared with prior art, the present invention has the following advantages:
1, semiconductor device provided by the invention and preparation method thereof, by preparing without the contrast window of extension drift and the extension window of extension drift, obtain the extension drift value by the distance that relatively contrasts window and extension window, and obtain extension drift value and extension amount of distortion by relatively contrasting window and extension window, compared with prior art, this method of measurement directly directly can observe by light microscope or electron microscope, need not cut into slices, save cost, and reach the effect of timely monitoring; The present invention can be on the same position of semiconductor device property testing once, be not subjected to the impact of processing technology and the fluctuation of testing equipment state between semiconductor device, have good measuring accuracy; And the preparation flow of method of the present invention and semiconductor device matches, and does not need section, so that this method can combine with the preparation of product sheet, need not special preparation test semiconductor device, saves cost; Method of the present invention can record extension drift value and extension amount of distortion simultaneously by a structure, and is simple and convenient.
2, semiconductor device provided by the invention and preparation method thereof; in the step on the described protective layer of selective removal, intermediate layer and barrier layer; described contrast window is kept; the distance of described contrast window and extension window is the distance at the center of the center of described contrast window and described extension window; can avoid described substrate is carried out epitaxy technique with the process of grown epitaxial layer in extension distortion the size of described contrast window and extension window is exerted an influence, thereby the distance of further avoiding extension to distort to described contrast window and extension window exerts an influence.
3, semiconductor device provided by the invention and preparation method thereof, Implantation is carried out in described the first buried regions zone and the second buried regions zone, the truth of the semiconductor device of die region be can simulate really, extension drift value and extension amount of distortion in the semiconductor device reflected really.
4, semiconductor device provided by the invention and preparation method thereof; the edge of described the first buried regions window is to the spacing at the edge of the described epitaxial loayer thickness greater than described epitaxial loayer; can avoid when the described epitaxial loayer of growth; the gathering of polycrystalline can appear in described contrast window edge; the polycrystalline of avoiding further assembling can accumulate to the expansion of contrast window, thereby protection contrast window is not covered.
5, semiconductor device provided by the invention and preparation method thereof, described the first buried regions window is identical with the size and shape of the second buried regions window, make semiconductor device in preparation process, it is minimum that described the first buried regions window and the second buried regions window are affected by shape etc. to be down to, to reduce error, make under identical process conditions, to possess best contrast and accuracy.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (25)
1. semiconductor device comprises:
Substrate, described substrate have at least one the first buried regions window and at least one the second buried regions window;
The barrier layer is positioned on described the first buried regions window;
Protective layer is positioned on the other described substrate in described barrier layer;
The intermediate layer is positioned on described the first epitaxial loayer, and the joint of the upper surface of described protective layer and the upper surface on described barrier layer has a First jump, and described First jump forms a contrast window;
Epitaxial loayer is positioned on described barrier layer and the described protective layer described substrate in addition, and described epitaxial loayer has the extension window of described the second buried regions window after epitaxial growth.
2. semiconductor device as claimed in claim 1, it is characterized in that, described substrate also has by described the first buried regions window is carried out the first buried regions district that Implantation forms, and by described the second buried regions window is carried out the second buried regions district that Implantation forms.
3. semiconductor device as claimed in claim 2 is characterized in that, the ion of described Implantation is antimony or arsenic, and the dosage of Implantation is 1E14～1E16.
4. semiconductor device as claimed in claim 1 is characterized in that, the material of described protective layer is oxide, nitride, nitrogen oxide or polysilicon, and the thickness of described protective layer is
5. semiconductor device as claimed in claim 1 is characterized in that, the thickness on described barrier layer is
6. semiconductor device as claimed in claim 1 is characterized in that, the thickness of described epitaxial loayer is 1 μ m～100 μ m.
7. such as the described semiconductor device of any one among the claim 1-6, it is characterized in that, the edge of described the first buried regions window is to the spacing at the edge of the described epitaxial loayer thickness greater than described epitaxial loayer.
8. semiconductor device as claimed in claim 7 is characterized in that, the edge of described the first buried regions window is more than 1.5 times of thickness of described epitaxial loayer to the spacing at the edge of described epitaxial loayer.
9. such as the described semiconductor device of any one among the claim 1-6, it is characterized in that, described the first buried regions window is identical with the size and shape of the second buried regions window.
10. the preparation method of a semiconductor device comprises:
Substrate is provided;
Upper surface growth protecting layer at described substrate;
The described protective layer of selective removal, the described substrate of expose portion is to form at least one the first buried regions zone and at least one the second buried regions zone at described substrate;
Described substrate is carried out PROCESS FOR TREATMENT, form the barrier layer with the described substrate in described the first buried regions zone and the exposure of described the second buried regions zone, simultaneously between described substrate and remaining described protective layer, form the intermediate layer, wherein, the joint of the upper surface of the described protective layer in described the first buried regions zone and the upper surface on described barrier layer has a First jump, described First jump forms a contrast window, it is poor that the joint of the lower surface in described intermediate layer and the lower surface on described barrier layer has a second step, the poor formation one first buried regions window of the described second step in described the first buried regions zone, the poor formation one second buried regions window of the described second step in described the second buried regions zone;
The described protective layer of selective removal, intermediate layer and barrier layer keep described contrast window, and expose described the second buried regions window;
At described the second buried regions window preparation one epitaxial loayer, described epitaxial loayer has the extension window of described the second buried regions window after epitaxial growth.
11. the preparation method of semiconductor device as claimed in claim 10; it is characterized in that; in the described protective layer step of described selective removal with described described substrate is being carried out between the PROCESS FOR TREATMENT step; also comprise: Implantation is carried out in described the first buried regions zone and the second buried regions zone, to form respectively the first buried regions district and the second buried regions district in the described substrate in described the first buried regions window and the second buried regions window.
12. the preparation method of semiconductor device as claimed in claim 11 is characterized in that, the ion of described Implantation is antimony or arsenic, and the dosage of Implantation is 1E14～1E16.
13. the preparation method of semiconductor device as claimed in claim 11; it is characterized in that; adopt annealing process to form the barrier layer in the described Semiconductor substrate of the first buried regions window and the exposure of the second buried regions window, between described substrate and remaining described protective layer, form the intermediate layer simultaneously.
14. the preparation method of semiconductor device as claimed in claim 10 is characterized in that, excavating technology is treated to thermal oxidation technology, hot nitriding process or hot carbonization technique.
15. the preparation method of semiconductor device as claimed in claim 10 is characterized in that, the thickness on described barrier layer is
16. the preparation method of semiconductor device as claimed in claim 10 is characterized in that, the thickness of described epitaxial loayer is 1 μ m～100 μ m.
17. the preparation method of semiconductor device as claimed in claim 10 is characterized in that, the material of described protective layer is oxide, nitride, nitrogen oxide or polysilicon, and the thickness of described protective layer is
18. the preparation method of semiconductor device as claimed in claim 10 is characterized in that, the edge of described the first buried regions window is to the spacing at the edge of the described epitaxial loayer thickness greater than described epitaxial loayer.
19. the preparation method of semiconductor device as claimed in claim 18 is characterized in that, the edge of described the first buried regions window is more than 1.5 times of thickness of described epitaxial loayer to the spacing at the edge of described epitaxial loayer.
20. the preparation method of semiconductor device as claimed in claim 10 is characterized in that, described the first buried regions window is identical with the size and shape of the second buried regions window.
21. the preparation method such as the described semiconductor device of any one among the claim 10-19, it is characterized in that, the method of measurement that also comprises the extension drift value of semiconductor device, the method of measurement of described extension drift value comprises: by the distance of more described the first buried regions window and described the second buried regions window and the distance of described the first buried regions window and described extension window, calculate the extension drift value in the epitaxial growth.
22. the preparation method of semiconductor device as claimed in claim 21, it is characterized in that, the distance of described the first buried regions window and extension window is that the distance of the distance at center of the center of described the first buried regions window and described extension window and described the first buried regions window and the second buried regions window is the distance at the center of the center of described the first buried regions window and described the second buried regions window.
23. the preparation method of semiconductor device as claimed in claim 21, it is characterized in that, the distance of the distance of described the first buried regions window and described the second buried regions window and described the first buried regions window and described extension window, adopt light microscope or electron microscope to take pictures, then process through image and accurately measure, or adopt step instrument to measure.
24. the preparation method such as the described semiconductor device of any one among the claim 10-20, it is characterized in that, the method of measurement that also comprises the extension amount of distortion of semiconductor device, the method of measurement of described extension amount of distortion comprises: by the width of more described the first buried regions window and the width of described extension window, calculate the extension amount of distortion in the epitaxial growth.
25. the preparation method of semiconductor device as claimed in claim 24, it is characterized in that, the width of the width of described the first buried regions window and described extension window, adopt light microscope or electron microscope to take pictures, then process through image and accurately measure, or adopt step instrument to measure.
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