CN102931187A - Layout structure of temperature compensation clock chip - Google Patents
Layout structure of temperature compensation clock chip Download PDFInfo
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- CN102931187A CN102931187A CN2012104119538A CN201210411953A CN102931187A CN 102931187 A CN102931187 A CN 102931187A CN 2012104119538 A CN2012104119538 A CN 2012104119538A CN 201210411953 A CN201210411953 A CN 201210411953A CN 102931187 A CN102931187 A CN 102931187A
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Abstract
The invention discloses a layout structure of a temperature compensation clock chip, and belongs to the technical field of integrated circuit design. A clock chip layout comprises a first layout area, a second layout area, a third layout area, a fourth layout area, a fifth layout area, a sixth layout area, a seventh layout area, an eighth layout area and a ninth layout area, wherein the first layout area is connected with all the other layout areas; the second layout area is connected with the first, fourth, eighth and ninth layout areas; the third layout area is connected with the first, fourth, fifth, sixth, eighth and ninth layout areas; the fourth layout area is connected with all the other layout areas; the fifth layout area is connected with the first, third, fourth, sixth, eighth and ninth layout areas; the sixth layout area is connected with the first, third, fourth, fifth, eighth and ninth layout areas; the seventh layout area is connected with the first, second, fourth, sixth, eighth and ninth layout areas; the eighth layout area is connected with all the other layout areas; and the ninth layout area is distributed along the three directions which are respectively at the upper part, lower part and right side of the layout. According to the temperature compensation clock chip, the positions of all the layout areas are fixed, so that the layout design of the temperature compensation clock chip is optimized, and the interference of digital noise to a temperature detection/analog circuit can be reduced.
Description
Technical field
The present invention relates to the integrated circuit (IC) design technical field, particularly a kind of temperature compensation clock chip domain structure
Background technology
For some TT﹠C system or portable equipment, often need to show and setting-up time.At present, there is multiple real-time timepiece chip that this class function is provided on the market.This programmable real-time timepiece chip is built-in programmable calendar clock and certain RAM memory, be used for setting and the holding time, the other general built-in leap year bucking-out system of clock chip, timing is very accurate, because crystal oscillator can be subject to the impact of temperature, in order to guarantee that clock is in the different zone of temperature, the areal Various Seasonal has an accurately timing, the clock chip that has also extra design temperature test and treatment circuit, be used for feeding back to crystal oscillator, realize temperature compensation function.The temperature compensation clock is low in energy consumption, adopts the reserce cell power supply, can work former of system's end points.These advantages of real-time clock so that its extensive use with need the time showing occasion.
Summary of the invention
In order to solve owing to layout design is unreasonable, the problem that causes the temperature compensated clock chip design, the invention provides a kind of temperature compensation clock chip domain structure,, described temperature compensated clock chip layout is comprised of the 1st domain district, the 2nd domain district, the 3rd domain district, the 4th domain district, the 5th domain district, the 6th domain district, the 7th domain district, the 8th domain district and the 9th domain district;
Described the 1st domain district is EEPROM domain district, and described EEPROM domain district is driven by EEPROM and EEPROM and forms.
Described the 2nd domain district is automatic control figure temperature compensating crystal oscillator domain district; described automatic control figure temperature compensating crystal oscillator domain district is comprised of control circuit, capacitor array, switch arrays and amplifier, and each part has independently guard ring.
Described the 3rd domain district is 4 bit DAC domain districts, and described DAC domain district is comprised of electric resistance array and switch arrays, has designed guard ring.
Described the 4th domain district is temperature detection domain district, described be temperature detection domain district by, temperature measurement circuit domain, amplifier domain, voltage buffering domain and resistance trim domain and form temperature measurement circuit domain common centroid.
Described the 5th domain district is comparator domain district, has designed independently guard ring.
Described the 6th domain district is benchmark domain district, specifically comprises current reference domain and voltage reference domain, and triode common centroid in the described benchmark domain has independently guard ring.
Described the 7th domain district is 8 ADC domain districts, specifically comprises 8 domains and reference voltage buffering.
Described the 8th domain district is digital control domain district, specifically comprises and external communication module domain, test mode control circuit domain, RAM domain.
Described the 8th domain district is input/output interface domain district, specifically comprises 12 parallel input/output interfaces.
Description of drawings
Fig. 1 is embodiment of the invention temperature compensation clock chip domain structure schematic diagram.
Claims (5)
1. the domain structure of a temperature compensated clock chip, it is characterized in that described temperature compensated clock chip layout is comprised of the 1st domain district, the 2nd domain district, the 3rd domain district, the 4th domain district, the 5th domain district, the 6th domain district, the 7th domain district, the 8th domain district and the 9th domain district; All domain districts, the 1st domain district and other all link to each other, the 2nd domain district all links to each other with 1,4,8,9 domain districts, the 3rd domain district all links to each other with 1,4,5,6,8,9 domain districts, all domain districts, the 4th domain district and other all link to each other, the 5th domain district all links to each other with 1,3,4,6,8,9 domain districts, the 6th domain district all links to each other with 1,3,4,5,8,9 domain districts, the 7th domain district all links to each other with 1,2,4,6,8,9 domain districts, the 8th domain district all links to each other with all domain districts, and the 9th domain district is distributed in upper and lower, right three directions of domain.
2. temperature compensated clock chip layout structure as claimed in claim 1 is characterized in that, described the 1st domain district is EEPROM domain district.
3. temperature compensated clock chip layout structure as claimed in claim 1 is characterized in that, described the 3rd domain district is 4 bit DAC, is close to the 5th domain district that it need to be controlled, and has reduced parasitic effects.
4. temperature compensated clock chip layout structure as claimed in claim 1 is characterized in that, described the 5th domain district is temperature sensing circuit, places away from digital circuit, thereby has reduced the interference of clock signal.
5. temperature compensated clock chip layout structure as claimed in claim 1 is characterized in that, described the 8th domain is divided into and external communication module domain, test mode control circuit domain, RAM domain.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012104119538A CN102931187A (en) | 2012-10-25 | 2012-10-25 | Layout structure of temperature compensation clock chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012104119538A CN102931187A (en) | 2012-10-25 | 2012-10-25 | Layout structure of temperature compensation clock chip |
Publications (1)
| Publication Number | Publication Date |
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| CN102931187A true CN102931187A (en) | 2013-02-13 |
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| CN2012104119538A Pending CN102931187A (en) | 2012-10-25 | 2012-10-25 | Layout structure of temperature compensation clock chip |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104485330A (en) * | 2014-11-18 | 2015-04-01 | 北京七芯中创科技有限公司 | Layout structure of high-precision temperature-measuring chip with ultra-high ESD (Electronic Static Discharge) circuit |
| CN113728387A (en) * | 2019-04-04 | 2021-11-30 | 美光科技公司 | Apparatus and method for staggered timing of targeted refresh operations |
| US11935576B2 (en) | 2018-12-03 | 2024-03-19 | Micron Technology, Inc. | Semiconductor device performing row hammer refresh operation |
| US11955158B2 (en) | 2018-10-31 | 2024-04-09 | Micron Technology, Inc. | Apparatuses and methods for access based refresh timing |
-
2012
- 2012-10-25 CN CN2012104119538A patent/CN102931187A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104485330A (en) * | 2014-11-18 | 2015-04-01 | 北京七芯中创科技有限公司 | Layout structure of high-precision temperature-measuring chip with ultra-high ESD (Electronic Static Discharge) circuit |
| US11955158B2 (en) | 2018-10-31 | 2024-04-09 | Micron Technology, Inc. | Apparatuses and methods for access based refresh timing |
| US11935576B2 (en) | 2018-12-03 | 2024-03-19 | Micron Technology, Inc. | Semiconductor device performing row hammer refresh operation |
| CN113728387A (en) * | 2019-04-04 | 2021-11-30 | 美光科技公司 | Apparatus and method for staggered timing of targeted refresh operations |
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| DD01 | Delivery of document by public notice |
Addressee: Beijing 7Q Technology Co., Ltd. Document name: the First Notification of an Office Action |
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| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130213 |