CN102931172B - Test device and preparation method thereof, semiconductor device and preparation method thereof - Google Patents
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Abstract
A kind of test device and preparation method thereof, semiconductor device and preparation method thereof.Described test device includes: Semiconductor substrate；It is positioned at the dielectric layer in described Semiconductor substrate, the material of described dielectric layer is the silicon oxide adopting TEOS to be reaction source formation, described dielectric layer includes metal plug and pseudo-contact hole, the material of described pseudo-contact hole includes tungsten, and the upper surface area of described pseudo-contact hole and the ratio of the upper surface area of whole dielectric layer are more than or equal to 20%；Being positioned at the electric connection line on described dielectric layer, the material of described electric connection line includes copper, aluminum or albronze.Described semiconductor device includes multiple chip and the Cutting Road between described chip, and described Cutting Road includes above-mentioned test device.The present invention can improve the bonding force in test device between electric connection line and dielectric layer, the final stable performance ensureing semiconductor device.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular a kind of test device and preparation method thereof, semiconductor device and preparation method thereof.
Background technology
In field of semiconductor manufacture, would generally manufacturing simultaneously multiple have mutually isostructural chip (Die) on a block semiconductor wafer, the region between adjacent chips is Cutting Road.In order to ensure the reliability of semiconductor device, it will usually make multiple test device in Cutting Road, for some key parameters (such as RS resistance value) are tested.Different semiconductor device is likely to need to obtain different test parameters, and different test parameters is likely to need to adopt different test devices.When completing chip manufacturing process, and after the test device detection in Cutting Road is all met the requirements, it is possible to along predetermined Cutting Road, wafer is cut to separate chip, then again chip is packaged.
The upper surface of existing test device is the electric connection line for realizing electrical connection, and for for stopping the dielectric layer of insulation below electric connection line, and dielectric layer is to adopt TEOS(tetraethyl orthosilicate) silicon oxide that formed for reaction source.Fig. 1 illustrates a concrete test device in prior art.With reference to shown in Fig. 1, described test device includes from bottom to up successively:
Semiconductor substrate 10；
It is positioned at the oxide layer 20 in Semiconductor substrate 10；
Being positioned at the dielectric layer 30 in oxide layer 20, the material of described dielectric layer 30 is the silicon oxide adopting TEOS to be reaction source formation, needs to arrange metal plug (not shown) in described dielectric layer 30 according to concrete connection；
Being positioned at the electric connection line 40 of described dielectric layer 30 upper surface, for accessing the signal of telecommunication of test, the material of described electric connection line 40 includes copper, aluminum or albronze.
More it is referred to the Chinese patent application file that application publication number is CN101807535A about the technology testing device in Cutting Road.
But after cutting along the Cutting Road including above-mentioned test device, the electrical property of corresponding chip there occurs great changes, thus causing the chip of whole wafer all to be scrapped.
Therefore, the appearance how avoiding the problems referred to above just becomes one of those skilled in the art's problem demanding prompt solution.
Summary of the invention
The problem that this invention address that is to provide a kind of test device and preparation method thereof, semiconductor device and preparation method thereof, to improve in test device the bonding force between electric connection line and dielectric layer, the stable performance of final maintenance semiconductor device.
For solving the problems referred to above, the invention provides a kind of semiconductor device, including:
Semiconductor substrate；
It is positioned at the dielectric layer in described Semiconductor substrate, the material of described dielectric layer is the silicon oxide adopting TEOS to be reaction source formation, described dielectric layer includes metal plug and pseudo-contact hole (DummyContact), the material of described pseudo-contact hole includes tungsten, and the upper surface area of described pseudo-contact hole and the ratio of the upper surface area of whole dielectric layer are more than or equal to 20%；
Being positioned at the electric connection line on described dielectric layer, the material of described electric connection line includes copper, aluminum or albronze.
Alternatively, including oxide layer between described Semiconductor substrate and described dielectric layer, the material of described oxide layer is silicon oxide；Described test device also includes: the insulating barrier between described oxide layer and described dielectric layer.
Alternatively, described insulating barrier includes first area and second area, described first area is different with the material of second area, the material of described first area is the silicon oxide adopting TEOS to be reaction source formation, described second area is at least corresponding with all of pseudo-contact hole, and the material of described second area is polysilicon or silicon nitride.
Alternatively, the size of described metal plug and described pseudo-contact hole is equivalently-sized.
Alternatively, the side of described pseudo-contact hole also includes isolation side walls (spacer).
Alternatively, described isolation side walls includes the first silicon oxide layer, silicon nitride layer and the second silicon oxide layer that stacking is arranged.
Alternatively, described pseudo-contact hole includes titanium layer, titanium nitride layer and the tungsten layer that stacking is arranged.
For solving the problems referred to above, present invention also offers a kind of semiconductor device, including multiple chips and the Cutting Road between described chip, described Cutting Road includes above-mentioned test device.
Alternatively, described chip includes metal plug；The size of the metal plug of described chip, material are corresponding identical with the size of metal plug of described test device, material respectively；The size of the metal plug of described chip is equivalently-sized with the pseudo-contact hole of described test device.
Alternatively, described chip includes grid structure and is positioned at the isolation side walls of grid structure side；The side of described pseudo-contact hole includes isolation side walls；The isolation side walls of described chip is all corresponding identical with the size of the isolation side walls of described pseudo-contact hole and material.
For solving the problems referred to above, present invention also offers a kind of manufacture method testing device, including:
Semiconductor substrate is provided；
Adopting TEOS is the dielectric layer that reaction source forms silica material on the semiconductor substrate, described dielectric layer is formed multiple through hole, the through hole of fractional numbers is filled the first material and forms metal plug, residue through hole is filled the second material and forms pseudo-contact hole, described second material includes tungsten, and the upper surface area of described pseudo-contact hole and the ratio of the upper surface area of whole dielectric layer are more than or equal to 20%；
Forming electric connection line on described dielectric layer, the material of described electric connection line includes copper, aluminum or albronze.
Alternatively, the manufacture method of described test device also includes: before forming described dielectric layer, forming oxide layer on the semiconductor substrate, the material of described oxide layer is silicon oxide；After forming the oxide layer and formed before described dielectric layer, in the described oxide layer of part, insulating barrier is at least formed；Forming dielectric layer in described oxide layer and on described insulating barrier, described pseudo-contact hole is positioned on described insulating barrier.
Alternatively, form described pseudo-contact hole to include: form isolation side walls in the side of described pseudo-contact hole.
For solving the problems referred to above, present invention also offers the manufacture method of a kind of semiconductor device, described semiconductor device includes multiple chip and the Cutting Road between described chip, adopts above-mentioned manufacture method to form described test device in described Cutting Road.
Alternatively, described chip includes metal plug；Concurrently form the metal plug of described chip and the metal plug of described test device.
Alternatively, described chip includes grid structure and is positioned at the isolation side walls of grid structure side；The side of described pseudo-contact hole includes isolation side walls；Concurrently form the isolation side walls of described pseudo-contact hole and the isolation side walls of described chip.
Compared with prior art, technical solution of the present invention has the advantage that
1) present invention adds pseudo-contact hole in the dielectric layer, the material of described pseudo-contact hole includes tungsten, due to tungsten and copper, the bonding force of aluminum or copper aluminum is relatively good, in the upper surface area of the described pseudo-contact hole of guarantee and the ratio of the upper surface area of whole dielectric layer under the premise more than or equal to 20%, can ensure that electric connection line and dielectric layer are pasted together securely very much, thus when cutting is arranged in the test device of Cutting Road, electric connection line will not come off everywhere, more will not be splashed in chip, thus ensure that the stability of semiconductor device, improve the yield rate of chip.
Additionally, described dielectric layer includes metal plug, by concurrently forming multiple through hole in the dielectric layer, the contact hole making fractional numbers becomes described metal plug, the contact hole of remaining number becomes described pseudo-contact hole, thus saving process, reduces production cost.
2) in alternative, oxide layer is included between described Semiconductor substrate and described dielectric layer, when the material of described oxide layer is silicon oxide, described test device also includes the insulating barrier between described oxide layer and described dielectric layer, described insulating barrier not only can as etch dielectric layer time stop-layer, but also can ensure that the electrical property of test device does not change because of the increase of pseudo-contact hole.
3) in alternative, described chip includes metal plug and isolation side walls, described pseudo-contact hole includes isolation side walls, the metal plug of the metal plug of described chip and described test device can concurrently form, the isolation side walls of the isolation side walls of described chip and described pseudo-contact hole can also concurrently form, such that it is able to save processing step further, reduce production cost.
Accompanying drawing explanation
Fig. 1 is a kind of structural representation testing device in prior art；
Fig. 2 is a kind of structural representation testing device in the embodiment of the present invention；
Fig. 3 is the structural representation of pseudo-contact hole in Fig. 2；
Fig. 4 is the structural representation of another kind of test device in prior art；
Fig. 5 is the structural representation of another test device in the embodiment of the present invention.
Detailed description of the invention
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Elaborating a lot of detail in the following description so that fully understanding the present invention, but the present invention can also adopt other to be different from alternate manner described here to be implemented, therefore the present invention is not by the restriction of following public specific embodiment.
Just as described in the background section, the channel region of prior art wafer includes one or more test device, and after chip being divided along channel region, the electrical property of chip there occurs great changes compared with before dividing, thus causing that chip cannot use, finally make whole wafer loss.
Through research, inventor finds that its Producing reason is in that: the material of the electric connection line of test device upper space includes copper, aluminum or albronze, the material of the dielectric layer below electric connection line is the silicon oxide adopting TEOS to be reaction source formation, owing to described silicon oxide is smaller with the bonding force of copper, aluminum or albronze, so causing that dielectric layer is poor with the cohesive of electric connection line.When chip being divided along channel region, inevitably cut described test device, owing to the cohesive of dielectric layer Yu electric connection line is poor, therefore to I haven't seen you for ages, generating portion comes off (peeling) to electric connection line, the electric connection line come off can sputter and enter in adjacent chip, the parts that should insulate in this chip Central Plains are made to achieve electrical connection, thus greatly changing the electrical property of chip.Because the detection to single separate chip cannot be realized, thus scrapping of all chips on this wafer being caused.Additionally, by the wafer after amplifying cutting it have also been discovered that: the electric connection line of the subregion upper surface that cut test device should stay all comes off, thus further demonstrating the correctness of the studies above.
For the problems referred to above, the invention provides a kind of test device and preparation method thereof, semiconductor device and preparation method thereof, the bonding force of dielectric layer and electric connection line is improved by increasing the mode of pseudo-contact hole in the dielectric layer, prevent the impact on chip electrical property that comes off of electric connection line in cutting process, qualified separate chip may finally be obtained.
It is described in detail below in conjunction with accompanying drawing.
With reference to shown in Fig. 2, present embodiment one embodiment provides a kind of test device, including:
Semiconductor substrate 110；
Being positioned at the oxide layer 120 in described Semiconductor substrate 110, described oxide layer 120 is as channel layer；
Being positioned at the insulating barrier in described oxide layer 120, described insulating barrier includes first area 130 and second area 140；
It is positioned at the dielectric layer 150 on described insulating barrier, the material of described dielectric layer 150 is the silicon oxide adopting TEOS to be reaction source formation, described dielectric layer 150 includes metal plug (not shown) and pseudo-contact hole 160, and described second area 140 is at least corresponding with all of pseudo-contact hole 160；
It is positioned at the electric connection line 180 on described dielectric layer 150.
Compared with the test device shown in Fig. 1 in prior art, the present embodiment adds pseudo-contact hole 160 in dielectric layer 150, to improve the bonding force between dielectric layer 150 and electric connection layer 180；And adding insulating barrier between dielectric layer 150 and oxide layer 120, the electrical property to ensure test device does not change.
Described Semiconductor substrate 110 can be Silicon Wafer, it is also possible to being other semi-conducting materials, it is well known to those skilled in the art, and does not repeat them here.
The material of described oxide layer 120 can be silicon oxide, and described silicon oxide can adopt physical vapor deposition (PVD) method, chemical vapour deposition (CVD) (CVD) method or boiler tube method to be formed.Specifically, the thickness range of described oxide layer 120 can be but not limited to 200 angstroms ~ 800 angstroms.
In described insulating barrier, the material of first area 130 can be the silicon oxide adopting TEOS to be reaction source formation, and the material of second area 140 can be polysilicon or silicon nitride.Specifically, the thickness range of described insulating barrier can be but not limited to 4000 angstroms ~ 5000 angstroms.
It should be noted that in other embodiments of the invention, described first area 130 can also adopt other any insulant, and described second area 140 can adopt any insulant outside silicon oxide.
Metal plug in described dielectric layer 150 can need to be configured according to actual electrical connection, and the material of described metal plug can be copper, aluminum or albronze, and it is same as the prior art, does not repeat them here.
Preferably, the size of described metal plug and described pseudo-contact hole 160 equivalently-sized, such that it is able to form the through hole corresponding with metal plug and puppet contact hole 160 in dielectric layer 150 simultaneously, save processing step, reduce cost.It should be noted that in other embodiments of the invention, the size of the size of described metal plug and described pseudo-contact hole 160 can also be different, and it is not intended to protection scope of the present invention.
The effect of described pseudo-contact hole 160 is in that to improve the bonding force between dielectric layer 150 and electric connection line 180.Owing to the material of electric connection line 180 includes copper, aluminum or albronze more, and tungsten and copper, aluminum or copper aluminum have bigger bonding force, and therefore the material of pseudo-contact hole 160 is mainly tungsten.
In order to ensure to cut in the process of described test device, electric connection line 180 will not fall off, the described upper surface area of pseudo-contact hole 160 needs more than or equal to 20% with the ratio of the upper surface area of whole dielectric layer 150, as: 20%, 30%, 50%, 80% or 95% etc., otherwise it is unable to reach the purpose preventing electric connection line 180 from coming off.Found by follow-up detection, when the upper surface area of described pseudo-contact hole 160 meets above-mentioned condition, by the wafer after amplifying cutting it appeared that the cut electric connection line testing the subregion upper surface that device should stay all exists, namely do not fall off；And the electrical property of separate chip is also without changing, it is possible to realize the function of correspondence well.It should be noted that the upper surface area of described whole dielectric layer 150 includes the upper surface area of described pseudo-contact hole 160 and the upper surface area of described metal plug simultaneously.
In conjunction with referring to figs. 2 and 3 shown, the side of described pseudo-contact hole 160 can include isolation side walls 170, for realizing the isolation to described pseudo-contact hole 160.Specifically, described isolation side walls 170 can include the first silicon oxide layer 171, silicon nitride layer 172 and the second silicon oxide layer 173 that stacking is arranged.It should be noted that in other embodiments of the invention, described isolation side walls 170 can simply be one layer or two-layer, does not repeat them here.
In conjunction with reference to shown in Fig. 3, described pseudo-contact hole 160 can include titanium layer 161, titanium nitride layer 162 and the tungsten layer 163 that stacking is arranged.Wherein, described titanium layer 161 is possible to prevent tungsten layer 163 to blast, and described titanium nitride layer 162 can improve tungsten layer 163 and the bonding force of titanium layer 161, and described tungsten layer 163 can improve the bonding force of dielectric layer 150 and electric connection line 180.It should be noted that described titanium layer 161 and titanium nitride layer 162 may be replaced by the other materials with identical function, it is not intended to protection scope of the present invention.
Specifically, the thickness of described first silicon oxide layer 171 can be but not limited to 100 angstroms ~ 200 angstroms, the thickness of silicon nitride layer 172 can be but not limited to 100 angstroms ~ 300 angstroms, the thickness of the second silicon oxide layer 173 can be but not limited to 100 angstroms ~ 3000 angstroms, the thickness of titanium layer 161 can be but not limited to 350 angstroms ~ 650 angstroms, and the thickness of titanium nitride layer 162 can be but not limited to 600 angstroms ~ 1000 angstroms.
The present embodiment improves the bonding force between dielectric layer 150 and electric connection line 180 by pseudo-contact hole 160, thus when cutting this test device, electric connection line 180 does not come off, accordingly without the electrical property affecting other devices.Additionally, due to the barrier effect of insulating barrier, it is also ensured that the pseudo-contact hole 160 of increase is without influence on the electrical property of test device.
Fig. 4 illustrates the structure of another kind of test device in prior art, itself and Fig. 1 shown test device are distinctive in that: also set up a functional layer between dielectric layer 30 and oxide layer 20, described functional layer includes first area 50 and second area 60, wherein the material of first area 50 is the silicon oxide adopting TEOS to be reaction source formation, and the material of second area 60 is polysilicon.Owing to silicon oxide and polysilicon are all non-conductive, therefore this functional layer insulation.Owing to now dielectric layer 30 is all identical with Fig. 1 with annexation with the material of electric connection line 40, the problem that the electric connection line 40 therefore existed in cutting comes off yet suffers from.
For the test device shown in Fig. 4, the test device that another embodiment of present embodiment provides is as it is shown in figure 5, include:
Semiconductor substrate 110；
It is positioned at the oxide layer 120 in described Semiconductor substrate 110；
Being positioned at the functional layer in described oxide layer 120, described functional layer includes first area 50 and second area 60, and the material of described first area 50 is the silicon oxide adopting TEOS to be reaction source formation, and the material of second area 60 is polysilicon；
It is positioned at the dielectric layer 150 on described insulating barrier, the material of described dielectric layer 150 is the silicon oxide adopting TEOS to be reaction source formation, described dielectric layer 150 includes metal plug (not shown) and pseudo-contact hole 160, described pseudo-contact hole 160 is positioned on described second area 60, and the ratio of the upper surface area of described pseudo-contact hole 160 and the upper surface area of whole dielectric layer 150 is more than or equal to 20%, the side of described pseudo-contact hole 160 includes isolation side walls 170；
It is positioned at the electric connection line 180 on described dielectric layer 150.
Owing to the test device shown in Fig. 4 having included between oxide layer 20 and dielectric layer 30 insulating barrier, and the material of the second area of insulating barrier is different from the material of dielectric layer 30, therefore when the region of the second area 60 of insulating barrier is sufficiently large, when the ratio of the upper surface area of the pseudo-contact hole 160 that ensure that in Fig. 5 on second area 60 and the upper surface area of whole dielectric layer 150 is more than or equal to 20%, the test device shown in Fig. 5 compared with Fig. 4 then without adding insulating barrier more.
The present embodiment again may be by pseudo-contact hole 160 and improves the bonding force between dielectric layer 150 and electric connection line 180, thus when cutting this test device, electric connection line 180 does not come off, accordingly without the electrical property affecting other devices.Additionally, due to the barrier effect of second area 60, it is also ensured that the pseudo-contact hole 160 of increase is without influence on the electrical property of test device.
In other embodiments of the invention, when in Fig. 4, the ratio of the upper surface area of the second area 60 of insulating barrier and the upper surface area of whole dielectric layer is less than 20%, then need nonetheless remain for arranging between functional layer and dielectric layer 150 in Figure 5 a layer insulating more, the insulating barrier that this newly-installed insulating barrier includes first area 130 and second area 140 with Fig. 2 is similar, does not repeat them here.
It should be noted that in other embodiments of the invention, described test device can also adopt other concrete structures, and it is not intended to protection scope of the present invention.
Correspondingly, present embodiment additionally provides a kind of manufacture method testing device, including:
Step S1, it is provided that Semiconductor substrate；
Step S2, adopting TEOS is the dielectric layer that reaction source forms silica material on the semiconductor substrate, described dielectric layer is formed multiple through hole, the through hole of fractional numbers is filled the first material and forms metal plug, residue through hole is filled the second material and forms pseudo-contact hole, described second material includes tungsten, and the upper surface area of described pseudo-contact hole and the ratio of the upper surface area of whole dielectric layer are more than or equal to 20%；
Step S3, forms electric connection line on described dielectric layer.
Wherein, the material of described electric connection line can include copper, aluminum or albronze；Described first material can include copper, aluminum or albronze；Described second material can include successively: titanium, titanium nitride and tungsten.
Described dielectric layer is formed the step of through hole and to fill the first material in through-holes all same as the prior art with the step forming metal plug, and it is similar with the step of formation metal plug with the step forming pseudo-contact hole to fill the second material in through-holes, all repeat no more at this.
Forming described pseudo-contact hole can also include: form isolation side walls in the side of described pseudo-contact hole, the step forming described isolation side walls is identical with the step forming isolation side walls in prior art in the side of grid structure.
Preferably, before forming described dielectric layer, it is possible to adopting PVD, CVD or boiler tube method to form oxide layer on the semiconductor substrate, the material of described oxide layer is silicon oxide；After forming the oxide layer and formed before described dielectric layer, it is possible to adopt and first deposit the technique etched again in the described oxide layer of part, at least form the insulating barrier of the material such as polysilicon or silicon nitride；Thus forming dielectric layer in described oxide layer and on described insulating barrier, described pseudo-contact hole is positioned on described insulating barrier.
Adopt the test device that said method makes specifically be referred to Fig. 2 and illustrate accordingly, do not repeat them here.
Correspondingly, present embodiment additionally provides a kind of semiconductor device, and including multiple chips and the Cutting Road between described chip, it is one or more that described Cutting Road includes in above-mentioned test device.
Described chip can include metal plug and grid structure, and the side of described grid structure can also include isolation side walls, and it is known for those skilled in the art, does not repeat them here.Specifically, described chip can be planar power MOS pipe, it is also possible to be other devices.
Preferably, the size of the metal plug of described chip, material can be corresponding identical with the size of metal plug of described test device, material respectively；The size of the pseudo-contact hole of the size of the metal plug of described chip and described test device can be identical, such that it is able to concurrently form the metal plug of described chip and the metal plug of described test device, to save process, reduces production cost.
Preferably, size and the material of the isolation side walls of described chip and the isolation side walls of described pseudo-contact hole can be all corresponding identical, such that it is able to concurrently form the isolation side walls of described chip and the isolation side walls of described pseudo-contact hole, it is possible to save process further, reduce production cost.
Owing to the bonding force of test device dielectric layer and electric connection line is relatively good, therefore when along Cutting Road cutting test device, do not have electric connection line and come off, thus ensure that the electric performance stablity of separate chip.
Correspondingly, present embodiment additionally provides the manufacture method of a kind of semiconductor device, and described semiconductor device includes multiple chip and the Cutting Road between described chip, adopts the manufacture method of above-mentioned test device to form described test device in described Cutting Road.
Preferably, when described chip includes metal plug, it is possible to concurrently form the metal plug of described chip and the metal plug of described test device, such that it is able to save process, production cost is reduced.
Preferably, when described chip includes grid structure and is positioned at the isolation side walls of grid structure side, when the side of described pseudo-contact hole includes isolation side walls, the isolation side walls of described pseudo-contact hole and the isolation side walls of described chip can be concurrently formed, such that it is able to save process further, reduce production cost.
Additionally, when described chip includes polysilicon gate, the first area of the insulating barrier between dielectric layer and oxide layer can concurrently form with described polysilicon gate, such that it is able to save process further, reduce production cost.
Under the present embodiment adeciduate premise of electric connection line in ensureing test device, adopting the process identical with chip, thus method simply and readily realizes, production cost is relatively low.
Although the present invention discloses as above with preferred embodiment, but the present invention is not limited to this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (16)
1. a test device, it is characterised in that including:
Semiconductor substrate；
It is positioned at the dielectric layer in described Semiconductor substrate, the material of described dielectric layer is the silicon oxide adopting tetraethyl orthosilicate to be reaction source formation, described dielectric layer includes the metal plug and the puppet contact hole that run through its thickness, and the upper surface of described pseudo-contact hole and dielectric layer upper surface flush, the material of described pseudo-contact hole includes tungsten, and the upper surface area of described pseudo-contact hole and the ratio of the upper surface area of whole dielectric layer are more than or equal to 20%；
Being positioned at the electric connection line on described dielectric layer, described electric connection line covers described pseudo-contact hole, and the material of described electric connection line includes copper, aluminum or albronze.
2. testing device as claimed in claim 1, it is characterised in that include oxide layer between described Semiconductor substrate and described dielectric layer, the material of described oxide layer is silicon oxide；Described test device also includes: the insulating barrier between described oxide layer and described dielectric layer.
3. test device as claimed in claim 2, it is characterized in that, described insulating barrier includes first area and second area, the material of described first area is the silicon oxide adopting tetraethyl orthosilicate to be reaction source formation, described second area is at least corresponding with all of pseudo-contact hole, and the material of described second area is polysilicon or silicon nitride.
4. test device as claimed in claim 1, it is characterised in that the size of described metal plug is equivalently-sized with described pseudo-contact hole.
5. test device as claimed in claim 1, it is characterised in that the side of described pseudo-contact hole also includes isolation side walls.
6. test device as claimed in claim 5, it is characterised in that described isolation side walls includes the first silicon oxide layer, silicon nitride layer and the second silicon oxide layer that on left and right directions, stacking is arranged.
7. test device as claimed in claim 1, it is characterised in that described pseudo-contact hole includes titanium layer, titanium nitride layer and the tungsten layer that on left and right directions, stacking is arranged.
8. a semiconductor device, it is characterised in that include multiple chip and the Cutting Road between described chip, described Cutting Road includes the test device as according to any one of claim 1 to 7.
9. semiconductor device as claimed in claim 8, it is characterised in that described chip includes metal plug；The size of the metal plug of described chip, material are corresponding identical with the size of metal plug of described test device, material respectively；The size of the metal plug of described chip is equivalently-sized with the pseudo-contact hole of described test device.
10. semiconductor device as claimed in claim 8, it is characterised in that described chip includes grid structure and is positioned at the isolation side walls of grid structure side；The side of described pseudo-contact hole includes isolation side walls；The isolation side walls of described chip is all corresponding identical with the size of the isolation side walls of described pseudo-contact hole and material.
11. the manufacture method testing device, it is characterised in that including:
Semiconductor substrate is provided；
Adopting tetraethyl orthosilicate is the dielectric layer that reaction source forms silica material on the semiconductor substrate, described dielectric layer is formed multiple through hole running through its thickness, the through hole of fractional numbers is filled the first material and forms metal plug, residue through hole is filled the second material and forms pseudo-contact hole, the upper surface of described pseudo-contact hole and dielectric layer upper surface flush, described second material includes tungsten, and the upper surface area of described pseudo-contact hole and the ratio of the upper surface area of whole dielectric layer are more than or equal to 20%；
Forming electric connection line on described dielectric layer, described electric connection line covers described pseudo-contact hole, and the material of described electric connection line includes copper, aluminum or albronze.
12. test the manufacture method of device as claimed in claim 11, it is characterised in that also include:
Before forming described dielectric layer, forming oxide layer on the semiconductor substrate, the material of described oxide layer is silicon oxide；
After the described oxide layer of formation and before forming described dielectric layer, in the described oxide layer of part, at least form insulating barrier；
Forming dielectric layer in described oxide layer and on described insulating barrier, described pseudo-contact hole is positioned on described insulating barrier.
13. test the manufacture method of device as claimed in claim 12, it is characterised in that form described pseudo-contact hole and include: form isolation side walls in the side of described pseudo-contact hole.
14. the manufacture method of a semiconductor device, described semiconductor device includes multiple chip and the Cutting Road between described chip, it is characterized in that, adopt manufacture method according to any one of claim 11 to 13 as described in Cutting Road formed described test device.
15. the manufacture method of semiconductor device as claimed in claim 14, it is characterised in that described chip includes metal plug；Concurrently form the metal plug of described chip and the metal plug of described test device.
16. the manufacture method of semiconductor device as claimed in claim 14, it is characterised in that described chip includes grid structure and is positioned at the isolation side walls of grid structure side；The side of described pseudo-contact hole includes isolation side walls；Concurrently form the isolation side walls of described pseudo-contact hole and the isolation side walls of described chip.
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