CN102931172A - Test device, test device manufacturing method, semiconductor device and semiconductor device manufacturing method - Google Patents
Test device, test device manufacturing method, semiconductor device and semiconductor device manufacturing method Download PDFInfo
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- CN102931172A CN102931172A CN2012104727711A CN201210472771A CN102931172A CN 102931172 A CN102931172 A CN 102931172A CN 2012104727711 A CN2012104727711 A CN 2012104727711A CN 201210472771 A CN201210472771 A CN 201210472771A CN 102931172 A CN102931172 A CN 102931172A
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Abstract
The invention discloses a test device, a test device manufacturing method, a semiconductor device and a semiconductor device manufacturing method. The test device comprises a semiconductor substrate, a dielectric layer positioned on the semiconductor substrate and an electrical connecting line positioned on the dielectric layer, wherein the dielectric layer is made from silicon oxide formed by adopting TEOS (tetraethyl orthosilicate) as a reaction source; the dielectric layer comprises metal plugs and dummy contacts; the dummy contacts can be made of tungsten; the ratio of the upper surface area of the dummy contacts to the upper surface area of the whole dielectric layer is greater than or equal to 20 percent; and the electrical connecting line can be made of copper, aluminum or copper aluminum alloy. The semiconductor device comprises a plurality of dies and cutting channels positioned between the dies, and the cutting channels comprise the test devices. According to the invention, the adhesive force between the electrical connecting line and the dielectric layer of the test device can be increased and finally the stable performance of the semiconductor device can be ensured.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular a kind of test component and preparation method thereof, semiconductor device and preparation method thereof.
Background technology
In the field of semiconductor manufacture, usually can make simultaneously a plurality of chips (Die) with same structure on a block semiconductor wafer, the zone between the adjacent chips is Cutting Road.In order to guarantee the reliability of semiconductor device, usually can in Cutting Road, make a plurality of test components, be used for some key parameters (as: RS resistance value) are tested.Different semiconductor device may need to obtain different test parameters, and different test parameters may need to adopt different test components.When finishing chip manufacturing process, and, just can form separate chip to wafer cutting along the Cutting Road of being scheduled to, and then chip is encapsulated after test all meets the requirements the test component in the Cutting Road.
The upper surface of existing test component is the electric connection line that is electrically connected for realizing, below the electric connection line for being used for stopping the dielectric layer of insulation, and dielectric layer is to adopt the TEOS(tetraethoxysilane) be the silica of reaction source formation.Fig. 1 shows concrete test component in the prior art.With reference to shown in Figure 1, described test component comprises from bottom to up successively:
Be positioned at the oxide layer 20 on the Semiconductor substrate 10;
Be positioned at the dielectric layer 30 on the oxide layer 20, the material of described dielectric layer 30 is the silica that reaction source forms for adopting TEOS, according to concrete connection needs the metal plug (not shown) is set in described dielectric layer 30;
Be positioned at the electric connection line 40 of described dielectric layer 30 upper surfaces, be used for the signal of telecommunication of access test usefulness, the material of described electric connection line 40 comprises copper, aluminium or albronze.
More technology about test component in the Cutting Road can the application reference publication No. be the Chinese patent application file of CN101807535A.
But after cutting along the Cutting Road that comprises above-mentioned test component, great changes have occured in the electrical property of corresponding chip, thereby cause the chip of whole wafer all to be scrapped.
Therefore, how to avoid the appearance of the problems referred to above just to become one of those skilled in the art's problem demanding prompt solution.
Summary of the invention
The problem that the present invention solves provides a kind of test component and preparation method thereof, semiconductor device and preparation method thereof, with the bonding force between electric connection line and the dielectric layer in the raising test component, the stable performance that finally keeps semiconductor device.
For addressing the above problem, the invention provides a kind of semiconductor device, comprising:
Semiconductor substrate;
Be positioned at the dielectric layer on the described Semiconductor substrate, the material of described dielectric layer is the silica that reaction source forms for adopting TEOS, comprise metal plug and pseudo-contact hole (DummyContact) in the described dielectric layer, the material of described pseudo-contact hole comprises tungsten, and the ratio of the upper surface area of described pseudo-contact hole and the upper surface area of whole dielectric layer is more than or equal to 20%;
Be positioned at the electric connection line on the described dielectric layer, the material of described electric connection line comprises copper, aluminium or albronze.
Alternatively, comprise oxide layer between described Semiconductor substrate and the described dielectric layer, the material of described oxide layer is silica; Described test component also comprises: the insulating barrier between described oxide layer and described dielectric layer.
Alternatively, described insulating barrier comprises first area and second area, the material of described first area and second area is different, the material of described first area is the silica that reaction source forms for adopting TEOS, described second area is corresponding with all pseudo-contact holes at least, and the material of described second area is polysilicon or silicon nitride.
Alternatively, the size of described metal plug and described pseudo-contact hole is measure-alike.
Alternatively, the side of described pseudo-contact hole also comprises isolation side walls (spacer).
Alternatively, described isolation side walls comprises the first silicon oxide layer, silicon nitride layer and second silicon oxide layer of stacked setting.
Alternatively, described pseudo-contact hole comprises titanium layer, titanium nitride layer and the tungsten layer of stacked setting.
For addressing the above problem, the present invention also provides a kind of semiconductor device, comprises a plurality of chips and the Cutting Road between described chip, comprises above-mentioned test component in the described Cutting Road.
Alternatively, described chip comprises metal plug; The size of the metal plug of described chip, material respectively size, the material with the metal plug of described test component are corresponding identical; The size of the metal plug of described chip and the pseudo-contact hole of described test component measure-alike.
Alternatively, described chip comprises grid structure and the isolation side walls that is positioned at the grid structure side; The side of described pseudo-contact hole comprises isolation side walls; The isolation side walls of described chip is all corresponding identical with size and the material of the isolation side walls of described pseudo-contact hole.
For addressing the above problem, the present invention also provides a kind of manufacture method of test component, comprising:
Semiconductor substrate is provided;
Adopting TEOS is reaction source forms silica material in described Semiconductor substrate dielectric layer, in described dielectric layer, form a plurality of through holes, in the through hole of part number, fill the first material and form metal plug, in the residue through hole, fill the second material and form pseudo-contact hole, described the second material comprises tungsten, and the ratio of the upper surface area of described pseudo-contact hole and the upper surface area of whole dielectric layer is more than or equal to 20%;
Form electric connection line at described dielectric layer, the material of described electric connection line comprises copper, aluminium or albronze.
Alternatively, the manufacture method of described test component also comprises: before forming described dielectric layer, form oxide layer in described Semiconductor substrate, the material of described oxide layer is silica; After forming oxide layer and before forming described dielectric layer, form insulating barrier in the described oxide layer of part at least; Form dielectric layer with described insulating barrier on described oxide layer, described pseudo-contact hole is positioned on the described insulating barrier.
Alternatively, forming described pseudo-contact hole comprises: the side at described pseudo-contact hole forms isolation side walls.
For addressing the above problem, the present invention also provides a kind of manufacture method of semiconductor device, and described semiconductor device comprises a plurality of chips and the Cutting Road between described chip, adopts above-mentioned manufacture method to form described test component in described Cutting Road.
Alternatively, described chip comprises metal plug; Form simultaneously the metal plug of described chip and the metal plug of described test component.
Alternatively, described chip comprises grid structure and the isolation side walls that is positioned at the grid structure side; The side of described pseudo-contact hole comprises isolation side walls; Form simultaneously the isolation side walls of described pseudo-contact hole and the isolation side walls of described chip.
Compared with prior art, technical solution of the present invention has the following advantages:
1) the present invention has increased pseudo-contact hole in dielectric layer, the material of described pseudo-contact hole comprises tungsten, because tungsten and copper, the bonding force of aluminium or copper aluminium is relatively good, the ratio of the upper surface area that guarantees described pseudo-contact hole and the upper surface area of whole dielectric layer more than or equal to 20% prerequisite under, can guarantee that electric connection line and dielectric layer are pasted together very securely, thereby when cutting is arranged in the test component of Cutting Road, electric connection line can not come off everywhere, more can not be splashed in the chip, thereby guaranteed the stability of semiconductor device, improved the rate of finished products of chip.
In addition, comprise metal plug in the described dielectric layer, by in dielectric layer, forming simultaneously a plurality of through holes, make the contact hole of part number become described metal plug, remainder purpose contact hole becomes described pseudo-contact hole, thereby has saved process, has reduced production cost.
2) in the possibility, between described Semiconductor substrate and described dielectric layer, comprise oxide layer, when the material of described oxide layer is silica, described test component also comprises the insulating barrier between described oxide layer and described dielectric layer, stop-layer when described insulating barrier not only can be used as the etching dielectric layer, but also can guarantee that the electrical property of test component does not change because of the increase of pseudo-contact hole.
3) in the possibility, described chip comprises metal plug and isolation side walls, described pseudo-contact hole comprises isolation side walls, the metal plug of described chip and the metal plug of described test component can form simultaneously, the isolation side walls of described chip and the isolation side walls of described pseudo-contact hole also can form simultaneously, thereby can further save processing step, reduce production costs.
Description of drawings
Fig. 1 is the structural representation of a kind of test component in the prior art;
Fig. 2 is the structural representation of a kind of test component in the embodiment of the invention;
Fig. 3 is the structural representation of pseudo-contact hole among Fig. 2;
Fig. 4 is the structural representation of another kind of test component in the prior art;
Fig. 5 is the structural representation of another test component in the embodiment of the invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Set forth in the following description a lot of details so that fully understand the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not been subjected to the restriction of following public specific embodiment.
Just as described in the background section, comprise one or more test components in the channel region of prior art wafer, after along channel region chip being divided, the electrical property of chip with divide before compare great changes occured, thereby cause chip to use, final so that whole wafer loss.
The inventor finds that through research the reason of its generation is: the material of the electric connection line of test component upper space comprises copper, aluminium or albronze, the material of the dielectric layer of electric connection line below is that employing TEOS is the silica that reaction source forms, because the bonding force of described silica and copper, aluminium or albronze is smaller, so cause the adhesiveness of dielectric layer and electric connection line relatively poor.When along channel region chip being divided, can cut described test component inevitably, because the adhesiveness of dielectric layer and electric connection line is relatively poor, therefore generating unit is divided come off (peeling) to electric connection line to I haven't seen you for ages, the electric connection line that comes off can enter in the adjacent chip in sputter, so that the parts that should insulate in this chip Central Plains have been realized electrical connection, thereby greatly changed the electrical property of chip.Because can't realize the detection to single separate chip, thereby will cause scrapping of all chips on this wafer.In addition, also can find by the wafer that amplifies after cutting: the electric connection line of the subregion upper surface that the test component that is cut should stay all comes off, thereby has further proved the correctness of above-mentioned research.
For the problems referred to above, the invention provides a kind of test component and preparation method thereof, semiconductor device and preparation method thereof, improve the bonding force of dielectric layer and electric connection line by the mode that in dielectric layer, increases pseudo-contact hole, prevent coming off on the impact of chip electrical property of electric connection line in the cutting process, finally can obtain qualified separate chip.
Be elaborated below in conjunction with accompanying drawing.
With reference to shown in Figure 2, present embodiment one embodiment provide a kind of test component, comprising:
Be positioned at the oxide layer 120 on the described Semiconductor substrate 110, described oxide layer 120 is as channel layer;
Be positioned at the insulating barrier on the described oxide layer 120, described insulating barrier comprises first area 130 and second area 140;
Be positioned at the dielectric layer 150 on the described insulating barrier, the material of described dielectric layer 150 is the silica that reaction source forms for adopting TEOS, comprise metal plug (not shown) and pseudo-contact hole 160 in the described dielectric layer 150, described second area 140 is corresponding with all pseudo-contact holes 160 at least;
Be positioned at the electric connection line 180 on the described dielectric layer 150.
Compare with test component shown in Figure 1 in the prior art, present embodiment has increased pseudo-contact hole 160 in dielectric layer 150, to improve the bonding force between dielectric layer 150 and the electric connection layer 180; And between dielectric layer 150 and oxide layer 120, increased insulating barrier, do not changed with the electrical property that guarantees test component.
Described Semiconductor substrate 110 can be Silicon Wafer, can be other semi-conducting materials also, and it is known for those skilled in the art, does not repeat them here.
The material of described oxide layer 120 can be silica, and described silica can adopt physical vapor deposition (PVD) method, chemical vapour deposition (CVD) (CVD) method or boiler tube method to form.Particularly, the thickness range of described oxide layer 120 can be but be not limited to 200 dusts ~ 800 dusts.
The material of first area 130 can be that employing TEOS is the silica that reaction source forms in the described insulating barrier, and the material of second area 140 can be polysilicon or silicon nitride.Particularly, the thickness range of described insulating barrier can be but be not limited to 4000 dusts ~ 5000 dusts.
Need to prove that in other embodiments of the invention, other any insulating material can also be adopted in described first area 130, described second area 140 can adopt any insulating material outside the silica.
Metal plug in the described dielectric layer 150 can arrange according to the electrical connection needs of reality, and the material of described metal plug can be copper, aluminium or albronze, and it is same as the prior art, does not repeat them here.
Preferably, the size of described metal plug and described pseudo-contact hole 160 measure-alike, thereby can be simultaneously in dielectric layer 150 the corresponding through hole of formation and metal plug and pseudo-contact hole 160, saved processing step, reduced cost.Need to prove that in other embodiments of the invention, the size of the size of described metal plug and described pseudo-contact hole 160 also can be different, it does not limit protection scope of the present invention.
The effect of described pseudo-contact hole 160 is to improve the bonding force between dielectric layer 150 and the electric connection line 180.Because the material of electric connection line 180 comprises copper, aluminium or albronze more, and tungsten and copper, aluminium or copper aluminium have larger bonding force, therefore the material of pseudo-contact hole 160 is mainly tungsten.
In order to guarantee to cut in the process of described test component, electric connection line 180 can not come off, the upper surface area of described pseudo-contact hole 160 need to be more than or equal to 20% with the ratio of the upper surface area of whole dielectric layer 150, as: 20%, 30%, 50%, 80% or 95% etc., otherwise can't reach the purpose that prevents that electric connection line 180 from coming off.Find by follow-up detection, when the upper surface area of described pseudo-contact hole 160 satisfies above-mentioned condition, all exist by the electric connection line that amplifies the subregion upper surface that test component that wafer after the cutting can find to be cut should stay, namely do not come off; And the electrical property of separate chip does not change yet, and can realize well corresponding function.Need to prove that the upper surface area of described whole dielectric layer 150 comprises the upper surface area of described pseudo-contact hole 160 and the upper surface area of described metal plug simultaneously.
In conjunction with referring to figs. 2 and 3 shown in, the side of described pseudo-contact hole 160 can comprise isolation side walls 170, be used for to realize the isolation to described pseudo-contact hole 160.Particularly, described isolation side walls 170 can comprise the first silicon oxide layer 171, silicon nitride layer 172 and second silicon oxide layer 173 of stacked setting.Need to prove that in other embodiments of the invention, described isolation side walls 170 can be one deck or two-layer only, does not repeat them here.
Shown in Figure 3 in conjunction with reference, described pseudo-contact hole 160 can comprise titanium layer 161, titanium nitride layer 162 and the tungsten layer 163 of stacked setting.Wherein, described titanium layer 161 can prevent that tungsten layer 163 from blasting, and described titanium nitride layer 162 can improve the bonding force of tungsten layer 163 and titanium layer 161, and described tungsten layer 163 can improve the bonding force of dielectric layer 150 and electric connection line 180.Need to prove that described titanium layer 161 and titanium nitride layer 162 can also replace with the other materials with identical function, it does not limit protection scope of the present invention.
Particularly, the thickness of described the first silicon oxide layer 171 can be but be not limited to 100 dusts ~ 200 dusts, the thickness of silicon nitride layer 172 can be but be not limited to 100 dusts ~ 300 dusts, the thickness of the second silicon oxide layer 173 can be but be not limited to 100 dusts ~ 3000 dusts, the thickness of titanium layer 161 can be but be not limited to 350 dusts ~ 650 dusts that the thickness of titanium nitride layer 162 can be but be not limited to 600 dusts ~ 1000 dusts.
Improved bonding force between dielectric layer 150 and the electric connection line 180 by pseudo-contact hole 160 in the present embodiment, thereby when this test component of cutting, electric connection line 180 can not come off, can not affect the electrical property of other devices accordingly yet.In addition, because the barrier effect of insulating barrier can guarantee that also the pseudo-contact hole 160 that increases can not affect the electrical property of test component.
Fig. 4 shows the structure of another kind of test component in the prior art, the difference of itself and test component shown in Figure 1 is: between dielectric layer 30 and oxide layer 20 functional layer is set also, described functional layer comprises first area 50 and second area 60, wherein the material of first area 50 is the silica that reaction source forms for adopting TEOS, and the material of second area 60 is polysilicon.Because silica and polysilicon are all non-conductive, so this functional layer insulation.Because this moment, the material of dielectric layer 30 and electric connection line 40 was all identical with Fig. 1 with annexation, the problem that the electric connection line 40 that therefore exists in the cutting comes off still exists.
For test component shown in Figure 4, the test component that another embodiment of present embodiment provides comprises as shown in Figure 5:
Be positioned at the oxide layer 120 on the described Semiconductor substrate 110;
Be positioned at the functional layer on the described oxide layer 120, described functional layer comprises first area 50 and second area 60, and the material of described first area 50 is the silica that reaction source forms for adopting TEOS, and the material of second area 60 is polysilicon;
Be positioned at the dielectric layer 150 on the described insulating barrier, the material of described dielectric layer 150 is the silica that reaction source forms for adopting TEOS, comprise metal plug (not shown) and pseudo-contact hole 160 in the described dielectric layer 150, described pseudo-contact hole 160 is positioned on the described second area 60, and the ratio of the upper surface area of described pseudo-contact hole 160 and the upper surface area of whole dielectric layer 150 is more than or equal to 20%, and the side of described pseudo-contact hole 160 comprises isolation side walls 170;
Be positioned at the electric connection line 180 on the described dielectric layer 150.
Owing to comprised insulating barrier between oxide layer 20 and the dielectric layer 30 in the test component shown in Figure 4, and the material of the second area of insulating barrier is different from the material of dielectric layer 30, therefore when the zone of the second area 60 of insulating barrier enough greatly the time, the upper surface area that can guarantee the pseudo-contact hole 160 on the second area 60 among Fig. 5 and the ratio of the upper surface area of whole dielectric layer 150 are more than or equal to 20% the time, and test component shown in Figure 5 is compared with Fig. 4 and then be need not the insulating barriers that add more.
Present embodiment can pass through the bonding force that pseudo-contact hole 160 improves between dielectric layers 150 and the electric connection line 180 equally, thereby when this test component of cutting, electric connection line 180 can not come off, and can not affect the electrical property of other devices accordingly yet.In addition, because the barrier effect of second area 60 can guarantee that also the pseudo-contact hole 160 that increases can not affect the electrical property of test component.
In other embodiments of the invention, when the ratio of the upper surface area of the second area 60 of insulating barrier among Fig. 4 and the upper surface area of whole dielectric layer less than 20% the time, then still need to be in Fig. 5 a layer insulating be set between functional layer and the dielectric layer 150 more, the insulating barrier that comprises first area 130 and second area 140 among this newly-installed insulating barrier and Fig. 2 is similar, does not repeat them here.
Need to prove that in other embodiments of the invention, described test component can also adopt other concrete structures, it does not limit protection scope of the present invention.
Correspondingly, present embodiment also provides a kind of manufacture method of test component, comprising:
Step S1 provides Semiconductor substrate;
Step S2, adopting TEOS is reaction source forms silica material in described Semiconductor substrate dielectric layer, in described dielectric layer, form a plurality of through holes, in the through hole of part number, fill the first material and form metal plug, in the residue through hole, fill the second material and form pseudo-contact hole, described the second material comprises tungsten, and the ratio of the upper surface area of described pseudo-contact hole and the upper surface area of whole dielectric layer is more than or equal to 20%;
Step S3 forms electric connection line at described dielectric layer.
Wherein, the material of described electric connection line can comprise copper, aluminium or albronze; Described the first material can comprise copper, aluminium or albronze; Described the second material can comprise successively: titanium, titanium nitride and tungsten.
In described dielectric layer, form the step of through hole and in through hole, fill the first material all same as the prior art with the step that forms metal plug, and filling the second material is similar with the step that forms metal plug with the step that forms pseudo-contact hole in through hole, all repeats no more at this.
Forming described pseudo-contact hole can also comprise: form isolation side walls in the side of described pseudo-contact hole, the step in the side of grid structure formation isolation side walls in the step that forms described isolation side walls and the prior art is identical.
Preferably, before forming described dielectric layer, can adopt PVD, CVD or boiler tube method to form oxide layer in described Semiconductor substrate, the material of described oxide layer be silica; After forming oxide layer and before forming described dielectric layer, can adopt the technique that deposits first again etching to form at least the insulating barrier of the materials such as polysilicon or silicon nitride in the described oxide layer of part; Thereby form dielectric layer with described insulating barrier on described oxide layer, described pseudo-contact hole is positioned on the described insulating barrier.
The test component that adopts said method to make specifically can with reference to figure 2 and corresponding explanation, not repeat them here.
Correspondingly, present embodiment also provides a kind of semiconductor device, comprises a plurality of chips and the Cutting Road between described chip, comprises one or more in the above-mentioned test component in the described Cutting Road.
Described chip can comprise metal plug and grid structure, and the side of described grid structure can also comprise isolation side walls, and it is known for those skilled in the art, does not repeat them here.Particularly, described chip can be the planar power MOS pipe, also can be other devices.
Preferably, the size of the metal plug of described chip, material are can be respectively corresponding identical with size, the material of the metal plug of described test component; The size of the size of the metal plug of described chip and the pseudo-contact hole of described test component can be identical, thereby can form simultaneously the metal plug of described chip and the metal plug of described test component, to save process, reduces production costs.
Preferably, size and the material of the isolation side walls of described chip and the isolation side walls of described pseudo-contact hole can be all corresponding identical, thereby can form simultaneously the isolation side walls of described chip and the isolation side walls of described pseudo-contact hole, can further save process, reduce production costs.
Because the bonding force of test component dielectric layer and electric connection line is relatively good, therefore along Cutting Road cutting test component the time, does not have electric connection line and come off, thereby guaranteed the electric performance stablity of separate chip.
Correspondingly, present embodiment also provides a kind of manufacture method of semiconductor device, described semiconductor device comprises a plurality of chips and the Cutting Road between described chip, adopts the manufacture method of above-mentioned test component to form described test component in described Cutting Road.
Preferably, when described chip comprises metal plug, can form simultaneously the metal plug of described chip and the metal plug of described test component, thereby can save process, reduce production costs.
Preferably, when described chip comprises grid structure and the isolation side walls that is positioned at the grid structure side, when the side of described pseudo-contact hole comprises isolation side walls, can form simultaneously the isolation side walls of described pseudo-contact hole and the isolation side walls of described chip, thereby can further save process, reduce production costs.
In addition, when described chip comprised polysilicon gate, the first area of the insulating barrier between dielectric layer and oxide layer can form simultaneously with described polysilicon gate, thereby can further save process, reduced production costs.
Under the adeciduate prerequisite of electric connection line of present embodiment in guaranteeing test component, adopt with chip in identical process, thereby method is simple and easily realization, production cost is lower.
Although the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with the claim limited range.
Claims (16)
1. a test component is characterized in that, comprising:
Semiconductor substrate;
Be positioned at the dielectric layer on the described Semiconductor substrate, the material of described dielectric layer is the silica that reaction source forms for adopting tetraethoxysilane, comprise metal plug and pseudo-contact hole in the described dielectric layer, the material of described pseudo-contact hole comprises tungsten, and the ratio of the upper surface area of described pseudo-contact hole and the upper surface area of whole dielectric layer is more than or equal to 20%;
Be positioned at the electric connection line on the described dielectric layer, the material of described electric connection line comprises copper, aluminium or albronze.
2. test component as claimed in claim 1 is characterized in that, comprises oxide layer between described Semiconductor substrate and the described dielectric layer, and the material of described oxide layer is silica; Described test component also comprises: the insulating barrier between described oxide layer and described dielectric layer.
3. test component as claimed in claim 2, it is characterized in that, described insulating barrier comprises first area and second area, the material of described first area is the silica that reaction source forms for adopting tetraethoxysilane, described second area is corresponding with all pseudo-contact holes at least, and the material of described second area is polysilicon or silicon nitride.
4. test component as claimed in claim 1 is characterized in that, the size of described metal plug and described pseudo-contact hole measure-alike.
5. test component as claimed in claim 1 is characterized in that, the side of described pseudo-contact hole also comprises isolation side walls.
6. test component as claimed in claim 5 is characterized in that, described isolation side walls comprises the first silicon oxide layer, silicon nitride layer and second silicon oxide layer of stacked setting.
7. test component as claimed in claim 1 is characterized in that, described pseudo-contact hole comprises titanium layer, titanium nitride layer and the tungsten layer of stacked setting.
8. a semiconductor device is characterized in that, comprises a plurality of chips and the Cutting Road between described chip, comprises in the described Cutting Road such as each described test component in the claim 1 to 7.
9. semiconductor device as claimed in claim 8 is characterized in that, described chip comprises metal plug; The size of the metal plug of described chip, material respectively size, the material with the metal plug of described test component are corresponding identical; The size of the metal plug of described chip and the pseudo-contact hole of described test component measure-alike.
10. semiconductor device as claimed in claim 8 is characterized in that, described chip comprises grid structure and is positioned at the isolation side walls of grid structure side; The side of described pseudo-contact hole comprises isolation side walls; The isolation side walls of described chip is all corresponding identical with size and the material of the isolation side walls of described pseudo-contact hole.
11. the manufacture method of a test component is characterized in that, comprising:
Semiconductor substrate is provided;
Adopting tetraethoxysilane is reaction source forms silica material in described Semiconductor substrate dielectric layer, in described dielectric layer, form a plurality of through holes, in the through hole of part number, fill the first material and form metal plug, in the residue through hole, fill the second material and form pseudo-contact hole, described the second material comprises tungsten, and the ratio of the upper surface area of described pseudo-contact hole and the upper surface area of whole dielectric layer is more than or equal to 20%;
Form electric connection line at described dielectric layer, the material of described electric connection line comprises copper, aluminium or albronze.
12. the manufacture method of test component as claimed in claim 11 is characterized in that, also comprises:
Before forming described dielectric layer, form oxide layer in described Semiconductor substrate, the material of described oxide layer is silica;
After forming described oxide layer and before forming described dielectric layer, form insulating barrier in the described oxide layer of part at least;
Form dielectric layer with described insulating barrier on described oxide layer, described pseudo-contact hole is positioned on the described insulating barrier.
13. the manufacture method of test component as claimed in claim 12 is characterized in that, forms described pseudo-contact hole and comprises: the side at described pseudo-contact hole forms isolation side walls.
14. the manufacture method of a semiconductor device, described semiconductor device comprises a plurality of chips and the Cutting Road between described chip, it is characterized in that, adopt as each described manufacture method in the claim 11 to 13 as described in form in the Cutting Road as described in test component.
15. the manufacture method of semiconductor device as claimed in claim 14 is characterized in that, described chip comprises metal plug; Form simultaneously the metal plug of described chip and the metal plug of described test component.
16. the manufacture method of semiconductor device as claimed in claim 14 is characterized in that, described chip comprises grid structure and is positioned at the isolation side walls of grid structure side; The side of described pseudo-contact hole comprises isolation side walls; Form simultaneously the isolation side walls of described pseudo-contact hole and the isolation side walls of described chip.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11297882A (en) * | 1998-04-13 | 1999-10-29 | Hitachi Ltd | Semiconductor device, manufacture thereof, electronic device and manufacture thereof |
| CN1900725A (en) * | 1998-12-02 | 2007-01-24 | 佛姆法克特股份有限公司 | Lithographic contact elements |
| CN101211807A (en) * | 2006-12-28 | 2008-07-02 | 株式会社瑞萨科技 | Method of manufacturing semiconductor integrated circuit device and method of manufacturing thin film probe sheet for using the same |
| US20100055842A1 (en) * | 2008-08-28 | 2010-03-04 | Yuki Sugo | Thermosetting die-bonding film |
| US20120013348A1 (en) * | 2010-07-16 | 2012-01-19 | Chroma Ate Inc. | Test fixture for testing semiconductor die with its loading member maintained flat throughout the test |
-
2012
- 2012-11-20 CN CN201210472771.1A patent/CN102931172B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11297882A (en) * | 1998-04-13 | 1999-10-29 | Hitachi Ltd | Semiconductor device, manufacture thereof, electronic device and manufacture thereof |
| CN1900725A (en) * | 1998-12-02 | 2007-01-24 | 佛姆法克特股份有限公司 | Lithographic contact elements |
| CN101211807A (en) * | 2006-12-28 | 2008-07-02 | 株式会社瑞萨科技 | Method of manufacturing semiconductor integrated circuit device and method of manufacturing thin film probe sheet for using the same |
| US20100055842A1 (en) * | 2008-08-28 | 2010-03-04 | Yuki Sugo | Thermosetting die-bonding film |
| US20120013348A1 (en) * | 2010-07-16 | 2012-01-19 | Chroma Ate Inc. | Test fixture for testing semiconductor die with its loading member maintained flat throughout the test |
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