CN102929818B - The transmitting message data method of PCIe interface, bridge module, read module and system - Google Patents
The transmitting message data method of PCIe interface, bridge module, read module and system Download PDFInfo
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- CN102929818B CN102929818B CN201210407425.5A CN201210407425A CN102929818B CN 102929818 B CN102929818 B CN 102929818B CN 201210407425 A CN201210407425 A CN 201210407425A CN 102929818 B CN102929818 B CN 102929818B
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Abstract
This application discloses the transmitting message data method of PCIe interface, bridge module, read module and system, wherein method comprises: be that each PCIe interface arranges corresponding pointer space in CPU internal memory at bridge module end; Respectively by each PCIe interface, by pointer space corresponding with each PCIe interface for write pointer write.In this application, owing to only this message data being write this CPU memory cache block by PCIe interface; And, by PCIe interface by after in the receiving queue in this bag descriptor write CPU, these two steps complete, the pointer of each pointer space just can be identical, so by when the pointer of each pointer space is identical again reading pointer to obtain the mode of message data, can effectively avoid when bridge module supports the transmission of multichannel PCIe interface data, the message data read error that the write of the pointer that the time delay difference due to different PCIe interface causes causes early than above-mentioned two steps.
Description
Technical field
The present invention relates to computer realm, more particularly, relate to the transmitting message data method of PCIe interface, bridge module, read module and system.
Background technology
PCIe interface is that X86CPU and other devices carry out interconnected important interface, can complete the conversion as the high-speed interfaces such as XAUI interface and PCIe interface by bridge module.
As shown in Figure 1, undertaken by bridge module in the transfer process of XAUI interface and PCIe interface, after bridge module receives the message data of XAUI interface, needing to perform following 3 operations:
S11, distribute to this message data CPU memory cache block, by PCIe interface, this message data is write this CPU memory cache block;
S12, structure comprise the bag descriptor of the first address of this CPU memory cache block, and by PCIe interface by the receiving queue in this bag descriptor write CPU;
S13, by the pointer space of the write pointer of described receiving queue by specifying in PCIe interface write CPU internal memory.
In addition, when CPU obtains message data, obtain write pointer at described assigned address, the bag descriptor then read in CPU receiving queue according to write pointer can obtain the first address of message data in CPU memory cache block, thus can read required message data.
PCIe interface bridge module generally can adopt FPGA device to realize, assuming that the maximum effective bandwidth that the PCIe interface of FPGA device used can provide is Gen1*4 pattern, namely, 2.5G*4*0.8=8Gbps, when needing bridge module to provide larger bandwidth to connect high bandwidth device, such as, when being connected with XAUI interface, because the effective bandwidth that can provide is less than the bandwidth required for, in order to improve the bandwidth of PCIe interface, prior art is generally by selecting high-end FPGA device to realize, the FPGA device of PCIeGen1*8 or PCIeGen2*4 can be supported as selected, but the mode shortcoming selecting high-end FPGA device to realize the bandwidth improving PCIe interface is that cost is higher.
Summary of the invention
In view of this, this application provides the transmitting message data method of PCIe interface, bridge module, read module and system.
The application is achieved in that
In the one side of the application, provide a kind of multichannel PCIe interface transmitting message data method, it is characterized in that, comprising:
For each PCIe interface arranges corresponding pointer space in CPU internal memory;
The write pointer of receiving queue is write pointer space by PCIe interface, is specially:
Respectively by each PCIe interface, by pointer space corresponding with each PCIe interface for described write pointer write.
In the another aspect of the application, additionally provide a kind of multichannel PCIe interface transmitting message data method, it is characterized in that, comprising: judge that whether the write pointer in the pointer space that each PCIe interface is corresponding in CPU internal memory is identical;
If identical:
Then read described write pointer, read the bag descriptor in corresponding receiving queue according to described write pointer, obtain the first address of message data in CPU memory cache block according to described bag descriptor, and the message data needed for obtaining according to described first address;
Otherwise:
Suspend and read described write pointer.
In the another aspect of the application, additionally provide a kind of PCIe interface bridge module, it is characterized in that, comprising: multichannel PCIe interface;
Pointer space setting unit, for arranging corresponding pointer space in CPU internal memory for each PCIe interface;
Pointer space writing unit, for the write pointer of receiving queue is write pointer space by PCIe interface, comprising:
Respectively by each PCIe interface, by pointer space corresponding with each PCIe interface for described write pointer write.
Preferably, in this application, described multichannel comprises two-way PCIe interface.
In the another aspect of the application, additionally provide a kind of multichannel PCIe interface transmitting message data read module, it is characterized in that, comprising:
Whether pointer judging unit is identical for judging the write pointer in the pointer space that each PCIe interface is corresponding in CPU internal memory;
Pointer reads control module, for
When the write pointer in each pointer space is identical, read described write pointer, obtain the first address of message data in CPU memory cache block according to described write pointer bag descriptor, and the message data needed for obtaining according to described first address;
When the write pointer in each pointer space is not identical, suspends and read described write pointer.
Preferably, in this application, described multiple pointer space comprises two pointer space.
Preferably, in this application, described transmitting message data read module is located in CPU.
In the another aspect of the application, additionally provide a kind of PCIe interface transmitting message data transmission system, it is characterized in that, comprising: bridge module and transmitting message data read module;
Described bridge module comprises:
Multichannel PCIe interface;
Pointer space setting unit, for arranging corresponding pointer space in CPU internal memory for each PCIe interface;
Pointer space writing unit, for the write pointer of receiving queue is write pointer space by PCIe interface, comprising:
Respectively by each PCIe interface, by pointer space corresponding with each PCIe interface for described write pointer write;
Described transmitting message data read module comprises:
Pointer judging unit, for when obtaining message data, judges that whether the write pointer in each pointer space is identical;
Pointer reads control module, for
When the write pointer in each pointer space is identical, read described write pointer, read the bag descriptor in corresponding receiving queue according to described write pointer, obtain the first address of message data in CPU memory cache block according to described bag descriptor, and the message data needed for obtaining according to described first address;
When the write pointer in each pointer space is not identical, suspends and read described write pointer.
Preferably, in this application, described transmitting message data read module is located in CPU.
As can be seen from above-mentioned technical scheme, in this application, be provided with multiple pointer space, the pointer corresponding to same message data is stored by the transmission of different PCIe interface, due to only distributing to this message data CPU memory cache block, by PCIe interface, this message data is write this CPU memory cache block; And, structure comprises the bag descriptor of the first address of this CPU memory cache block, and by PCIe interface by after in the receiving queue in this bag descriptor write CPU, these two steps complete, the pointer of each pointer space just can be identical, so by when the pointer of each pointer space is identical again reading pointer to obtain the mode of message data, can effectively avoid when bridge module supports the transmission of multichannel PCIe interface data, the message data read error that the write of the pointer that the time delay difference due to different PCIe interface causes causes early than above-mentioned two steps.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the treatment scheme schematic diagram in prior art after bridge module reception message data;
Fig. 2 is the treatment scheme schematic diagram in the application after bridge module reception message data;
Fig. 3 is the schematic flow sheet reading message data in the application at CPU end;
Fig. 4 is the structural representation of PCIe interface bridge module in the application;
Fig. 5 is the structural representation of multichannel PCIe interface transmitting message data read module in the application;
Fig. 6 is the structural representation of PCIe interface transmitting message data transmission system in the application.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
As shown in Figure 2, in order to avoid message data read error, in an embodiment of the application, provide a kind of multichannel PCIe interface transmitting message data method, comprising: at bridge module end:
S21, corresponding pointer space is set in CPU internal memory for each PCIe interface;
S22, the write pointer of receiving queue is write pointer space by PCIe interface, be specially, respectively by each PCIe interface, by pointer space corresponding with each PCIe interface for write pointer write.
In the prior art, multiple PCIe interface why cannot be realized to bundle, because message data is being write in the process of CPU, because each step of message data write can by different PCIe interface executed in parallel to write in CPU, so likely there will be following situation: the step of message data write buffer memory completing to lag behind write pointer is write completing of pointer space step maybe by the bag descriptor of this message data write receiving queue step, because the bag descriptor of this message data write receiving queue step does not maybe also complete by the step of now message data write buffer memory, if so now read data according to the write pointer in pointer space, data read errors will be there is.
In order to solve the message data read error caused by above reason, in the present embodiment, for each PCIe interface arranges corresponding pointer space in CPU internal memory, concrete, to bundle two PCIe interface, just need to be provided with two pointer space, for storing write pointer, after each PCIe interface is provided with independent pointer space, also need when write pointer is write pointer space by PCIe interface, respectively by each PCIe interface, by pointer space corresponding with each PCIe interface for write pointer write.That is, when the bag descriptor of this message data is maybe write receiving queue step by the step performing message data write buffer memory, by two PCIe interface parallel processings, when write pointer is write pointer space step by execution, then two PCIe interface are needed respectively write pointer to be write each self-corresponding pointer space of PCIe interface.
In order to avoid what cause due to the time delay difference of two PCIe interface, the step of message data write buffer memory, completing maybe by the bag descriptor of this message data write receiving queue step, lag behind and write pointer is write completing of pointer space step, repeated so write pointer to be write pointer space step by each PCIe interface, when the write pointer homogeneous phase of each pointer space while, then represent that the write of this write pointer is later than message data write buffer memory and the bag descriptor of this message data is write receiving queue, thus ensure this write pointer, corresponding with the bag descriptor of this message data in the write message data of buffer memory and receiving queue.And then also just avoid the read error of message data.
Due in the present embodiment, avoid the read error of message data when bundling multiple PCIe interface.To achieve the packet data transmission of the PCIe interface of high bandwidth due to the embodiment of the present application in the mode bundling multiple PCIe interface, and then effectively save equipment cost.In addition, according to the technical scheme in the present embodiment, the PCIe interface more than two can be bundled, thus greatly can improve the bandwidth of PCIe interface, thus can also realize also being beyond one's reach packet data transmission bandwidth by high side device.
As shown in Figure 3, in the another aspect of the application, additionally provide another kind of multichannel PCIe interface transmitting message data method, comprising:
S31, CPU end judge each PCIe interface in CPU internal memory correspondence pointer space in write pointer whether identical;
If S32 is identical, read described write pointer, obtain the first address of message data in CPU memory cache block according to described pointer bag descriptor, and the message data needed for obtaining according to described first address; Otherwise suspend and read described write pointer.
In the present embodiment, with on the basis of the embodiment corresponding to Fig. 2, CPU holds corresponding multichannel PCIe interface transmitting message data method, owing to being equipped with pointer space for each PCIe interface in CPU, and only have the write pointer in each pointer space identical, just represent that the write of this write pointer is later than message data write buffer memory and the bag descriptor of this message data is write receiving queue, thus ensure this write pointer, be corresponding with the bag descriptor of this message data in the write message data of buffer memory and receiving queue.For this reason, in the present embodiment, when obtaining message data, first to judge that whether the pointer in each pointer space is identical, follow-up read action is just performed when only having the write pointer in each pointer space identical, that is, the first address of message data in CPU memory cache block is obtained according to pointer bag descriptor, and the message data needed for obtaining according to first address.
If the write pointer in each pointer space is different, then represent in the PCIe interface likely had and not yet complete message data write buffer memory maybe by the step of the bag descriptor of this message data write receiving queue, so the write pointer now in reading pointer space likely will cause the read error of message data, thus in this case, the reading suspending message data is needed.Until when the write pointer in each pointer space is identical, then perform the reading of message data.
As shown in Figure 4, in the another aspect of the application, additionally provide a kind of PCIe interface bridge module 1, comprising: multichannel PCIe interface;
Pointer space setting unit 3, for arranging corresponding pointer space 4 in CPU2 internal memory for each PCIe interface;
Pointer space writing unit 5, for the write pointer of receiving queue is write pointer space by PCIe interface, specifically comprises: respectively by each PCIe interface, by pointer space 4 corresponding with each PCIe interface for described write pointer write.
The present embodiment is the device embodiment corresponding with multichannel PCIe interface transmitting message data embodiment of the method illustrated in fig. 2, in the present embodiment, PCIe interface bridge module can bundle the PCIe interface of multichannel, during in order to solve multichannel PCIe interface parallel transmission message data, likely can write buffer memory because of message data, completing to lag behind write pointer write completing of pointer space maybe by the bag descriptor of this message data write receiving queue, due to maybe the bag descriptor of this message data write receiving queue also not being completed of now message data write buffer memory, if so now read data according to the write pointer in pointer space, there will be the problem of data read errors, by pointer space setting unit 3, for each PCIe interface arranges corresponding pointer space in the internal memory of CPU2, like this, in time write pointer being write specify in CPU2 internal memory pointer space 4, by pointer space writing unit 5, respectively by each PCIe interface, by pointer space 4 corresponding with each PCIe interface for described write pointer write.
Write pointer is write pointer space 4 by each PCIe interface by pointer space writing unit 5, when the write pointer homogeneous phase of each pointer space 4 while, then represent that the write of this write pointer is later than message data write buffer memory and the bag descriptor of this message data is write receiving queue, thus ensure this write pointer, be corresponding with the bag descriptor of this message data in the write message data of buffer memory and receiving queue.And then also just avoid the read error of message data.
Due in the present embodiment, avoid the read error of message data when bundling multiple PCIe interface.To achieve the packet data transmission of the PCIe interface of high bandwidth due to the embodiment of the present application in the mode bundling multiple PCIe interface, and then effectively save equipment cost.In addition, according to the technical scheme in the present embodiment, the PCIe interface more than two can be bundled, thus greatly can improve the bandwidth of PCIe interface, thus can also realize also being beyond one's reach packet data transmission bandwidth by high side device.
As shown in Figure 5, in the another aspect of the application, additionally provide a kind of multichannel PCIe interface transmitting message data read module 21, comprising: pointer judging unit 22, whether identical for judging the write pointer in the pointer space 4 that each PCIe interface is corresponding in CPU internal memory; Pointer reads control module 23, for when write pointer in each pointer space 4, read described write pointer, obtain the first address of message data in CPU memory cache block according to described write pointer bag descriptor, and the message data needed for obtaining according to described first address; When the write pointer in each pointer space 4 is not identical, suspends and read described write pointer.
PCIe interface bridge module in embodiment illustrated in fig. 4 complete message data the storage in CPU, construct the first address of this CPU memory cache block bag descriptor and by PCIe interface by the receiving queue in this bag descriptor write CPU and by the write pointer of described receiving queue by after the pointer space of specifying in PCIe interface write CPU internal memory, also need to read accordingly message data, so that the subsequent applications of CPU.
At the present embodiment, multichannel PCIe interface transmitting message data read module 21 generally can be arranged in CPU; Owing to being equipped with pointer space 4 for each PCIe interface in CPU, and only have the write pointer in each pointer space identical, just represent that the write of this write pointer is later than message data write buffer memory and by the bag descriptor of this message data write receiving queue, thus ensure that this write pointer is corresponding with the bag descriptor writing this message data in the message data of buffer memory and receiving queue.
For this reason, in the present embodiment, being provided with pointer judging unit 22 when obtaining message data, judging that whether the write pointer in each pointer space 4 is identical; Then, read control module 23 by pointer, perform follow-up read action when the write pointer in each pointer space 4 is identical, namely, the bag descriptor corresponding according to write pointer obtains the first address of message data in CPU memory cache block, and the message data needed for obtaining according to first address.When the pointer in each pointer space 4 is not identical, then suspends and read described pointer, to avoid the read error of message data.
If the write pointer of 4 is different in each pointer space, then represent in the PCIe interface likely had and not yet complete message data write buffer memory maybe by the step of the bag descriptor of this message data write receiving queue, so the write pointer now in reading pointer space 4 likely will cause the read error of message data, thus in this case, the reading suspending message data is needed.Until when the write pointer in each pointer space is identical, then perform the reading of message data.
As shown in Figure 6, in the another aspect of the application, additionally provide a kind of PCIe interface transmitting message data transmission system, bridge module and transmitting message data read module; Bridge module comprises: multichannel PCIe interface; Pointer space setting unit, for arranging corresponding pointer space in CPU internal memory for each PCIe interface; Pointer space writing unit, for the write pointer of receiving queue is write pointer space by PCIe interface, specifically comprises: respectively by each PCIe interface, by pointer space corresponding with each PCIe interface for described write pointer write;
Transmitting message data read module comprises: pointer judging unit, for when obtaining message data, judges that whether the pointer in each pointer space is identical;
Pointer reads control module, for when pointer in each pointer space, reads described pointer, obtains the first address of message data in CPU memory cache block according to described pointer bag descriptor, and the message data needed for described first address acquisition; When the pointer in each pointer space is not identical, suspends and read described pointer.
In the present embodiment, include PCIe interface bridge module illustrated in fig. 4, and, multichannel PCIe interface transmitting message data read module illustrated in fig. 5; Due to principle of work and the effect that can reach of the present embodiment, similar also coordinate multichannel PCIe interface transmitting message data read module illustrated in fig. 5 with PCIe interface bridge module illustrated in fig. 4 after, just repeat no more at this for this reason.
In this instructions, each embodiment adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar portion mutually see.
To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (7)
1. a multichannel PCIe interface transmitting message data method, is characterized in that, comprising: be that each PCIe interface arranges corresponding pointer space in CPU internal memory at bridge module end; And the write pointer of receiving queue is write pointer space by PCIe interface;
Wherein, the write pointer of receiving queue is write pointer space by PCIe interface, is specially:
Respectively by each PCIe interface, by pointer space corresponding with each PCIe interface for described write pointer write;
Judge that whether the write pointer in the pointer space that each PCIe interface is corresponding in CPU internal memory is identical at CPU end;
If identical:
Then read described write pointer, read the bag descriptor in corresponding receiving queue according to described write pointer, obtain the first address of message data in CPU memory cache block according to described bag descriptor, and the message data needed for obtaining according to described first address;
Otherwise:
Suspend and read described write pointer.
2. a multichannel PCIe interface transmitting message data method, is characterized in that, comprising: judge that whether the write pointer in the pointer space that each PCIe interface is corresponding in CPU internal memory is identical;
If identical:
Then read described write pointer, read the bag descriptor in corresponding receiving queue according to described write pointer, obtain the first address of message data in CPU memory cache block according to described bag descriptor, and the message data needed for obtaining according to described first address;
Otherwise:
Suspend and read described write pointer.
3. a multichannel PCIe interface transmitting message data read module, is characterized in that, comprising:
Whether pointer judging unit is identical for judging the write pointer in the pointer space that each PCIe interface is corresponding in CPU internal memory;
Pointer reads control module, for
When the write pointer in each pointer space is identical, read described write pointer, obtain the first address of message data in CPU memory cache block according to described write pointer bag descriptor, and the message data needed for obtaining according to described first address;
When the write pointer in each pointer space is not identical, suspends and read described write pointer.
4. transmitting message data read module according to claim 3, it is characterized in that, described pointer space comprises two pointer space.
5. transmitting message data read module according to claim 4, it is characterized in that, described transmitting message data read module is located in CPU.
6. a PCIe interface transmitting message data transmission system, is characterized in that, comprising: bridge module and transmitting message data read module;
Described bridge module comprises:
Multichannel PCIe interface;
Pointer space setting unit, for arranging corresponding pointer space in CPU internal memory for each PCIe interface;
Pointer space writing unit, for the write pointer of receiving queue is write pointer space by PCIe interface, comprising:
Respectively by each PCIe interface, by pointer space corresponding with each PCIe interface for described write pointer write;
Described transmitting message data read module comprises:
Pointer judging unit, for when obtaining message data, judges that whether the write pointer in each pointer space is identical;
Pointer reads control module, for
When the write pointer in each pointer space is identical, read described write pointer, read the bag descriptor in corresponding receiving queue according to described write pointer, obtain the first address of message data in CPU memory cache block according to described bag descriptor, and the message data needed for obtaining according to described first address;
When the write pointer in each pointer space is not identical, suspends and read described write pointer.
7. transmitting message data transmission system according to claim 6, it is characterized in that, described transmitting message data read module is located in CPU.
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| CN111026324B (en) | 2018-10-09 | 2021-11-19 | 华为技术有限公司 | Updating method and device of forwarding table entry |
| CN112486888A (en) * | 2020-12-11 | 2021-03-12 | 盛立金融软件开发（杭州）有限公司 | Market data transmission method, device, equipment and medium |
| CN115277407B (en) * | 2022-07-25 | 2024-01-23 | 北京天融信网络安全技术有限公司 | Internet access configuration processing method and device, electronic equipment and storage medium |
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| CN101071393A (en) * | 2006-05-11 | 2007-11-14 | 梁国恩 | Syncronous backing-up device for store device and method |
| CN101150527A (en) * | 2007-11-09 | 2008-03-26 | 杭州华三通信技术有限公司 | A PCIE data transmission method, system and device |
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| CN101071393A (en) * | 2006-05-11 | 2007-11-14 | 梁国恩 | Syncronous backing-up device for store device and method |
| CN101030168A (en) * | 2007-02-15 | 2007-09-05 | 华为技术有限公司 | Method and apparatus for realizing high-reliability chain list |
| CN101150527A (en) * | 2007-11-09 | 2008-03-26 | 杭州华三通信技术有限公司 | A PCIE data transmission method, system and device |
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