CN102916586B - Systems and methods for switching power converters - Google Patents

Abstract

The present invention discloses systems and methods for switching power converters. The system includes: a first comparator configured to receive a first input signal and a second input signal and generate a first comparison signal based at least on information associated with the first input signal and the second input signal; pulse width modulation generates a device configured to receive at least a first comparison signal and generate a modulation signal based on at least information associated with the first comparison signal; a driver component configured to receive the modulation signal and output a drive signal to a switch to regulate the current flowing through the power converter a primary current of the primary winding; and a voltage rate-of-change detection component configured to sample the feedback signal to generate a first sampled signal during a first modulation period and sample the feedback signal to generate a second sampled signal during a second modulation period.

Description

System and method for switching power converters

Technical field

The present invention relates to integrated circuit.More specifically, the invention provides the switching frequency and the peak current that in response to load, change regulates.As just example, the present invention has been applied to flyback power supply converter.But will recognize, the present invention has range of application widely.

Background technology

Usually, conventional power source transformation system is usually isolated input voltage in primary side and the output voltage in primary side with transformer.In order to adjust output voltage, the controller chip of some assembly such as TL431 and photoelectrical coupler can being used to from primary side to primary side sends feedback signal.In another method, the output voltage in primary side also can be reflected to primary side by magnetic coupling, therefore by some parameters in direct adjusting primary side, controls output voltage.

Fig. 1 is the simplification diagram that the classical inverse excitation power supply transformation system with primary side sensing and adjustment is shown.This power converting system 100 comprises the equivalent resistor 140, resistor 150 and 152 and rectifier diode 160 of armature winding 110, secondary winding 112, auxiliary winding 114, mains switch 120, current-sense resistor 130, output cable.For example, mains switch 120 is bipolar transistors.In another example, mains switch 120 is MOS transistor.

In order to adjust output voltage in preset range, usually need to extract the information relevant with output voltage and output loading.In power converting system 100, such information can be extracted by auxiliary winding 114.When mains switch 120 is switched on, energy is stored in secondary winding 112.Then, when mains switch 120 cut-off, institute's stored energy is released to lead-out terminal, and the voltage of auxiliary winding 114 output voltage shining upon like this in primary side as follows.

$V_{\mathrm{FB}}=\frac{R_2}{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HSA00000552366600031.png,HSA00000552366600051.png"\; state="\{\{state\}\}">R</figure-callout>}}_1+{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="HSA00000552366600141.png,HSA00000552366600161.png"\; state="\{\{state\}\}">R</figure-callout>}}_2}\&times;V_{\mathrm{aux}}=k\&times;n\&times;(V_o+V_F+I_o\&times;R_{\mathrm{eq}})$ (formula 1)

Wherein, V _fBthe voltage that represents node 154 places, and V _auxthe voltage that represents auxiliary winding 114.R ₁and R ₂the resistance value that represents respectively resistor 150 and 152.In addition, n represents the turn ratio between auxiliary winding 114 and secondary winding 112.Particularly, n equals the number of turn of auxiliary winding 114 divided by the number of turn of secondary winding 112.V _oand I _orepresent respectively output voltage and output current.In addition V, _fthe forward voltage that represents rectifier diode 160, and R _eqthe resistance value that represents equivalent resistor 140.In addition, k represents feedback factor, as follows:

$k=\frac{R_2}{R_1+R_2}$ (formula 2)

Fig. 2 is the simplification diagram that the traditional operation mechanism of flyback power supply transformation system 100 is shown.As shown in Figure 2, the controller chip of transformation system 100 is used sampling to keep mechanism.Demagnetization process in primary side almost completes and the electric current I of secondary winding 112 _secalmost during vanishing, the voltage V of auxiliary winding 114 _auxfor example at the some A place of Fig. 2, be sampled.This sample voltage value is held conventionally until next voltage sample is performed.By feedback loop, this sample voltage value can become and equal reference voltage V _ref.Therefore,

V _fR=V _ref(formula 3)

Combination equation 1 and 3, can obtain following formula:

$V_o=\frac{V_{\mathrm{ref}}}{k\&times;n}-V_F-I_o\&times;R_{\mathrm{eq}}$ (formula 4)

Based on equation 4, output voltage reduces along with the increase of output current.

Yet this power converting system 100 usually can not change response fast and is effectively provided output loading.Therefore, very wish to improve the technology of primary side sensing and adjustment.

Summary of the invention

The present invention relates to integrated circuit.More specifically, the invention provides the switching frequency and the peak current that in response to load, change regulates.As just example, the present invention has been applied to flyback power supply converter.But will recognize, the present invention has range of application widely.

According to an embodiment, a kind of system for switching power converters comprises the first comparator, pulse-width modulation maker, actuator assembly and voltage change rate detection components.The first comparator be configured to receive the first input signal and the second input signal and at least the information based on being associated with the first input signal and the second input signal generate the first comparison signal, at least relevant with output current with the supply convertor feedback signal of the first input signal is associated.Pulse-width modulation maker is configured at least receive the first comparison signal and the Information generation modulation signal based on being associated with the first comparison signal at least, and modulation signal is associated with modulating frequency.In addition, actuator assembly be configured to receive modulation signal and to switch output drive signal to regulate the primary current of the armature winding of the supply convertor of flowing through, the peak value size during primary current and modulating frequency corresponding each modulation period is associated.In addition, voltage change rate detection components be configured to sampled feedback signal with generate first during the first modulation period through sampled signal and sampled feedback signal with second during generating for the second modulation period through sampled signal, voltage change rate detection components is also configured to compare through sampled signal with second through the size of sampled signal first, and the second modulation period is after the first modulation period.This system is also configured to judge that first deducts second through sampled signal and whether meet one or more first conditions through sampled signal.If one or more first conditions are satisfied, this system is also configured to increase modulating frequency and the peak value size relevant with primary current.

According to another embodiment, a kind of method for switching power converters comprises: receive the first input signal and the second input signal, process the information being associated with the first input signal and the second input signal, and at least the information based on being associated with the first input signal and the second input signal generates the first comparison signal, at least relevant with output current with the supply convertor feedback signal of the first input signal is associated.The method also comprises: at least receives the first comparison signal, processes the information be associated with the first comparison signal, and the Information generation modulation signal based on being associated with the first comparison signal at least, modulation signal is associated with modulating frequency.In addition, the method comprises: receive modulation signal, process the information being associated with modulation signal, and to regulate the primary current of the armature winding of the supply convertor of flowing through, the peak value size during primary current and modulating frequency corresponding each modulation period is associated to switch output drive signal.In addition, the method comprises: sampled feedback signal to be to generate for first during the first modulation period through sampled signal, and sampled feedback signal to be to generate for second during the second modulation period through sampled signal, and the second modulation period is after the first modulation period.In addition, the method comprises: judge that first deducts second through sampled signal and whether meet one or more first conditions through sampled signal, and if one or more first condition is satisfied, increase modulating frequency and the peak value size relevant with primary current.

According to another embodiment, a kind of system for switching power converters comprises the first comparator, pulse-width modulation maker, actuator assembly and voltage change rate detection components.The first comparator be configured to receive the first input signal and the second input signal and at least the information based on being associated with the first input signal and the second input signal generate the first comparison signal, at least relevant with output current with the supply convertor feedback signal of the first input signal is associated.Pulse-width modulation maker is configured at least receive the first comparison signal and the Information generation modulation signal based on being associated with the first comparison signal at least, and modulation signal is associated with modulating frequency.In addition, actuator assembly be configured to receive modulation signal and to switch output drive signal to regulate the primary current of the armature winding of the supply convertor of flowing through, the peak value size during primary current and modulating frequency corresponding each modulation period is associated.In addition, voltage change rate detection components be configured to sampled feedback signal with generate first during the first modulation period through sampled signal and sampled feedback signal with second during generating for the second modulation period through sampled signal, voltage change rate detection components is also configured to compare through sampled signal with second through the size of sampled signal first, and the second modulation period is after the first modulation period.This system is also configured to: judge that first deducts second through sampled signal and whether be greater than first threshold voltage through sampled signal, first threshold voltage is more than or equal to zero; If first deducts second through sampled signal, through sampled signal, be judged as and be greater than first threshold voltage, increase modulating frequency and the peak value size relevant with primary current.This system is also configured to: judge that second deducts first through sampled signal and whether be greater than Second Threshold voltage through sampled signal, Second Threshold voltage is more than or equal to zero; And if second deduct first through sampled signal and be judged as and be greater than Second Threshold voltage through sampled signal, reduce modulating frequency and the peak value size relevant with primary current.

According to another embodiment, a kind of method for switching power converters comprises: receive the first input signal and the second input signal, process the information being associated with the first input signal and the second input signal, and at least the information based on being associated with the first input signal and the second input signal generates the first comparison signal, at least relevant with output current with the supply convertor feedback signal of the first input signal is associated.The method also comprises: at least receives the first comparison signal, processes the information be associated with the first comparison signal, and the Information generation modulation signal based on being associated with the first comparison signal at least, modulation signal is associated with modulating frequency.In addition, the method comprises reception modulation signal, process the information be associated with modulation signal, and to switch output drive signal with the flow through primary current of armature winding of supply convertor of adjusting, the peak value size during primary current and modulating frequency corresponding each modulation period is associated.In addition, the method comprises that sampled feedback signal is to generate for first during the first modulation period through sampled signal, and sampled feedback signal to be to generate for second during the second modulation period through sampled signal, and the second modulation period is after the first modulation period.In addition, the method comprises and judges that first deducts second through sampled signal and whether be greater than first threshold voltage through sampled signal, and first threshold voltage is more than or equal to zero; And if first deducts second through sampled signal, through sampled signal, be judged as and be greater than first threshold voltage, increase modulating frequency and the peak value size relevant with primary current.In addition, the method comprises and judges that second deducts first through sampled signal and whether be greater than Second Threshold voltage through sampled signal, and Second Threshold voltage is more than or equal to zero; And if second deducts first through sampled signal, through sampled signal, be judged as and be greater than Second Threshold voltage, reduce modulating frequency and the peak value size relevant with primary current.

Depend on embodiment, can obtain one or more in these benefits.With reference to the detailed description and the accompanying drawings below, can understand all sidedly these benefits of the present invention and each other object, feature and advantage.

Accompanying drawing explanation

Fig. 1 is the simplification diagram that the classical inverse excitation power supply transformation system with primary side sensing and adjustment is shown.

Fig. 2 is the simplification diagram that the traditional operation mechanism of this flyback power supply transformation system 100 is shown.

Fig. 3 (A) and (B) be the peak current of function and the simplification diagram of switching frequency illustrating according to the output current as the power converting system in constant voltage (CV) pattern of the embodiment of the present invention.

Fig. 4 illustrates in response to output current, to carry out the simplification diagram of the power converting system of by-pass cock frequency and peak current according to the embodiment of the present invention.

Fig. 5 is according to the simplified timing diagram of the switched-mode power supply transformation system 400 with constant voltage control of the embodiment of the present invention.

Fig. 6 illustrates the simplification diagram that carrys out according to another embodiment of the present invention the power converting system of by-pass cock frequency and peak current in response to output current.

Fig. 7 be illustrate according to further embodiment of this invention there is voltage compensation in response to output current, carry out the simplification diagram of the power converting system of by-pass cock frequency and peak current.

Fig. 8 is the simplification diagram illustrating according to the offset current maker for power converting system 700 of the embodiment of the present invention.

Fig. 9 be illustrate according to further embodiment of this invention there is offset modulation electric current in response to output current, carry out the simplification diagram of the power converting system of by-pass cock frequency and peak current.

Figure 10 is according to another embodiment of the present invention for the simplified timing diagram of switched-mode power supply transformation system.

Figure 11 illustrates in response to output current, to change the dynamically simplification diagram of some assembly of the power converting system of by-pass cock frequency and peak current according to further embodiment of this invention.

Figure 12 illustrates the simplified flow chart to the dynamic adjustments of the peak current of switching frequency and armature winding in power converting system according to an embodiment of the invention.

Figure 13 is the simplified timing diagram to the switched-mode power supply transformation system of the dynamic adjustments of the peak current of switching frequency and armature winding that has according to the embodiment of the present invention.

Figure 14 is the simplification diagram illustrating according to some assembly of the power converting system of further embodiment of this invention.

Figure 15 is according to the simplified timing diagram of the switched-mode power supply transformation system as shown in figure 14 of further embodiment of this invention.

Figure 16 is the simplification diagram illustrating according to some assembly of the power converting system of further embodiment of this invention.

Figure 17 is according to the simplified timing diagram of the power converting system as shown in figure 16 of further embodiment of this invention.

Embodiment

The present invention relates to integrated circuit.More specifically, the invention provides the switching frequency and the peak current that in response to load, change regulates.As just example, the present invention has been applied to flyback power supply converter.But will recognize, the present invention has range of application widely.

With reference to figure 1 and Fig. 2, the information exchange relevant with the output voltage of power converting system 100 is everlasting in each switch periods and is only sampled once.Switch periods and switching frequency are inversely proportional to, and switching frequency is set to lower to reduce power consumption conventionally when non-loaded or light-load conditions.But if load becomes full load from non-loaded or underload, low switching frequency usually causes the non-constant of dynamic response of power converting system 100.For example, if switching frequency is hundreds of hertz when non-loaded or light-load conditions, the information relevant with the output voltage of power converting system 100 every several milliseconds (msec) is sampled once.For example, if load (becomes full load from non-loaded or underload, output current becomes 1A when full load), output voltage may drop to below acceptable level, this be because for example after several milliseconds next sampling be performed before controller can not respond.A kind of mode of head it off is the switching frequency while increasing non-loaded or light-load conditions.But if switching frequency increases, the peak current of armature winding during non-loaded or light-load conditions should be limited so that output voltage can not surpass acceptable level.However, its switching frequency still can not meet required dynamic response.

Fig. 3 (A) and (B) be the peak current of function and the simplification diagram of switching frequency illustrating according to the output current as the power converting system in constant voltage (CV) pattern of the embodiment of the present invention.These diagrams are only examples, and it should not limit the scope of claim undeservedly.Those skilled in the art will recognize that many variants, substitutions and modifications.Curve 310 for example represents, as output current (, I _out) switching frequency (for example, the F of function _sw), and curve 320 for example represents, as output current (, I _out) peak current (for example, the I of armature winding of function _peak).For example,, if I _out=I ₁, this power converting system is in no-load condition, and if I _out=I ₆, this power converting system is in full-load conditions.In another example, I ₁< I ₂< I ₃< I ₄< I ₅< I ₆.

As shown in Fig. 3 (A), according to an embodiment, if I ₁≤ I _out< I ₂, switching frequency (for example, F _sw) with slope S _1ffor example, along with output current (, I _out) change, if I ₂≤ I _out< I ₅, switching frequency (for example, F _sw) with slope S _2ffor example, along with output current (, I _out) change, and if I ₅≤ I _out< I ₆, switching frequency (for example, F _sw) with slope S _3ffor example, along with output current (, I _out) change.For example, slope S _1f, S _2fand S _3fin each be greater than zero.

As shown in Fig. 3 (B), according to another embodiment, if I ₁≤ I _out< I ₃, each switch periods (for example, T _sw) peak current (for example, I _peak) with slope S _1pfor example, along with output current (, I _out) change, if I ₃≤ I _out< I ₄, with slope S _2pchange, and if I ₄≤ I _out< I ₆, with slope S _3pchange.For example, slope S _1pand S _3pbe equal to or be greater than zero.In another example, slope S _2pbe greater than zero.According to another embodiment, this power converting system is at I ₁≤ I _out< I ₃shi Liyong pulse-frequency modulation(FM) operates, at I ₃≤ I _out< I ₄shi Liyong pulse-frequency modulation(FM) and pulse-width modulation operate, and at I ₄≤ I _out< I ₆shi Liyong pulse-frequency modulation(FM) operates.For example, slope S _1pand S _3pbe equal to zero, and peak current (for example, I _peak) with slope S _2pfrom I _minincrease to I _max.

Fig. 4 illustrates in response to output current, to carry out the simplification diagram of the power converting system of by-pass cock frequency and peak current according to the embodiment of the present invention.This diagram is only example, and it should not limit the scope of claim undeservedly.Those skilled in the art will recognize that many variants, substitutions and modifications.

Power converting system 400 comprises the equivalent resistor 1440, resistor 1450 and 1452 and rectifier diode 1460 of armature winding 1410, secondary winding 1412, auxiliary winding 1414, switch 1420 (for example, bipolar transistor), current-sense resistor 1430, output cable.In addition, power converting system 400 also comprises demagnetization detector 420, sampling controller 422, sampling switch 424, capacitor 426, oscillator 428, error amplifier 430, index maker 440, comparator 450, trigger assembly 452, gate driver 454, comparator 460,462 and 464, logic module 466, resistor 470 and 472 and capacitor 474.

For example, armature winding 1410, secondary winding 1412, auxiliary winding 1414, switch 1420, current-sense resistor 1430, equivalent resistor 1440, resistor 1450 and 1452 and rectifier diode 1460 respectively with armature winding 110, secondary winding 112, auxiliary winding 114, switch 120, current-sense resistor 130, equivalent resistor 140, resistor 150 and 152 and rectifier diode 160 identical.In another example, demagnetization detector 420, sampling controller 422, sampling switch 424, capacitor 426, oscillator 428, error amplifier 430, index maker 440, comparator 450, trigger assembly 452, gate driver 454, comparator 460,462 and 464, logic module 466, resistor 470 and 472 and capacitor 474 be positioned on chip 410.In another example, chip 410 comprises terminal 412,414 and 416.

Fig. 5 is according to the simplified timing diagram of the switched-mode power supply transformation system 400 with constant voltage control of the embodiment of the present invention.This diagram is only example, and it should not limit the scope of claim undeservedly.Those skilled in the art will recognize that many variants, substitutions and modifications.

As shown in Figure 5, waveform 510 represents conducting and the cut-off condition as the switch 1420 of the function of time, ramp signal (for example, the V that waveform 520 represents as the function of time _ramp), amplifying signal 431 (for example, the V that waveform 530 represents as the function of time _ea), and waveform 540 expressions are as the feedback signal 1455 of the function of time.In addition, sensing signal 461 (for example, the V that waveform 550 represents as the function of time _cs), control signal 475 (for example, the V that waveform 552 represents as the function of time _p), and waveform 554 expressions for example, as threshold signal 473 (, the V of the function of time _{th_max}).

As shown in Figure 4 and Figure 5, according to an embodiment, the information exchange relevant with output voltage crossed auxiliary winding 1414 and is extracted.For example, auxiliary winding 1414 generates feedback signal 1455 (for example, with waveform 540 corresponding V at node 1454 places with resistor 1450 together with 1452 _fB).In another example, feedback signal 1455 (for example, V _fB) at least by demagnetization detector 420 and sampling switch 424, received.

According to an embodiment, as response, demagnetization detector 420 is to index maker 440 output signals 421.For example, oscillator 428 is also to index maker 440 clock signals 429.In another example, index maker 440 generates following ramp signal 441 (for example, the V corresponding with waveform 520 _ramp):

$V_{\mathrm{ramp}}\left(n\right)=(V_{\mathrm{refb}}-V_{\mathrm{refa}})\&times;e^{-\left(\frac{n\&times;T}{\mathrm{\&tau;}}\right)}+V_{\mathrm{refa}}$ (formula 5)

Wherein, V _rampthe voltage swing that represents ramp signal 441.In addition, V _refaand V _refball represent constant voltage level.For example, V _refaequal 1V, V _refbequal 3V.In addition, n represents that the ramp signal 441 from the last reset of ramp signal 441 calculating with the number of clock cycle is from V _refbthe time declining.T is the clock cycle of clock signal 429.τ is time constant.Particularly, if 0≤n≤64, τ=128 * T; If 64 < n≤128, τ=256 * T; If 128 < n≤256, τ=512 * T; And if 256 < n≤512, τ=1024 * T.

In one embodiment, when switch 1420 cut-off, the energy being stored in transformer is released to output.For example, demagnetization process starts, and the electric current of the secondary winding 1412 of flowing through tilts to decline linearly.For example,, when demagnetization process almost finishes and when the electric current of the secondary winding 1412 of flowing through approaches zero, sampled signal 423 is sampled controller 422 and generates for example to come, to feedback signal 1455 (, the V corresponding with waveform 540 by closed sampling switch 424 _fB) sampling.In another example, after sampling processing completes, sampling switch 424 disconnects in response to sampled signal 423.In another example, institute's sampled voltage is maintained on capacitor 426, and quilt and reference voltage V _ref(for example 2V) compares.

According to an embodiment, institute samples/keep voltage and reference voltage V _refdifference by error amplifier 430, amplified to generate amplifying signal 431 (for example, the V corresponding with waveform 530 _ea).According to another embodiment, amplifying signal 431 is received by the negative input terminal of resistor 470 and comparator 450.For example, resistor 470 is for example come together, to comparator 460 output control signal 475 (, the V corresponding with waveform 552 with resistor 472 and capacitor 474 _p).In another example, resistor 470 and 472 and capacitor 474 form compensating networks, this compensating network is carried out decay and low-pass filtering and generates control signal 475 amplifying signal 431.In another example, comparator 450 also receives ramp signal 441 (for example, the V corresponding with waveform 520 at positive input terminal place _ramp), and as response, to trigger assembly 452, send output signal 451.

As shown in Figure 5, according to an embodiment, when demagnetization process starts, ramp signal 441 (for example, the V corresponding with waveform 520 _ramp) be restored to initial value (for example, V _refb), but after demagnetization process completes, ramp signal 441 declines with exponential manner.In another embodiment, if becoming in size, ramp signal 441 is less than amplifying signal 431 (for example, the V corresponding with waveform 530 _ea), comparison signal 451 becomes logic low, thereby makes signal 453 become logic high and make switch 1420 conductings.

In another embodiment, flow through the primary current 1411 of armature winding 1410 by current-sense resistor 1430 sensings, as response, current-sense resistor 1430 for example, to comparator 460,462 and 464 output sensing signals 461 (, the V corresponding with waveform 550 _cs).For example, if for example, switch 1420 closures (, being switched on), transformer stored energy and primary current 1411 tilt to rise linearly, thereby make primary current sensing signal 461 (V for example, _cs) also tilt to rise linearly.In another example, the positive terminal reception control signal 475 of comparator 460 (for example, the V corresponding with waveform 552 _p), and the negative terminal of comparator 460 receives sensing signal 461.In another example, the positive terminal receive threshold signal 463 of comparator 462 (for example, the V corresponding with waveform 554 _{th_max}), and the negative terminal of comparator 462 receives sensing signal 461.In another example, the positive terminal of comparator 464 receives sensing signal 461, and the negative terminal receive threshold signal 465 of comparator 464 is (for example,, in size than V _{th_max}little V _{th_min}).

In another embodiment, comparator 460,462 and 464 generates respectively comparison signal 471,473 and 479, and all these signals are all received by logic module 466.For example, logic module 466 is as response formation logic signal 467.

According to an embodiment, trigger assembly 452 receives comparison signal 451 and logical signal 467, and generates signal 453 as response.For example, as shown in Figure 5, if comparison signal 451 for logic low logical signal 467 be logic high, signal 453 is logic high, and if comparison signal 451 for logic low logical signal 467 be also logic low, signal 453 is logic low.In another example, if logical signal 467 is logic low, from

the signal 453 of terminal is also logic low to make switch 1420 cut-offs, and no matter comparison signal 451 is logic high or logic low.In another example, if logical signal 467 is that logic high and comparison signal 451 are logic low, signal 453 is that logic high is so that switch 1420 conductings.

According to another embodiment, signal 453 is received by gate driver 454, gate driver 454 via terminal 412 for example, to switch 1420 output drive signals 455 (, via terminal 412 to bipolar transistor 1420 output base currents 455).For example, if signal 453 is logic high, drive signal 455 to make switch 1420 closures (for example, be switched on, as shown in waveform 510).In another example, if signal 453 is logic low, drive signal 455 to make switch 720 disconnect (for example, be cut off, as shown in waveform 510).

As shown in Figure 4 and Figure 5, according to an embodiment, output loading (for example, output current) is larger, amplifying signal 431 (for example, the V corresponding with waveform 530 _ea) just become larger, thus make (for example, T deadline of switch 1420 _off) become shorter and make switching frequency (for example, F _sw) become higher.According to another embodiment, output loading (for example, output current) is less, amplifying signal 431 (for example, the V corresponding with waveform 530 _ea) just become less, thus make (for example, T deadline of switch 1420 _off) become longer and make switching frequency (for example, F _sw) become lower, as shown in Fig. 3 (A).

According to another embodiment, logic module 466 comprise or (OR) door and other assembly.For example,, for example, if control signal 475 (, V _p) size be less than threshold signal 465 (for example, V _{th_min}), sensing signal 461 (for example, the V corresponding with waveform 550 _cs) peak value size be restricted to threshold signal 465 (for example, the V corresponding with waveform 556 _{th_min}) size, and the ON time of switch 1420 (for example, T _on) and the peak value size of primary current 1411 keep constant, and no matter output loading (for example, output current) how, as I in Fig. 3 (B) ₁≤ I _out< I ₃time shown in.

In another example, for example, if control signal 475 (, V _p) size be greater than threshold signal 465 (for example, V _{th_min}) but be less than threshold signal 463 (for example, V _{th_max}), sensing signal 461 (for example, the V corresponding with waveform 550 _cs) peak value size be restricted to control signal 475 (for example, the V corresponding with waveform 552 _p) size.For example, control signal 475 (for example, V _p) size for example, along with output loading (, output current), increase; So ON time (for example, T of switch 1420 _on) and the peak value size of primary current 1411 all for example, along with output loading (, output current) increases, as I in Fig. 3 (B) ₃≤ I _out< I ₄time shown in.

In another example, for example, if control signal 475 (, V _p) size become and be greater than threshold signal 463 (for example, V _{th_max}), primary current sensing signal 461 (for example, the V corresponding with waveform 550 _cs) peak value size be restricted to threshold signal 463 (for example, the V corresponding with waveform 554 _{th_max}) size.For example, the ON time of switch 1420 (for example, T _on) and the peak value size of primary current 1411 all keep constant, and no matter output loading (for example, output current) how, as I in Fig. 3 (B) ₄≤ I _out< I ₆time shown in.

As discussed above and further emphasize at this, Fig. 4 is only example, and it should not limit the scope of claim undeservedly.Those skilled in the art will recognize that many variants, substitute and revise.For example, bipolar transistor 1420 can be substituted by MOS transistor, as shown in Figure 6.

Fig. 6 illustrates the simplification diagram that carrys out according to another embodiment of the present invention the power converting system of by-pass cock frequency and peak current in response to output current.This diagram is only example, and it should not limit the scope of claim undeservedly.Those skilled in the art will recognize that many variants, substitute and revise.

Power converting system 600 comprises the equivalent resistor 1640, resistor 1650 and 1652 and rectifier diode 1660 of armature winding 1610, secondary winding 1612, auxiliary winding 1614, switch 1620 (for example, MOS transistor), current-sense resistor 1630, output cable.In addition, power converting system 600 also comprises demagnetization detector 620, sampling controller 622, sampling switch 624, capacitor 626, oscillator 628, error amplifier 630, index maker 640, comparator 650, trigger assembly 652, gate driver 654, comparator 660,662 and 664, logic module 666, resistor 670 and 672 and capacitor 674.

For example, armature winding 1610, secondary winding 1612, auxiliary winding 1614, switch 1620, current-sense resistor 1630, equivalent resistor 1640, resistor 1650 and 1652 and rectifier diode 1660 respectively with armature winding 110, secondary winding 112, auxiliary winding 114, switch 120, current-sense resistor 130, equivalent resistor 140, resistor 150 and 152 and rectifier diode 160 identical.In another example, demagnetization detector 620, sampling controller 622, sampling switch 624, capacitor 626, oscillator 628, error amplifier 630, index maker 640, comparator 650, trigger assembly 652, gate driver 654, comparator 660,662 and 664, logic module 666, resistor 670 and 672 and capacitor 674 be positioned on chip 610.In another example, chip 610 comprises terminal 612,614 and 616.

In another example, except having carried out some modification to drive to substitute the MOS transistor of bipolar transistor, demagnetization detector 620, sampling controller 622, sampling switch 624, capacitor 626, oscillator 628, error amplifier 630, index maker 640, comparator 650, trigger assembly 652, gate driver 654, comparator 660, 662 and 664, logic module 666, resistor 670 and 672 and capacitor 674 respectively with demagnetization detector 420, sampling controller 422, sampling switch 424, capacitor 426, oscillator 428, error amplifier 430, index maker 440, comparator 450, trigger assembly 452, gate driver 454, comparator 460, 462 and 464, logic module 466, resistor 470 and 472 and capacitor 474 similar.

Fig. 7 be illustrate according to further embodiment of this invention there is voltage compensation in response to output current, carry out the simplification diagram of the power converting system of by-pass cock frequency and peak current.This diagram is only example, and it should not limit the scope of claim undeservedly.Those skilled in the art will recognize that many variants, substitutions and modifications.

Power converting system 700 comprises the equivalent resistor 1440, resistor 1450 and 1452 and rectifier diode 1460 of armature winding 1410, secondary winding 1412, auxiliary winding 1414, switch 1420 (for example, bipolar transistor), current-sense resistor 1430, output cable.In addition, power converting system 700 also comprises demagnetization detector 420, sampling controller 422, sampling switch 424, capacitor 426, oscillator 428, error amplifier 430, index maker 440, comparator 450, trigger assembly 452, gate driver 454, comparator 460,462 and 464, logic module 466, resistor 470 and 472 and capacitor 474.In addition, power converting system 700 also comprises that frequency determines that assembly 720, frequency are to current converter 730 and electric current formation component 740.

For example, demagnetization detector 420, sampling controller 422, sampling switch 424, capacitor 426, oscillator 428, error amplifier 430, index maker 440, comparator 450, trigger assembly 452, gate driver 454, comparator 460,462 and 464, logic module 466, resistor 470 and 472, capacitor 474, frequency determine that assembly 720, frequency are positioned on chip 710 to current converter 730 and electric current formation component 740.In another example, chip 710 comprises terminal 712,714 and 716.In another example, frequency determines that assembly 720, frequency are a plurality of parts of offset current maker to current converter 730 and electric current formation component 740.

According to an embodiment, as shown in Fig. 3 (A), at least for I ₂≤ I _out< I ₅, switching frequency for example, for example, along with output loading (, output current) increases and therefore reflected the size (, the size of output current) of output loading.For example, frequency determines that assembly 720 receives the output signal (it is also received by gate driver 454) of trigger assembly 452, and generates the big or small frequency signal 721 that represents switching frequency.In another example, frequency signal 721 is received to current converter 730 by frequency, and is converted into current signal 731.In another example, electric current formation component 740 received current signals 731 and conduct response generate offset current 741 (for example, I _comp).In another example, electric current formation component 740 also comprises that low pass filter for example, with smooth compensating electric current 741 (, I _comp).

According to another embodiment, offset current 741 (for example, I _comp) via terminal 716, flow out chip 710, and generate following bucking voltage:

$V_{\mathrm{comp}}=\frac{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HSA00000552366600031.png,HSA00000552366600051.png"\; state="\{\{state\}\}">R</figure-callout>}}_1\&times;R_2}{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HSA00000552366600031.png,HSA00000552366600051.png"\; state="\{\{state\}\}">R</figure-callout>}}_1+{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="HSA00000552366600141.png,HSA00000552366600161.png"\; state="\{\{state\}\}">R</figure-callout>}}_2}\&times;I_{\mathrm{comp}}$ (formula 6)

Wherein, V _comprepresent bucking voltage, and I _comprepresent offset current 741.In addition, R ₁and R ₂the resistance value that represents respectively resistor 1450 and 1452.For example, bucking voltage is used to the voltage drop that compensation causes because of output cable (it is represented by equivalent resistor 1440), and the output voltage error that causes because of the intersection adjustment of secondary winding and auxiliary winding when non-loaded and light-load conditions of compensation.In another example, bucking voltage is used to regulate feedback signal 1455.

Fig. 8 is the simplification diagram illustrating according to the offset current maker for power converting system 700 of the embodiment of the present invention.This diagram is only example, and it should not limit the scope of claim undeservedly.Those skilled in the art will recognize that many variants, substitutions and modifications.

This offset current maker comprise comparator 1110 and 1112, trigger assembly 1120, signal generator 1130, trigger assembly 1140, encoding pack 1150, with (AND) door 1160, switch 1170, current sink 1172 and current source 1174.In addition, this offset current maker also comprises transistor 1280,1282,1284 and 1286, resistor 1290 and capacitor 1292.

As shown in Figure 8, according to an embodiment, depend on that the offset current 741 of switching frequency is generated.For example, because higher switching frequency for example, corresponding to heavier loading condition (, larger output current), and lower switching frequency for example, corresponding to non-loaded or light-load conditions (, less output current); Therefore for lower switching frequency, generate larger offset current, and generate less offset current for higher switching frequency.In another example, offset current 741 is smoothed by the low pass filter being formed by resistor 1290 and capacitor 1292.In another example, offset current 741 flows out chip 710 via terminal 716, and generates bucking voltage (for example, the V superimposed with feedback signal together with 1452 with resistor 1450 _comp).

As discussed above and emphasize at this, Fig. 7 is only example, and it should not limit the scope of claim undeservedly.Those skilled in the art will recognize that many variants, substitutions and modifications.For example, bipolar transistor 1420 can be substituted by MOS transistor, and one or more assemblies of power converting system 700 are modified to drive the MOS transistor that substitutes bipolar transistor.

Fig. 9 be illustrate according to further embodiment of this invention there is offset modulation electric current in response to output current, carry out the simplification diagram of the power converting system of by-pass cock frequency and peak current.This diagram is only example, and it should not limit the scope of claim undeservedly.Those skilled in the art will recognize that many variants, substitutions and modifications.

Power converting system 900 comprises the equivalent resistor 1940, resistor 1950 and 1952 and rectifier diode 1960 of armature winding 1910, secondary winding 1912, auxiliary winding 1914, switch 1920 (for example, bipolar transistor), current-sense resistor 1930, output cable.In addition, power converting system 900 also comprises demagnetization detector 920, sampling controller 922, sampling switch 924, capacitor 926, oscillator 928, error amplifier 930, index maker 940, comparator 950, trigger assembly 952 and gate driver 954.In addition, power converting system 900 also comprises that frequency determines that assembly 1720, frequency are to current converter 1730 and electric current formation component 1740.In addition, power converting system 900 also comprises that comparator 960, frequency are to current converter 1750, electric current formation component 1760 and resistor 1932.

For example, armature winding 1910, secondary winding 1912, auxiliary winding 1914, switch 1920, current-sense resistor 1930, equivalent resistor 1940, resistor 1950 and 1952 and rectifier diode 1960 respectively with armature winding 110, secondary winding 112, auxiliary winding 114, switch 120, current-sense resistor 130, equivalent resistor 140, resistor 150 and 152 and rectifier diode 160 identical.In another example, demagnetization detector 920, sampling controller 922, sampling switch 924, capacitor 926, oscillator 928, error amplifier 930, index maker 940, comparator 950, trigger assembly 952, gate driver 954, frequency determine that assembly 1720, frequency are positioned on chip 910 to current converter 1750 and electric current formation component 1760 to current converter 1730, electric current formation component 1740, comparator 960, frequency.In another example, chip 910 comprises terminal 912,914 and 916.

In another example, demagnetization detector 920, sampling controller 922, sampling switch 924, capacitor 926, oscillator 928, error amplifier 930, index maker 940, comparator 950, trigger assembly 952, gate driver 954, frequency is determined assembly 1720, frequency to current converter 1730 and electric current formation component 1740 substantially respectively with demagnetization detector 420, sampling controller 422, sampling switch 424, capacitor 426, oscillator 428, error amplifier 430, index maker 440, comparator 450, trigger assembly 452, gate driver 454, frequency is determined assembly 720, frequency is identical to current converter 730 and electric current formation component 740.

According to an embodiment, at least in the region II of Fig. 3 (A), switching frequency for example, for example, along with output loading (, output current) increases and therefore reflected the size (, the size of output current) of output loading.For example, frequency determines that assembly 1720 receives the output signal (it is also received by gate driver 954) of trigger assembly 952, and generates the big or small frequency signal 1721 that represents switching frequency.In another example, frequency signal 1721 is received to current converter 1730 and 1750 by frequency respectively, and is converted into current signal 1731 and 1751.

As shown in Figure 9, according to an embodiment, electric current formation component 1740 received current signals 1731 and conduct response generate offset current 1741 (for example, I _comp), and electric current formation component 1760 received current signals 1751 and conduct response generation offset modulation electric current 1761 (for example, I _offset).For example, offset modulation electric current 1761 (for example, I _offsettherefore) along with the increase of switching frequency, reduce, and also for example, along with the increase of the output loading increase of output current (, along with), reduce.

According to another embodiment, offset modulation electric current 1761 (for example, I _offset) via terminal 914, flow out chip 910, and generate following offset voltage:

V _offset=R _c* I _offset(formula 7)

Wherein, V _offsetrepresent offset voltage, and I _offsetrepresent offset modulation electric current 1761.In addition, R _cthe resistance value that represents resistor 1932.

For example, this offset voltage is used to regulate sensing signal 963 (for example, V _cs).In another example, utilize equation 7, the peak value size of the primary current 1911 of the armature winding 1912 of flowing through is confirmed as follows:

$I_{\mathrm{peak}}=\frac{V_{\mathrm{th}\_\mathrm{OC}}-R_c\&times;I_{\mathrm{offset}}}{R_s}$ (formula 8)

Wherein, I _peakthe peak value size that represents primary current 1911, and V _{th_OC}represent threshold signal 961.In addition, R _cthe resistance value that represents resistor 1932.For example, according to equation 8, offset modulation electric current 1761 (for example, I _offset) for example, along with the increase of the output loading increase of output current (, along with) and reduce; Therefore, the peak value size of primary current 1911 for example, increases along with the increase (, along with the increase of output current) of output loading, but can not surpass V _{th_OC}/ R _s.

As shown in Figure 9, according to some embodiment, offset current 1741 (for example, I _comp) at least by frequency, to current converter 1730 and electric current formation component 1740, generated, and offset modulation electric current 1761 (for example, I _offset) at least by frequency, to current converter 1750 and electric current formation component 1760, generated.For example,, for example, although offset current 1741 (, I _comp) and offset modulation electric current 1761 (for example, I _offset) be all from being determined that by frequency the frequency signal 1721 that assembly 1720 generates draws, but electric current 1741 and 1761 is different and separates.

As discussed above and emphasize at this, Fig. 9 is only example, and it should not limit the scope of claim undeservedly.Those skilled in the art will recognize that many variants, substitutions and modifications.For example, bipolar transistor 1920 can be substituted by MOS transistor, and one or more assemblies of power converting system 900 are modified to drive the MOS transistor that substitutes bipolar transistor.In another example, electric current formation component 1740 and 1760 comprises low pass filter separately.In another example, electric current formation component 1740 and 1760 is shared low pass filters, and this low pass filter is used for smooth compensating electric current 1741 (for example, I _comp) and offset modulation electric current 1761 (for example, I _offset) both.

According to another embodiment, a kind of system for switching power converters comprises: comparator, be configured to receive first signal and secondary signal, and the Information generation comparison signal based on being associated with first signal and secondary signal at least.First signal is at least associated with the output current of supply convertor.In addition, this system comprises: pulse-width modulation maker, be configured at least receive comparison signal, and the Information generation modulation signal based on being associated with comparison signal at least; And actuator assembly, be configured to receive modulation signal and to switch output drive signal to regulate the primary current of the armature winding of the supply convertor of flowing through.This modulation signal with modulation period corresponding modulating frequency be associated.Modulating frequency in the first current range with the first slope along with output current increases, modulating frequency in the second current range with the second slope along with output current increases, and modulating frequency in the 3rd current range with the 3rd slope along with output current increases.The first current range and the 3rd current range are at least separated by the second current range, and each of the first slope, the second slope and the 3rd slope is greater than zero.Peak value size during primary current and each modulation period is associated.Peak value size remains unchanged or increases with the 4th slope with respect to output current in the 4th current range, and the 4th slope is equal to or greater than zero.Peak value size in the 5th current range with the 5th slope along with output current increases, and the 5th slope is greater than zero.Peak value size remains unchanged or increases with respect to output current with the 6th slope in the 6th current range, and the 6th slope is equal to or greater than zero.The 4th current range and the 6th current range are at least separated by the 5th current range.For example, this system realizes according to Fig. 4, Fig. 6, Fig. 7 and/or Fig. 9.

According to another embodiment, a kind of method for switching power converters comprises reception first signal and secondary signal.First signal is at least associated with the output current of supply convertor.In addition, the method comprises the information that processing is associated with first signal and secondary signal, at least the Information generation comparison signal based on being associated with first signal and secondary signal, at least receives comparison signal, and the Information generation modulation signal based on being associated with comparison signal at least.In addition, the method comprises reception modulation signal, and at least the information output drive signal based on being associated with modulation signal to regulate the primary current of the armature winding of the supply convertor of flowing through.This modulation signal with modulation period corresponding modulating frequency be associated.Modulating frequency in the first current range with the first slope along with output current increases, modulating frequency in the second current range with the second slope along with output current increases, and modulating frequency in the 3rd current range with the 3rd slope along with output current increases.The first current range and the 3rd current range are at least separated by the second current range, and each of the first slope, the second slope and the 3rd slope is greater than zero.Peak value size during primary current and each modulation period is associated.Peak value size remains unchanged or increases with the 4th slope with respect to output current in the 4th current range, and the 4th slope is equal to or greater than zero.Peak value size in the 5th current range with the 5th slope along with output current increases, and the 5th slope is greater than zero.Peak value size remains unchanged or increases with respect to output current with the 6th slope in the 6th current range, and the 6th slope is equal to or greater than zero.The 4th current range and the 6th current range are at least separated by the 5th current range.For example, the method realizes according to Fig. 4, Fig. 6, Fig. 7 and/or Fig. 9.

According to another embodiment, a kind of system for switching power converters comprises: the first comparator, be configured to receive first signal and secondary signal, and Information generation the first comparison signal based on being associated with first signal and secondary signal at least.First signal is at least associated with the output current of supply convertor.In addition, this system comprises: the second comparator, be configured to receive the 3rd signal and the 4th signal, and Information generation the second comparison signal based on the 3rd signal and the 4th signal correction connection at least.The 3rd signal is relevant with secondary signal, and the 4th signal is associated with the primary current of the armature winding of the supply convertor of flowing through.In addition, this system comprises: logic module, is configured at least receive the second comparison signal and the Information generation logical signal based on being associated with the second comparison signal at least; Pulse-width modulation maker, is configured at least receive the first comparison signal and logical signal, and the Information generation modulation signal based on being associated with the first comparison signal and logical signal at least; And actuator assembly, be configured to receive modulation signal and to switch output drive signal to regulate primary current.For example, this system realizes according to Fig. 4, Fig. 6 and/or Fig. 7.

According to another embodiment, a kind of method for switching power converters comprises reception first signal and secondary signal, and first signal is at least associated with the output current of supply convertor.In addition, the method comprises: the information that processing is associated with first signal and secondary signal, Information generation the first comparison signal based on being associated with first signal and secondary signal at least, and receive the 3rd signal and the 4th signal, the 3rd signal is relevant with secondary signal.The 4th signal is associated with the primary current of the armature winding of the supply convertor of flowing through.In addition, the method comprises: process the information with the 3rd signal and the 4th signal correction connection, Information generation the second comparison signal based on the 3rd signal and the 4th signal correction connection at least, at least receive the second comparison signal, process the information be associated with the second comparison signal, and the Information generation logical signal based on being associated with the second comparison signal at least.And, the method comprises: at least receive the first comparison signal and logical signal, the Information generation modulation signal based on being associated with the first comparison signal and logical signal at least, receive modulation signal, and at least the information output drive signal based on being associated with modulation signal to regulate primary current.For example, the method realizes according to Fig. 4, Fig. 6 and/or Fig. 7.

According to another embodiment, a kind of system for switching power converters comprises: the first comparator, be configured to receive first signal and secondary signal, and Information generation the first comparison signal based on being associated with first signal and secondary signal at least, and first signal is at least associated with the output current of supply convertor.In addition, this system comprises: the second comparator, be configured to receive the 3rd signal and the 4th signal, and Information generation the second comparison signal based on the 3rd signal and the 4th signal correction connection at least.The 3rd signal is relevant with secondary signal, and the 4th signal is associated with the primary current of the armature winding of the supply convertor of flowing through.In addition, this system comprises: logic module, is configured at least receive the second comparison signal and the Information generation logical signal based on being associated with the second comparison signal at least; Pulse-width modulation maker, is configured at least receive the first comparison signal and logical signal, and the Information generation modulation signal based on being associated with the first comparison signal and logical signal at least.Modulation signal is associated with modulating frequency.In addition, this system comprises actuator assembly, be configured to receive modulation signal and to switch output drive signal to regulate primary current.In addition, this system comprises: the first electric current maker, be configured to receive modulation signal and at least the information based on being associated with modulating frequency output offset current to generate bucking voltage and to regulate first signal; And the second electric current maker, be configured to receive the modulation signal being associated with modulating frequency, and at least the information output offset electric current based on being associated with modulating frequency with generation offset voltage and regulate the 4th signal.For example, this system realizes according to Fig. 9.

According to another embodiment, a kind of method for switching power converters comprises reception first signal and secondary signal.First signal is at least associated with the output current of supply convertor.In addition, the method comprises: the information that processing is associated with first signal and secondary signal, Information generation the first comparison signal based on being associated with first signal and secondary signal at least, and receive the 3rd signal and the 4th signal, the 3rd signal is relevant with secondary signal.The 4th signal is associated with the primary current of the armature winding of the supply convertor of flowing through.In addition, the method comprises: process the information with the 3rd signal and the 4th signal correction connection, Information generation the second comparison signal based on the 3rd signal and the 4th signal correction connection at least, at least receive the second comparison signal, process the information be associated with the second comparison signal, and the Information generation logical signal based on being associated with the second comparison signal at least.And the method comprises: at least receive the first comparison signal and logical signal, and the Information generation modulation signal based on being associated with the first comparison signal and logical signal at least.Modulation signal is associated with modulating frequency.In addition, the method comprises reception modulation signal, at least the information output drive signal based on being associated with modulation signal is to regulate primary current, at least the information based on being associated with modulating frequency output offset current to be to generate bucking voltage and to regulate first signal, and at least the information output offset electric current based on being associated with modulating frequency to generate offset voltage and to regulate the 4th signal.For example, the method realizes according to Fig. 9.

Return to Fig. 7, switching frequency (for example, F _sw) under non-loaded or light-load conditions (for example, less output current) be increased, to the output voltage primary side is increased to when non-loaded or underload become full load to proper level (for example,, in full load time output current become 1A) in output loading.Yet according to some embodiment, in some cases, the change of output loading may cause the output voltage fast-descending in primary side, and switching frequency is only just conditioned after a certain delay reducing fast in response to output voltage.

Figure 10 is according to another embodiment of the present invention for the simplified timing diagram of switched-mode power supply transformation system 700.This diagram is only example, and it should not limit the scope of claim undeservedly.Those skilled in the art will recognize that many variants, substitutions and modifications.Waveform 1002 represents as the output voltage in the primary side of the function of time, and waveform 1004 expressions are as conducting and the cut-off condition of the switch 1420 of the function of time.For example, if waveform 1004 is logic high, switch 1420 closures (for example, conducting), and if waveform 1004 is logic low, switch 1420 disconnects (for example, cut-off).

Three time period T have been shown in Figure 10 _a, T _band T _c.Time period T _aat moment t ₀start and at moment t ₁finish time period T _bat moment t ₁start and at moment t ₄finish, and time period T _cat moment t ₄start and at moment t ₆finish.For example, moment t ₂and t ₃at time period T _bin, and moment t ₅at time period T _cin.In another example, t ₀≤ t ₁≤ t ₂≤ t ₃≤ t ₄≤ t ₅≤ t ₆.

In one embodiment, at time period T _aduring this time, power converting system 700 has light output loading or non-loaded, and output loading is unchanged.For example, output voltage keeps constant (for example, the size as shown in waveform 1,002 1006).In another example, without the peak current of by-pass cock frequency or armature winding, and switch 1420 has constant switch periods 1010 (for example, the T as shown in waveform 1004 ₀).

In another embodiment, at time period T _bbeginning, output loading becomes full load from non-loaded or underload.For example, output voltage starts from size 1006 (for example,, at t ₁place) fast-descending, but feedback signal 1455 is at t ₂can again not be sampled before.Therefore, according to some embodiment, at t ₂before, the decline of output voltage may not can be detected.

According to an embodiment, detect delay that output voltage declines may be due to bucking voltage last much longer.For example, offset current 741 terminal 716 of flowing through, and generate the variation that affects feedback signal 1455, as follows:

$V_{\mathrm{FB}}=\frac{R_2}{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HSA00000552366600031.png,HSA00000552366600051.png"\; state="\{\{state\}\}">R</figure-callout>}}_1+{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="HSA00000552366600141.png,HSA00000552366600161.png"\; state="\{\{state\}\}">R</figure-callout>}}_2}\&times;V_{\mathrm{aux}}+I_{\mathrm{comp}}\&times;\frac{R_1{R}_2}{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HSA00000552366600031.png,HSA00000552366600051.png"\; state="\{\{state\}\}">R</figure-callout>}}_1+R_2}$ (formula 9)

Wherein, V _fBrepresent feedback signal 1455, and V _auxthe voltage that represents auxiliary winding 1414.In addition, I _comprepresent offset current 741.R ₁and R ₂the resistance value that represents respectively resistor 1450 and 1452.As shown in equation 9, according to some embodiment, although V _auxreflected the output voltage in primary side, but due to I _compmake V _fBconventionally can accurately not represent the output voltage in primary side.

For example,, at time period T _bduring this time, although output voltage fast-descending, sampled feedback signal 1455 (for example, V _fB) size may not can change very greatly, and it may keep being greater than reference voltage (for example, V _ref).Therefore, according to some embodiment, amplifying signal (for example, V _ea) can not change very large, and and then the switching frequency of switch 1420 do not regulated rapidly.In another example, offset current 741 responds the change of output loading at leisure, to guarantee the stability of the output in primary side.Therefore, according to some embodiment, at time period T _bduring this time only for example, by monitoring feedback signal 1455 (, V _fB) size the fast-descending of output voltage can not be detected.

According to another embodiment, as shown in figure 10, when the size of feedback signal 1455 drops to a certain degree in response to the quick change of output voltage, the peak current of switching frequency and armature winding may finally be conditioned.For example,, at time period T _cbeginning, the switch periods of switch 1420 is reduced to period 1014 (for example, T from the period 1010 ₁), the period 1014 is corresponding to the switching frequency increasing.In another example, as response, output voltage is dropping to minimal size 1016 (for example,, at moment t ₅place) start afterwards to increase, and continue to increase to size 1012 (for example,, at moment t ₆place).

According to another embodiment, switching frequency is increased after the delay that the fast reducing of output voltage is responded.For example, this delay at least comprises the time period T that equals several original switch cycles (for example, three switch periods) _b.Therefore, need a kind of scheme with the peak current of quick dynamically by-pass cock frequency and armature winding that reduces to postpone.

Figure 11 be illustrate according to further embodiment of this invention in response to the output current simplification diagram of some assembly of the power converting system of by-pass cock frequency and peak current dynamically.This diagram is only example, and it should not limit the scope of claim undeservedly.Those skilled in the art will recognize that many variants, substitutions and modifications.

Power converting system 1100 comprises the resistor 1450 and 1452 in secondary side.In addition, power converting system 1100 comprises sampling switch 1502, capacitor 1504, buffer 1506, error amplifier 1508, index maker 1510, demagnetization detector 1512, oscillator 1514, comparator 1516, trigger assembly 1518, gate driver 1520, voltage drop compensation assembly 1522, logic module 1524, comparator 1526, 1528 and 1530, voltage change rate detection components 1532 (for example, slope detection assembly), dynamically strengthen logic control assembly 1534, resistor 1536 and 1538, capacitor 1540, non-(NOT) door 1594, with non-(NAND) door 1590 and with (AND) door 1598.

For example, sampling switch 1502, capacitor 1504, buffer 1506, error amplifier 1508, index maker 1510, demagnetization detector 1512, oscillator 1514, comparator 1516, trigger assembly 1518, gate driver 1520, voltage drop compensation assembly 1522, logic module 1524, comparator 1526,1528 and 1530, voltage change rate detection components 1532, dynamically strengthen logic control assembly 1534, resistor 1536 and 1538, capacitor 1540, not gate 1594, NAND gate 1590 and be positioned on chip 1102 with door 1598.In another example, chip 1102 comprises terminal 1542,1544 and 1546.

According to an embodiment, sampling switch 1502, capacitor 1504, error amplifier 1508, index maker 1510, demagnetization detector 1512, oscillator 1514, comparator 1516, trigger assembly 1518, gate driver 1520, logic module 1524, comparator 1526, 1528 and 1530, resistor 1536 and 1538 and capacitor 1540 substantially respectively with sampling switch 424, capacitor 426, error amplifier 430, index maker 440, demagnetization detector 420, oscillator 428, comparator 450, trigger assembly 452, gate driver 454, logic module 466, comparator 460, 464 and 462, resistor 470 and 472 and capacitor 474 identical.In another example, voltage drop compensation assembly 1522 comprises that frequency determines that assembly 720, frequency are to current converter 730 and electric current formation component 740.In another example, terminal 1542,1544 and 1546 is identical with terminal 712,714 and 716 respectively.In another example, power converting system 1100 comprises armature winding 1410, secondary winding 1412, auxiliary winding 1414, switch 1420 and current-sense resistor 1430.

According to another embodiment, by auxiliary winding 1414, extract the information about output voltage.For example, feedback signal 1455 (for example, V _fB) at node 1454 places as shown in figure 11, be generated.In another example, feedback signal 1455 is at least received by demagnetization detector 1512, sampling switch 1502 and voltage change rate detection components 1532.

According to another embodiment, in response to the feedback signal 1455 receiving, demagnetization detector 1512 is to index maker 1510 output signals 1562.For example, index maker 1510 generates following ramp signal 1566 (for example, V _ramp):

$V_{\mathrm{ramp}}\left(n\right)=(V_{\mathrm{refb}}-V_{\mathrm{refa}})\&times;e^{-\left(\frac{n\&times;T}{\mathrm{\&tau;}}\right)}+V_{\mathrm{refa}}$ (formula 10)

Wherein, V _rampthe voltage swing that represents ramp signal 1566.In addition, V _refaand V _refball represent constant voltage level.For example, V _refaequal 1V, V _refbequal 3V.In addition, n represents that the ramp signal 1566 from the last reset of ramp signal 1566 calculating with the number of clock cycle is from V _refbthe time declining.T is the clock cycle from the clock signal 1558 of oscillator 1514.In addition, τ is time constant.

According to another embodiment, for example, when switch 1420 disconnects (, cut-off), the energy being stored in transformer is released to output.For example, demagnetization process starts, and the electric current of the secondary winding 1412 of flowing through tilts to decline linearly.In another example, when demagnetization process almost finishes, when the electric current of the secondary winding 1412 of flowing through approaches zero, sampling switch 1502 receives sampled signal (for example, pulse signal) and is closed with sampled feedback signal 1455.In another example, after sampling processing completes, sampling switch 1502 disconnects.In another example, institute's sampled voltage is maintained on capacitor 1504, and quilt and reference voltage V _ref(for example, 2V) compare.

According to an embodiment, institute samples/keep voltage and reference voltage V _refdifference by error amplifier 1508, amplified to generate the error signal 1584 (V for example of amplification _ea).For example, the error signal 1584 of amplification is received by the negative input terminal of resistor 1536 and comparator 1516.In another example, resistor 1536 is come together to comparator 1526 output control signals 1586 with resistor 1538 and capacitor 1540.In another example, resistor 1536 and 1538 and capacitor 1540 form compensating networks, this compensating network is carried out conversion process and low-pass filtering and generates control signal 1586 fault in enlargement signal 1584.

According to another embodiment, comparator 1516 also receives ramp signal 1566 (for example, V at positive input terminal place _ramp), and to NAND gate 1590, send output signal 1588 as response.For example, NAND gate 1590 also receive by not gate 1594, generated through anti-phase gate-control signal 1592.In another example, receive from the output signal 1593 of NAND gate 1590 and clock signal 1595 (for example, Timer_CC), and to trigger assembly 1518 generating output signals 1597 with door 1598.

In one embodiment, the primary current 1411 of the armature winding 1410 of flowing through is by current-sense resistor 1430 sensings, and as response, current-sense resistor 1430 for example, to comparator 1526,1528 and 1530 output sensing signal 1564 (, V _cs).For example, if for example, switch 1420 closures (, conducting), transformer stored energy and primary current 1411 tilt to rise linearly, thereby make sensing signal 1564 (for example, V _cs) also tilt to rise linearly.In another example, the positive terminal reception control signal 1586 of comparator 1526, and the negative terminal of comparator 1526 receives sensing signal 1564.In another example, positive terminal receive threshold signal 1531 (for example, the V of comparator 1530 _{th_max}) and the negative terminal of comparator 1530 receive sensing signal 1564.In another example, the negative terminal of comparator 1528 receives the positive terminal receive threshold signal 1529 of sensing signal 1564 and comparator 1528 (for example,, in size than V _{th_max}little V _{th_min}).

In another embodiment, comparator 1526,1528 and 1530 generates respectively comparison signal 1521,1523 and 1525, and all these signals are all received by logic module 1524.For example, logic module 1524 is as response formation logic signal 1574.

According to an embodiment, trigger assembly 1518 receives with the output signal 1597 of door 1598 with from the logical signal 1574 of logic module 1524.For example, as response, trigger assembly 1518 generates signal 1599.In another example, signal 1599 is received by gate driver 1520, gate driver 1520 via terminal 1542 for example, to switch 1420 output drive signals 1527 (, via terminal 1542 to bipolar transistor 1420 output base currents).In another example, if signal 1599 is logic high, drive signal 1527 to make switch 1420 closures (for example, conducting).In another example, if signal 1599 is logic low, drive signal 1527 to make switch 1420 disconnect (for example, cut-off).

According to another embodiment, output loading (for example, output current) is larger, fault in enlargement signal 1584 (for example, V _ea) just become larger, thus make (for example, T deadline of switch 1420 _off) become shorter and make switching frequency (for example, F _sw) become higher.According to another embodiment, output loading (for example, output current) is less, fault in enlargement signal 1584 (for example, V _ea) just become less, thus make (for example, T deadline of switch 1420 _off) become longer and make switching frequency (for example, F _sw) become lower.

According to another embodiment, logic module 1524 comprise or (OR) door and other assembly.For example,, for example, if the size of control signal 1586 is less than threshold signal 1529 (, V _{th_min}), sensing signal 1564 (for example, V _cs) peak value size be restricted to threshold signal 1529 (for example, V _{th_min}) size, and the ON time of switch 1420 (for example, T _on) and the peak value size of primary current 1411 keep constant, and no matter output loading (for example, output current) how.

In another example, for example, if the size of control signal 1586 is greater than threshold signal 1529 (, V _{th_min}) but be less than threshold signal 1531 (for example, V _{th_max}), sensing signal 1564 (for example, V _cs) peak value size be restricted to the size of control signal 1586.For example, the size of control signal 1586 for example, increases along with output loading (, output current); So ON time (for example, T of switch 1420 _on) and the peak value size of primary current 1411 all for example, along with output loading (, output current) increases.

In another example, if becoming, the size of control signal 1586 is greater than threshold signal 1531 (for example, V _{th_max}), sensing signal 1564 (for example, V _cs) peak value size be restricted to threshold signal 1531 (for example, V _{th_max}) size.For example, the ON time of switch 1420 (for example, T _on) and the peak value size of primary current 1411 all keep constant, and no matter output loading (for example, output current) how.

According to another embodiment, as shown in figure 11, voltage drop compensation assembly 1522 receives the output signals 1588 of comparator 1516, the clock signal 1558 of oscillator 1514 and the output signal 1552 that dynamically strengthens logic control assembly 1534.According to another embodiment, as response, voltage drop compensation assembly 1522 generates offset current 1548 (for example, I _comp).For example, offset current 1548 (for example, I _comp) via terminal 1546, flow out chip 1102, and generate following bucking voltage:

$V_{\mathrm{comp}}=\frac{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HSA00000552366600031.png,HSA00000552366600051.png"\; state="\{\{state\}\}">R</figure-callout>}}_1\&times;R_2}{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HSA00000552366600031.png,HSA00000552366600051.png"\; state="\{\{state\}\}">R</figure-callout>}}_1+{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="HSA00000552366600141.png,HSA00000552366600161.png"\; state="\{\{state\}\}">R</figure-callout>}}_2}\&times;I_{\mathrm{comp}}$ (formula 11)

Wherein, V _comprepresent bucking voltage, and I _comprepresent offset current 1548.In addition, R ₁and R ₂the resistance value that represents respectively resistor 1450 and 1452.For example, bucking voltage is used to the voltage drop that compensation causes because of the output cable in primary side, and the output voltage error that causes because of the intersection adjustment of secondary winding and auxiliary winding when non-loaded and light-load conditions of compensation.In another example, bucking voltage is used to regulate feedback signal 1455.

According to another embodiment, voltage change rate detection components 1532 is sampled to feedback signal 1455 during the particular switch cycle of switch 1420, and the current feedback signal sampling is compared with the feedback signal previously having sampled during last switch periods.For example, based on this result relatively, voltage change rate detection components 1532 is then to dynamic enhancing logic control assembly 1534 output signals 1550.In another example, signal 1550 comprises one or more subsignals.According to another embodiment, dynamically strengthen logic control assembly 1534 as response generating output signal 1552,1554 and 1556, these output signals are provided as respectively the other input signal of voltage drop compensation assembly 1522, index maker 1510 and logic module 1524.

For example, output signal 1552 is provided for and regulates offset current 1548 (for example, the I being generated by voltage drop compensation assembly 1522 _comp).In another example, output signal 1554 is provided for and changes ramp signal 1566 (for example, the V being generated by index maker 1510 _ramp) so that by-pass cock frequency.In another example, output signal 1556 is provided for the peak current that logic module 1524 regulates armature winding.

Figure 12 illustrates the simplified flow chart to the dynamic adjustments of the peak current of switching frequency and armature winding in power converting system 1100 according to an embodiment of the invention.This diagram is only example, and it should not limit the scope of claim undeservedly.Those skilled in the art will recognize that many variants, substitutions and modifications.

Processing for by-pass cock frequency dynamically and peak current at least comprises: for the processing 1204 of sampled feedback signal, for calculating the processing 1206 of demagnetization period, for storing the processing 1208 of sampled feedback signal, for the signal previously having sampled being deducted to the processing 1210 of the current signal sampling, for the processing 1212 that increases peak current and switching frequency, for the current signal sampling being deducted to the processing 1214 of the signal previously having sampled, for reducing the processing 1216 of peak current and switching frequency, for determining the processing 1218 of peak current and switching frequency and also generating for definite pulse duration the processing 1220 that drives signal.

According to an embodiment, processing 1204 places, feedback signal 1455 for example, is sampled to generate the current signal sampling (for example, X (n)) by voltage change rate detection components 1532 during current switch periods (, T (n)).According to another embodiment, processing 1206 places, at least the information based on for example, being associated with the current feedback signal sampling (, X (n)) is calculated the demagnetization period.According to another embodiment, processing 1208 places, the current feedback signal sampling is stored at least one or more assembly of voltage change rate detection components 1532.

According to another embodiment, in processing 1210, the current feedback signal sampling (for example, X (n)) be used to voltage change rate detection components 1532 in last switch periods (for example, T (n-1)) feedback signal previously having sampled during (for example, X (n-1)) is subtracted each other.For example, for example, for example, if deducting the current signal sampling (, X (n)), the signal previously having sampled (, X (n-1)) surpasses first threshold voltage (for example, V _th1), process 1212 and be performed.In another example, for example, for example, if deducting the current signal sampling (, X (n)), the signal previously having sampled (, X (n-1)) is no more than first threshold voltage (for example, V _th1), process 1214 and be performed.In another example, first threshold voltage is more than or equal to zero.

According to another embodiment, in processing 1212, peak current and switching frequency are increased.For example, voltage change rate detection components 1532 is to dynamic enhancing logic control assembly 1534 output signals 1550.In another example, as response, dynamically strengthen logic control assembly 1534 output signals 1554 and 1556 to increase the peak current of switching frequency and armature winding.In another example, signal 1554 is for example provided for index maker 1510, to change ramp signal 1566 (, V _ramp); Therefore, the deadline of switch 1420 (for example, T _off) be shortened and switching frequency is increased.In another example, signal 1556 is provided for logic module 1524 to increase the peak current of armature winding.In another example, the peak current of switching frequency and armature winding is increased to respectively maximum switching frequency and peak inrush current.In another example, after processing 1212 completes, process 1220 and be performed.

According to another embodiment, processing 1214 places, the current feedback signal sampling (for example, X (n)) (be for example subtracted in voltage change rate detection components 1532 last switch periods, T (n-1)) feedback signal previously having sampled during (for example, X (n-1)).For example, for example, for example, if deduct the current signal sampling (, X (n)) of the signal (, X (n-1)) previously having sampled, surpass Second Threshold voltage (for example, V _th2), process 1216 and be performed.In another example, for example, if for example, for example, be no more than Second Threshold voltage (, V if deduct the current signal sampling (, X (n)) of the signal (, X (n-1)) previously having sampled _th2), process 1218 and be performed.In another example, Second Threshold voltage (for example, V _th2) and first threshold voltage (for example, V _th1) identical or different.In another example, Second Threshold voltage is more than or equal to zero.

According to another embodiment, processing 1216 places, peak current and switching frequency are reduced.For example, voltage change rate detection components 1532 is to dynamic enhancing logic control assembly 1534 output signals 1550.In another example, as response, dynamically strengthen logic control assembly 1534 output signals 1554 and 1556 to increase the peak current of switching frequency and armature winding.In another example, signal 1554 is for example provided for index maker 1510, to change ramp signal 1566 (, V _ramp); Therefore, the deadline of switch 1420 (for example, T _off) be extended and switching frequency is lowered.In another example, signal 1556 is provided for logic module 1524 to reduce the peak current of armature winding.In another example, the peak current of switching frequency and armature winding is reduced to respectively minimal switching frequency and minimum peak electric current.In another example, after processing 1216 completes, process 1220 and be performed.

According to another embodiment, processing 1218 places, for example, based on fault in enlargement signal 1584 (, V _ea) determine peak current and switching frequency (for example, for next switch periods).After processing 1218 completes, process 1220 and be performed.According to another embodiment, processing 1220 places, drive the pulse duration of signal 1527 determined and drive signal 1527 to be generated.

As discussed above and further emphasize at this, Figure 12 is only example, and it should not limit the scope of claim undeservedly.Those skilled in the art will recognize that many variants, substitute and revise.For example, processing 1214 and 1216 is skipped.In another example, processing 1210 and 1212 is skipped.In another example, process 1206 and be skipped.In another example, process 1208 and be skipped.

Figure 13 is the simplified timing diagram to the switched-mode power supply transformation system 1100 of the dynamic adjustments of the peak current of switching frequency and armature winding that has according to the embodiment of the present invention.This diagram is only example, and it should not limit the scope of claim undeservedly.Those skilled in the art will recognize that many variants, substitute and revise.

As shown in figure 13, waveform 1302 represents as the output voltage in the primary side of the function of time, waveform 1304 represents conducting and the cut-off condition as the switch 1420 of the function of time, and waveform 1306 expressions for example, as sensing signal (, the V of the function of time _cS).In addition, waveform 1308 represents as the output current in the primary side of the function of time, and waveform 1310 represent as the function of time from the signal 1550 of voltage change rate detection components 1532 or a subsignal of signal 1550.Figure 13 illustrates four time periods, comprise T _d, T _e, T _fand T _g.

According to an embodiment, at time period T _dduring this time, power converting system 1100 has light output loading or no-output load, and output loading is unchanged.For example, output voltage keeps constant (for example, being the size 1316 shown in waveform 1302), and output current also keeps constant (for example, being the size 1322 shown in waveform 1308).In another example, voltage change rate detection components 1532 does not surpass first threshold voltage (for example, V in Check processing 1210 _th1) any change or process and in 1214, to surpass Second Threshold voltage (for example, V _th2) any change, and the therefore subsignal (for example,, as shown in waveform 1310) of the low level signal 1550 of formation logic or signal 1550.In another example, at time period T _dduring this time, in response to the signal 1550 of logic low or a subsignal of signal 1550, for the processing 1212 of the peak current of dynamic adjustments switching frequency or armature winding with process 1216 and be not performed.

In addition, according to another embodiment, at time period T _dduring this time, switch 1420 keeps constant switch periods 1312 (for example, the T as shown in waveform 1304 ₂).For example, logic high indicator cock 1420 closures (for example, conducting) as shown in waveform 1304, and the logic low indicator cock as shown in waveform 1,304 1420 disconnects (for example, cut-off).In addition, according to another embodiment, flow through armature winding (for example, winding 1410) primary current (for example, primary current 1411) for example, by current-sense resistor (, resistor 1430) sensing, as response, its output sensing signal (for example, V corresponding with waveform 1306 _cS).For example,, at time period T _dduring this time, if for example, switch 1420 closures (, conducting), primary current tilts to rise linearly, tilts to rise to size 1326, thereby make sensing signal linearity as shown in the crest in waveform 1306.

In one embodiment, at time period T _ebeginning, output loading becomes full load from non-loaded or underload.For example, as response, output voltage is from time period T _esize 1316 fast-descendings of beginning (for example, linearly or non-linearly) are to time period T _ethe size 1318 of ending place.In addition, in another example, at time period T _eduring this time, output current increases to size 1324 fast from size 1322.

In another embodiment, at time to approach section T _eending place time, switch 1420 closures (for example, as shown in the rising edge of waveform 1304), and then switch 1420 disconnects (for example, as shown in the trailing edge of waveform 1304), and demagnetization process starts.For example, when demagnetization process almost finishes, feedback signal 1455 is carried out current sampling by voltage change rate detection components 1532 in processing 1204.In another example, the current feedback signal sampling in processing 1210 by with last switch periods during the feedback signal previously having sampled compare.According to some embodiment, if surpassing the amount of the current feedback signal sampling, the size of the feedback signal previously having sampled is no less than first threshold voltage (for example, V _th1), voltage change rate detection components 1532 detects and recognizes this state of fast reducing of output voltage.Therefore, from the signal 1550 of voltage change rate detection components 1532 or a subsignal of signal 1550 at time period T _fbeginning from logic low, become logic high (as shown in the rising edge of waveform 1310).The size of the current feedback signal sampling surpasses the amount of the feedback signal previously having sampled and is for example no less than, in Second Threshold voltage (, V in another embodiment _th2), voltage change rate detection components 1532 detects and recognizes this state of quick rising of output voltage.

According to another embodiment, as response, at time period T _fduring this time, processing 1212 is performed.For example, dynamically strengthen logic control assembly 1534 as response output signal 1554 and 1556 peak currents with increase switching frequency and armature winding.In another example, the peak current of switching frequency and armature winding is increased to respectively maximum switching frequency and peak inrush current.In another example, the switch periods of switch 1420 for example, from cycle 1312 (, the T as shown in waveform 1304 ₂) be reduced to cycle 1314 (for example, the T as shown in waveform 1304 ₃).In another example, the increase of the peak current of armature winding makes the peak value of sensing signal increase (for example, increasing to the size 1328 as shown in waveform 1306).

In addition, according to another embodiment, at time period T _fduring this time, as response, output voltage reverts to the peak current (for example,, as shown in waveform 1302) that increases switching frequency and armature winding.For example, output voltage is from time period T _fthe size 1318 of beginning increases to size 1320, and then at time period T _fremainder keep size 1320.In another example, size 1320 equals size 1316.As shown in figure 13, according to some embodiment, the delay of the peak current of by-pass cock frequency and armature winding is approximately time period T _e, it for example, than original switch cycle 1312 (, T ₂) much shorter.For example, compare with Figure 10, the delay of adjusting is significantly reduced.

In another embodiment, at time period T _gbeginning, output voltage has kept size 1320 to reach several switch periods (for example, four switch periods).For example, voltage change rate detection components 1532 is changed into logic low (as shown in the trailing edge of waveform 1310) by a subsignal of signal 1550 or signal 1550 from logic high.According to an embodiment, as response, in processing 1218, dynamically strengthen logic control assembly 1534 output signals to reduce the peak current of switching frequency and armature winding.For example, the switch periods of switch 1420 is increased to cycle 1330 (for example, the T as shown in waveform 1304 ₄).In another example, the peak current of primary current reduce make the crest of sensing signal be reduced to the size 1332 as shown in waveform 1306.In another example, at time period T _fduring this time, output voltage and output current remain on respectively size 1320 and big or small 1324 places.

Figure 14 is the simplification diagram illustrating according to some assembly of the power converting system 1100 of further embodiment of this invention.This diagram is only example, and it should not limit the scope of claim undeservedly.Those skilled in the art will recognize that many variants, substitute and revise.

Power converting system 1100 comprises the resistor 1450 and 1452 in secondary side.In addition, power converting system 1100 comprise sampling switch 1502, capacitor 1504, buffer 1506, error amplifier 1508, index maker 1510, demagnetization detector 1512, oscillator 1514, comparator 1516, trigger assembly 1518, gate driver 1520, voltage drop compensation assembly 1522, logic module 1524, comparator 1526,1528 and 1530, voltage change rate detection components 1532, dynamically strengthen logic control assembly 1534, resistor 1536 and 1538, capacitor 1540, not gate 1594, NAND gate 1590 and with door 1598.

Voltage change rate detection components 1532 comprises 1602,1604,1606,1608,1636 and 1638, two capacitors 1670 and 1672 of six switches, and three operational amplifiers 1674,1676 and 1678.In addition, voltage change rate detection components 1532 comprises four resistors 1680,1682,1684 and 1686 and comparator 1688.For example, resistor 1680 and 1682 resistance equate, and the resistance of resistor 1684 and 1686 equates.In another example, switch 1606 and 1636 is disconnected simultaneously and is closed simultaneously, and switch 1608 and 1638 is disconnected simultaneously and is closed simultaneously.

In one embodiment, during the first switch periods, in response to the sampled signal at switch 1602 places, feedback signal 1455 is sampled and keeps at capacitor 1670 places, and the feedback signal 1690 of sampling/keeping be generated.In one example, during the second switch cycle, in response to another sampled signal at switch 1604 places, feedback signal 1455 is sampled and keeps at capacitor 1672 places, and the feedback signal 1692 of sampling/keeping be generated.In another example, the second switch cycle follows hard on the first switch periods.

According to another embodiment, the feedback signal 1690 and 1692 of sampling/keeping forms Buffer output via operational amplifier 1674 and 1676 respectively.For example, operational amplifier 1674 and 1676 is respectively through buffer generating output signal 1634 and 1635.In another example, when switch 1606 and 1636 disconnections and switch 1608 and 1638 closure, buffer output signal 1634 and 1635 is passed through respectively switch 1608 and 1638.In another example, buffer output signal 1634 and 1635 size equal respectively the feedback signal 1690 and 1692 of sampling/keeping.

According to another embodiment, resistor 1680 and 1682 is reception buffer output signal 1634 and 1635 and generate signal 1694 and 1696 respectively.Resistor 1680 and 1682,1684 and 1686 and operational amplifier 1678 form difference computing assemblies.For example, signal 1694 and 1696 carries out difference operation amplifier in operational amplifier 1678, and as response, operational amplifier 1678 generates amplifying signal (output signal of difference operation amplifier assembly) 1644.In another example, amplifying signal 1644 can be confirmed as follows:

$V_o=\frac{R_4}{{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="HSA00000552366600141.png"\; state="\{\{state\}\}">R</figure-callout>}}_3}\&times;(V_{\mathrm{FB}}(n-1)-V_{\mathrm{FB}}\left(n\right))$ (formula 12)

Wherein, V _orepresent amplifying signal 1644, V _fB(n-1) represent buffer output signal 1634, and V _fB(n) represent buffer output signal 1635.R ₃and R ₃' represent respectively the resistance of resistor 1680 and 1682, and R ₄and R ₄' represent respectively the resistance of resistor 1684 and 1686.For example, R ₃equal R ₃', and R ₄equal R ₄'.

According to another embodiment, the output signal 1644 of difference operation amplifier assembly amplifier 1678 in comparator 1688 by with threshold voltage 1646 (for example, V _{th_3}) compare.For example, the output 1550 of comparator 1688 is as dynamically strengthening the input signal of logic control assembly 1534.In another example, if the output signal 1644 of difference operation amplifier assembly is greater than threshold voltage 1646, mean the positive fast-descending of output voltage, dynamically strengthen 1534 outputs of logic control assembly for increasing the signal of the peak current of switching frequency and armature winding.In another example, threshold voltage 1646 (for example, V _{th_3}) size and first threshold voltage (for example, the V processing in 1210 _th1) proportional, as follows:

$V_{\mathrm{th}\_3}={\mathrm{<figure-callout\; id="1"\; label="V\; th"\; filenames="HSA00000552366600031.png,HSA00000552366600051.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{th}}\&times;\frac{R_4}{R_3}$ (formula 13)

Wherein, V _{th_3}represent threshold voltage 1646, and V _th1represent to process the first threshold voltage in 1210.In addition, R ₃and R ₃' represent respectively the resistance of resistor 1680 and 1682, and R ₄and R ₄' represent respectively the resistance of resistor 1684 and 1686.For example, R ₃equal R ₃', and R ₄equal R ₄'.

Figure 15 is according to the simplified timing diagram of the switched-mode power supply transformation system 1100 as shown in figure 14 of further embodiment of this invention.This diagram is only example, and it should not limit the scope of claim undeservedly.Those skilled in the art will recognize that many variants, substitute and revise.

As shown in figure 15, waveform 1802 represents conducting and the cut-off condition as the switch 1420 of the function of time, the first sampled signal for switch 1602 that waveform 1804 represents as the function of time, and waveform 1806 expressions are as second sampled signal for switch 1604 of the function of time.In addition, the first control signal for switch 1606 and 1636 that waveform 1808 represents as the function of time, and waveform 1810 expressions are as second control signal for switch 1608 and 1638 of the function of time.Figure 15 illustrates the different switch periods of switch 1420, for example time period T _h, T _iand T _j.For example, time period T _h, T _iand T _jthree continuous switch periods.In another example, moment t ₇and t ₈at time period T _hin, moment t ₉at time period T _iin, and moment t ₁₀at time period T _jin.In another example, t ₇≤ t ₈≤ t ₉≤ t ₁₀.

According to an embodiment, at time period T _hduring this time, switch 1420 is at moment t ₇place (for example, as shown in the trailing edge of waveform 1802) disconnection (for example, cut-off), and demagnetization process starts.For example,, at t ₈before, the first sampled signal is at moment t ₈be logic low (for example, as shown in waveform 1804), so switch 1602 disconnect (for example, cut-off) before.In another example, when demagnetization process is at moment t ₈when place almost finishes, the first sampled signal becomes logic high (for example,, as shown in the rising edge in waveform 1804) from logic low.Therefore, according to some embodiment, switch 1602 closures (for example, conducting), and and then, feedback signal 1455 is sampled and keeps at capacitor 1670 places.In another example, the feedback signal 1690 of sampling/keeping is generated to be provided for operational amplifier 1674.

According to another embodiment, at time period T _iduring this time, switch 1604 is used to sampled feedback signal 1455.For example,, at t ₉before, the second sampled signal that is provided for switch 1604 is logic low (for example, as shown in waveform 1806), so switch 1604 disconnects (for example, cut-off).In another example, at t ₉place, the second sampled signal becomes logic high (for example,, as shown in the rising edge in waveform 1806) from logic low.Therefore, according to some embodiment, switch 1604 conductings (for example, closure), and and then, feedback signal 1455 is sampled and keeps at capacitor 1672 places.In another example, the feedback signal 1692 of sampling/keeping is generated to be provided for operational amplifier 1676.

According to another embodiment, at time period T _iduring this time, switch 1606 and 1636 is used for respectively making through buffering feedback signal 1634 and 1635 by arriving operational amplifier 1678.For example, through buffering feedback signal 1634 and 1635 be respectively based on the feedback signal 1690 of sampling/keeping and 1692 generate.In another example, at moment t ₉before, for the first control signal of switch 1606 and 1636, be logic low (for example, as shown in waveform 1808), and be logic high (for example,, as shown in waveform 1810) for the second control signal of switch 1608 and 1638.Therefore,, according to some embodiment, switch 1606 and 1636 disconnects (for example, cut-off), and switch 1608 and 1638 closures (for example, conducting).

In another example, at moment t ₉place, the first control signal becomes logic high (for example,, as shown in the rising edge in waveform 1808) from logic low.Therefore, according to some embodiment, switch 1606 and 1636 closures (for example, conducting).In another example, at moment t ₉place, the second control signal becomes logic low (for example,, as shown in the lower liter edge in waveform 1810) from logic high.Therefore,, according to some embodiment, switch 1608 and 1638 disconnects (for example, cut-off).In another example, what from operational amplifier 1674 and 1676, generate passes through respectively switch 1606 and 1636 through buffering feedback signal 1634 and 1635.

In another embodiment, at time period T _jduring this time, the first sampled signal is at t ₁₀logic low not before, and at t ₁₀place becomes logic high from logic low.Therefore,, according to some embodiment, switch 1602 is at t ₁₀place's closed (for example, conducting).For example, feedback signal 1455 is sampled and is held at capacitor 1670 places, and new institute sample/keep feedback signal 1698 to be generated to offer operational amplifier 1674.In another example, sample/institute of institute keeps feedback signal 1698 to be cushioned by operational amplifier 1674, operational amplifier 1674 generations new through cushioning feedback signal 1699.

In another embodiment, at time period T _jduring this time, switch 1606 and 1636 is used for respectively making through buffering feedback signal 1699 and 1635 by arriving operational amplifier 1678.For example,, at moment t ₁₀before, for the second control signal of switch 1608 and 1638, be logic low (for example, as shown in waveform 1810), and be logic high (for example,, as shown in waveform 1808) for the first control signal of switch 1606 and 1636.Therefore,, according to some embodiment, switch 1608 and 1638 disconnects (for example, cut-off), and switch 1606 and 1636 closures (for example, conducting).

In another example, at moment t ₁₀place, the second control signal becomes logic high (for example,, as shown in the rising edge in waveform 1810) from logic low.Therefore, according to some embodiment, switch 1608 and 1638 closures (for example, conducting).In another example, at moment t ₁₀place, the first control signal becomes logic low (for example,, as shown in the lower liter edge in waveform 1808) from logic high.Therefore,, according to some embodiment, switch 1606 and 1636 disconnects (for example, cut-off).In another example, what from operational amplifier 1674 and 1676, generate passes through respectively switch 1608 and 1638 through buffering feedback signal 1699 and 1635.

Figure 16 is the simplification diagram illustrating according to some assembly of the power converting system 1100 of further embodiment of this invention.This diagram is only example, and it should not limit the scope of claim undeservedly.Those skilled in the art will recognize that many variants, substitute and revise.

This power converting system 1100 comprises the resistor 1450 and 1452 in secondary side.In addition, power converting system 1100 comprise sampling switch 1502, capacitor 1504, buffer 1506, error amplifier 1508, index maker 1510, demagnetization detector 1512, oscillator 1514, comparator 1516, trigger assembly 1518, gate driver 1520, voltage drop compensation assembly 1522, logic module 1524, comparator 1526,1528 and 1530, voltage change rate detection components 1532, dynamically strengthen logic control assembly 1534, resistor 1536 and 1538, capacitor 1540, not gate 1594, NAND gate 1590 and with door 1598.

Voltage change rate detection components 1532 comprises two switches 1850 and 1852, two capacitors 1854 and 1856, threshold level displacement component 1858, comparator 1860, d type flip flop assembly 1862 and sampling delay assembly 1864.

In one embodiment, during the first switch periods, the first sampled signal 1866 is provided for sampling delay assembly 1864.For example, as response, sampling delay assembly 1864 generates delayed sampled signal 1868.In another example, switch 1852 is closed (for example, conducting) in response to this delayed sampled signal 1868.Therefore,, according to some embodiment, feedback signal 1455 is sampled and is held to reach the first switch periods at capacitor 1856 places.In another example, sample/institute inhibit signal 1880 is generated.In another example, threshold level displacement component 1858 receives sample/institute of this institute inhibit signal 1880, and generating output signal 1870 is to offer comparator 1860.In another example, the size of output signal 1870 equals delayed sampled signal 1868 and deducts threshold voltage (for example, V _th4).In another example, threshold voltage (for example, V _th4) be more than or equal to zero.

In another embodiment, during the second switch cycle, the second sampled signal 1882 is provided for switch 1850.For example, as response, switch 1850 closures (for example, conducting).Therefore,, according to some embodiment, feedback signal 1455 is sampled and is held at capacitor 1854 places.In another example, sample/institute inhibit signal 1872 is generated to offer comparator 1860.In another example, sample/institute inhibit signal 1872 is compared with output signal 1870 in comparator 1860.In another example, based on this relatively, comparator 1860 provides signal 1874 to d type flip flop assembly 1862, and d type flip flop assembly 1862 also receives the 3rd sampled signal 1878 and gate-control signal 1876.In another example, d type flip flop assembly 1862 is to a subsignal of dynamic enhancing logic control assembly 1534 output signals 1550 or signal 1550.In another example, if the size of output signal 1870 be greater than sample/institute inhibit signal 1872, mean the positive fast-descending of output voltage, dynamically strengthen 1534 outputs of logic control assembly for the signal of the peak current of by-pass cock frequency and armature winding.

For example, the first sampled signal 1866, the second sampled signal 1882 and delayed sampled signal 1868 comprise pulse signal.The falling edge of sample in another example ,/institute inhibit signal 1872 pulse signals in the second sampled signal 1882 is compared with output signal 1870.In another example, the second switch cycle follows hard on the first switch periods.In another example, threshold voltage V _th4size equal to process first threshold voltage (for example, the V in 1210 _th1).In another example, threshold voltage V _th4size and threshold voltage 1646 (for example, V _{th_3}) proportional.

In another embodiment, during the second switch cycle, the second sampled signal 1882 is provided for sampling delay assembly 1864.For example, sampling delay assembly 1864 generates new delayed sampled signal as response.In another example, switch 1852 in response to this new delayed sampled signal closure (for example, conducting).Therefore,, according to some embodiment, feedback signal 1455 is sampled and is held to reach the second switch cycle at capacitor 1856 places.In another example, new sample/institute of institute inhibit signal generates to be provided for threshold level displacement component 1858.In another example, threshold level displacement component 1858 generates new output signal to offer comparator 1860 as response.In another example, another sample/institute inhibit signal that comparator 1860 generates with capacitor 1854 the new output signal from threshold level displacement component 1858 during the 3rd switch periods is compared.In another example, the 3rd switch periods follows hard on the second switch cycle.

Figure 17 is according to the simplified timing diagram of the power converting system as shown in figure 16 1100 of further embodiment of this invention.This diagram is only example, and it should not limit the scope of claim undeservedly.Those skilled in the art will recognize that many variants, substitute and revise.

As shown in figure 17, waveform 2002 represents conducting and the cut-off condition as the switch 1420 of the function of time, the feedback signal 1455 that waveform 2004 represents as the function of time.The 3rd sampled signal for switch 1850 that waveform 2006 represents as the function of time, and waveform 2008 expressions are as the 4th sampled signal for switch 1852 of the function of time.Figure 17 illustrates the different switch periods of switch 1420.For example, the whole switch periods T of switch 1420 _land switch periods T _ma part be illustrated.In another example, T _land T _mtwo continuous switch periods.In another example, moment t ₁₁, t ₁₂, t ₁₃and t ₁₄at time period T _lin, and moment t ₁₅and t ₁₆at time period T _min.In another example, t ₁₁≤ t ₁₂≤ t ₁₃≤ t ₁₄≤ t ₁₅≤ t ₁₆.

According to an embodiment, at time period T _lduring this time, switch 1420 is at moment t ₁₁place's (for example, as shown in the trailing edge of waveform 2002) disconnects (for example, cut-off), and demagnetization process starts (for example,, as shown in waveform 2004).For example, the 3rd sampled signal is at moment t ₁₂be logic low (for example, as shown in waveform 2006), and therefore switch 1850 disconnect (for example, cut-off) before.In another example, at moment t ₁₂place, the 3rd sampled signal becomes logic high (for example,, as shown in the rising edge in waveform 2006) from logic low.Therefore, according to some embodiment, switch 1850 closures (for example, conducting).In another example, feedback signal 1455 is sampled and is held to reach time period T at capacitor 1854 places _l.In another example, the 3rd sampled signal is at moment t ₁₃place becomes logic low (for example,, as shown in the trailing edge in waveform 2006) from logic high.Therefore,, according to some embodiment, switch 1850 disconnects (for example, cut-off).

According to another embodiment, at time period T _lduring this time, the 4th sampled signal is at moment t ₁₄be logic low (for example,, as shown in waveform 2008) before.For example, switch 1852 disconnects (for example, cut-off).In another example, at moment t ₁₄place, the 4th sampled signal becomes logic high (for example,, as shown in the rising edge in waveform 2008) from logic low.Therefore, according to some embodiment, switch 1852 closures (for example, conducting), and and then feedback signal 1455 at capacitor 1856 places, be sampled and be held.In another example, t ₁₃with t ₁₄between difference be predetermined amount of time T _d.In another example, feedback signal 1455 is at t ₁₃the size at place is approximately equal to feedback signal 1455 at t ₁₄the size at place.

According to another embodiment, at time period T _mduring this time, the 3rd sampled signal is at moment t ₁₅place becomes logic high (for example,, as fallen in waveform 2006 as shown in edge) from logic low.Therefore, according to some embodiment, switch 1850 closures (for example, conducting), and and then feedback signal 1455 at capacitor 1854 places, be sampled and be held.In another example, sample/institute inhibit signal 1872 is generated to offer comparator 1860.In another example, the 3rd sampled signal is at moment t ₁₆place becomes logic low (for example,, as shown in the lower liter edge in waveform 2006) from logic high.In another example, at moment t ₁₆place, the output signal 1870 being generated by threshold level displacement component 1858 at comparator 1860 places by with sample/institute inhibit signal 1872 compare.

According to another embodiment, a kind of system for switching power converters comprises the first comparator, pulse-width modulation maker, actuator assembly and voltage change rate detection components.The first comparator be configured to receive the first input signal and the second input signal and at least the information based on being associated with the first input signal and the second input signal generate the first comparison signal, at least relevant with output current with the supply convertor feedback signal of the first input signal is associated.Pulse-width modulation maker is configured at least receive the first comparison signal and the Information generation modulation signal based on being associated with the first comparison signal at least, and modulation signal is associated with modulating frequency.In addition, actuator assembly be configured to receive modulation signal and to switch output drive signal to regulate the primary current of the armature winding of the supply convertor of flowing through, the peak value size during primary current and modulating frequency corresponding each modulation period is associated.In addition, voltage change rate detection components be configured to sampled feedback signal with generate first during the first modulation period through sampled signal and sampled feedback signal with second during generating for the second modulation period through sampled signal, voltage change rate detection components is also configured to compare through sampled signal with second through the size of sampled signal first, and the second modulation period is after the first modulation period.This system is also configured to judge that first deducts second through sampled signal and whether meet one or more first conditions through sampled signal.If one or more first conditions are satisfied, this system is also configured to increase modulating frequency and the peak value size relevant with primary current.For example, this system at least realizes according to Figure 11, Figure 12, Figure 13, Figure 14, Figure 15, Figure 16 and/or Figure 17.

According to another embodiment, a kind of method for switching power converters comprises: receive the first input signal and the second input signal, process the information being associated with the first input signal and the second input signal, and at least the information based on being associated with the first input signal and the second input signal generates the first comparison signal, at least relevant with output current with the supply convertor feedback signal of the first input signal is associated.The method also comprises: at least receives the first comparison signal, processes the information be associated with the first comparison signal, and the Information generation modulation signal based on being associated with the first comparison signal at least, modulation signal is associated with modulating frequency.In addition, the method comprises: receive modulation signal, process the information being associated with modulation signal, and to regulate the primary current of the armature winding of the supply convertor of flowing through, the peak value size during primary current and modulating frequency corresponding each modulation period is associated to switch output drive signal.In addition, the method comprises: sampled feedback signal to be to generate for first during the first modulation period through sampled signal, and sampled feedback signal to be to generate for second during the second modulation period through sampled signal, and the second modulation period is after the first modulation period.In addition, the method comprises: judge that first deducts second through sampled signal and whether meet one or more first conditions through sampled signal, and if one or more first condition is satisfied, increase modulating frequency and the peak value size relevant with primary current.For example, the method at least realizes according to Figure 11, Figure 12, Figure 13, Figure 14, Figure 15, Figure 16 and/or Figure 17.

According to another embodiment, a kind of system for switching power converters comprises the first comparator, pulse-width modulation maker, actuator assembly and voltage change rate detection components.The first comparator be configured to receive the first input signal and the second input signal and at least the information based on being associated with the first input signal and the second input signal generate the first comparison signal, at least relevant with output current with the supply convertor feedback signal of the first input signal is associated.Pulse-width modulation maker is configured at least receive the first comparison signal and the Information generation modulation signal based on being associated with the first comparison signal at least, and modulation signal is associated with modulating frequency.In addition, actuator assembly be configured to receive modulation signal and to switch output drive signal to regulate the primary current of the armature winding of the supply convertor of flowing through, the peak value size during primary current and modulating frequency corresponding each modulation period is associated.In addition, voltage change rate detection components be configured to sampled feedback signal with generate first during the first modulation period through sampled signal and sampled feedback signal with second during generating for the second modulation period through sampled signal, voltage change rate detection components is also configured to compare through sampled signal with second through the size of sampled signal first, and the second modulation period is after the first modulation period.This system is also configured to: judge that first deducts second through sampled signal and whether be greater than first threshold voltage through sampled signal, first threshold voltage is more than or equal to zero; If first deducts second through sampled signal, through sampled signal, be judged as and be greater than first threshold voltage, increase modulating frequency and the peak value size relevant with primary current.This system is also configured to: judge that second deducts first through sampled signal and whether be greater than Second Threshold voltage through sampled signal, Second Threshold voltage is more than or equal to zero; And if second deduct first through sampled signal and be judged as and be greater than Second Threshold voltage through sampled signal, reduce modulating frequency and the peak value size relevant with primary current.For example, this system at least realizes according to Figure 11, Figure 12, Figure 13, Figure 14, Figure 15, Figure 16 and/or Figure 17.

According to another embodiment, a kind of method for switching power converters comprises: receive the first input signal and the second input signal, process the information being associated with the first input signal and the second input signal, and at least the information based on being associated with the first input signal and the second input signal generates the first comparison signal, at least relevant with output current with the supply convertor feedback signal of the first input signal is associated.The method also comprises: at least receives the first comparison signal, processes the information be associated with the first comparison signal, and the Information generation modulation signal based on being associated with the first comparison signal at least, modulation signal is associated with modulating frequency.In addition, the method comprises reception modulation signal, process the information be associated with modulation signal, and to switch output drive signal with the flow through primary current of armature winding of supply convertor of adjusting, the peak value size during primary current and modulating frequency corresponding each modulation period is associated.In addition, the method comprises that sampled feedback signal is to generate for first during the first modulation period through sampled signal, and sampled feedback signal to be to generate for second during the second modulation period through sampled signal, and the second modulation period is after the first modulation period.In addition, the method comprises and judges that first deducts second through sampled signal and whether be greater than first threshold voltage through sampled signal, and first threshold voltage is more than or equal to zero; And if first deducts second through sampled signal, through sampled signal, be judged as and be greater than first threshold voltage, increase modulating frequency and the peak value size relevant with primary current.In addition, the method comprises and judges that second deducts first through sampled signal and whether be greater than Second Threshold voltage through sampled signal, and Second Threshold voltage is more than or equal to zero; And if second deducts first through sampled signal, through sampled signal, be judged as and be greater than Second Threshold voltage, reduce modulating frequency and the peak value size relevant with primary current.For example, the method at least realizes according to Figure 11, Figure 12, Figure 13, Figure 14, Figure 15, Figure 16 and/or Figure 17.

For example, the some or all of assemblies in each embodiment of the present invention individually and/or with another assembly at least combined be that one or more that utilize one or more component softwares, one or more nextport hardware component NextPort and/or software and nextport hardware component NextPort combine to realize.In another example, the some or all of assemblies in each embodiment of the present invention individually and/or with another assembly at least combined in one or more circuit, realize, for example in one or more analog circuits and/or one or more digital circuit, realize.In another example, each embodiment of the present invention and/or example can be combined.

Although described specific embodiment of the present invention, yet it will be apparent to one skilled in the art that other embodiment that existence and described embodiment are equal to.Therefore, will understand, the present invention is not limited to shown specific embodiment, but only by the scope of claim, is limited.

Claims (25)

1. A system for a switching power converter, the system comprising: A first comparator configured to receive a first input signal and a second input signal and generate a first comparison signal based at least on information associated with the first input signal and the second input signal, the first The input signal is associated with at least a feedback signal related to the output current of said power converter; a pulse width modulation generator configured to receive at least the first comparison signal and generate a modulation signal based on at least information associated with the first comparison signal, the modulation signal being associated with a modulation frequency; a driver component configured to receive the modulation signal and output a drive signal to a switch to regulate a primary current flowing through the primary winding of the power converter, the primary current being equal to the modulation frequency during each modulation period corresponding to the modulation frequency associated with the peak size of ; and a voltage change rate detection component configured to sample the feedback signal to generate a first sampled signal during a first modulation period and sample the feedback signal to generate a second sampled signal during a second modulation period, the voltage the rate-of-change detection component is further configured to compare the magnitude of the first sampled signal to the second sampled signal, the second modulation period following the first modulation period; Wherein, the system for switching power converter is also configured as: determining whether the first sampled signal minus the second sampled signal satisfies one or more first conditions; The modulation frequency and the peak magnitude related to the primary current are increased if the one or more first conditions are met. 2. The system of claim 1, further configured to determine that the first sampled signal minus the second sampled signal is greater than a first threshold voltage when the first sampled signal minus the second sampled signal is greater than a first threshold voltage. The second sampled signal satisfies the one or more first conditions, and the first threshold voltage is greater than or equal to zero. 3. The system of claim 1, further configured to: determining whether the second sampled signal minus the first sampled signal satisfies one or more second conditions; If the one or more second conditions are met, then reducing the modulation frequency and the peak magnitude related to the primary current. 4. The system of claim 3, further configured to determine that the second sampled signal minus the first sampled signal is greater than a second threshold voltage when the second sampled signal minus the first sampled signal is greater than a second threshold voltage. The first sampled signal satisfies the one or more second conditions, and the second threshold voltage is greater than or equal to zero. 5. The system of claim 3, further comprising: an index generator configured to generate the second input signal; and a dynamic control component coupled to the voltage rate-of-change detection component and configured to generate at least a third input signal and a fourth input signal; Wherein, the exponential generator is further configured to receive at least the third input signal, and in response change the second input signal to increase or decrease the modulation frequency. 6. The system of claim 5, further comprising: a logic control component configured to receive at least the fourth input signal, and in response, change a logic signal to increase or decrease said primary current related the peak size. 7. The system of claim 6, wherein the pulse width modulation generator is further configured to receive the logic signal and to determine based on at least information associated with the first comparison signal and the logic signal The modulated signal is generated. 8. The system of claim 1, wherein the second modulation period immediately follows the first modulation period. 9. The system of claim 1, further comprising: a second comparator configured to receive a third input signal and a fourth input signal and based at least on correlation with the third input signal and the fourth input signal The connected information generates a second comparison signal, the third input signal is related to the first input signal, and the fourth input signal is related to the primary current flowing through the primary winding of the power converter. 10. The system of claim 9, further comprising: a third comparator configured to receive the fourth input signal and the first threshold signal, and at least based on a relationship between the fourth input signal and the first information associated with the threshold signal to generate a third comparison signal; and A fourth comparator configured to receive the fourth input signal and the second threshold signal, and generate a fourth comparison signal based on at least information associated with the fourth input signal and the second threshold signal. 11. The system of claim 1, wherein the pulse width modulation generator comprises: a NAND gate configured to receive at least the first comparison signal; an AND gate coupled to the NAND gate; and A flip-flop component coupled to the AND gate and logic control component and configured to generate the modulated signal. 12. The system of claim 1, wherein the switch is a bipolar transistor. 13. The system of claim 1, wherein the switch is a MOS transistor. 14. The system of claim 1, further comprising: a current generator configured to receive the first comparison signal and output a compensation current based at least on information associated with the first comparison signal to generate a compensation voltage and adjust the first input signal. 15. The system of claim 1, wherein the voltage change rate detection component comprises: a first sample and hold circuit configured to sample the feedback signal to generate the first sampled signal during the first modulation period; a second sample and hold circuit configured to sample the feedback signal to generate the second sampled signal during the second modulation period; an operational amplifier configured to receive a third input signal and a fourth input signal having a magnitude proportional to the first sampled signal and generate a first output signal, the fourth input signal having a magnitude proportional to the second sampled signal, the first output signal represents the first sampled signal minus the second sampled signal; and A comparator configured to receive the first output signal and a third threshold voltage and generate a second comparison signal based on at least information associated with the first output signal and the third threshold voltage. 16. The system of claim 15, further comprising: a dynamic control component configured to receive at least the second comparison signal and generate at least a second output signal; a logic control component configured to receive at least said second output signal and in response alter a logic signal to increase or decrease said peak magnitude related to said primary current; Wherein, the pulse width modulation generator is further configured to receive the logic signal, and generate the modulation signal based at least on information associated with the first comparison signal and the logic signal. 17. The system of claim 15 , further configured to determine that the first sampled signal minus the second sampled signal satisfies the requirement when the first output signal is greater than the third threshold voltage. The one or more first conditions, the third threshold voltage is greater than or equal to zero. 18. The system of claim 1, wherein the voltage change rate detection component comprises: a first sample and hold circuit configured to sample the feedback signal to generate the first sampled signal during the first modulation period; a second sample and hold circuit configured to sample the feedback signal to generate the second sampled signal during the second modulation period; a voltage level shifting component configured to receive the first sampled signal and generate a first output signal having a magnitude equal to the first sampled signal minus a fourth threshold voltage; and A second comparator configured to receive the first output signal and the second sampled signal, and generate a second comparison signal. 19. The system of claim 18, further comprising: a dynamic control component configured to receive at least the second comparison signal and generate at least a second output signal; a logic control component configured to receive at least said second output signal and in response alter a logic signal to increase or decrease said peak magnitude related to said primary current; Wherein, the pulse width modulation generator is further configured to receive the logic signal, and generate the modulation signal based at least on information associated with the first comparison signal and the logic signal. 20. The system of claim 18, further configured to determine that the first sampled signal minus the second sampled signal satisfies when the first output signal is greater than the second sampled signal The one or more first conditions, the fourth threshold voltage is greater than or equal to zero. 21. A method for switching a power converter, the method comprising: receiving a first input signal and a second input signal; processing information associated with the first input signal and the second input signal; generating a first comparison signal based on at least information associated with the first input signal and the second input signal, the first input signal being associated with at least a feedback signal related to the output current of the power converter ; receiving at least the first comparison signal; processing information associated with the first comparison signal; generating a modulation signal based at least on information associated with the first comparison signal, the modulation signal being associated with a modulation frequency; receiving the modulated signal; processing information associated with the modulated signal, and generating a drive signal; outputting the drive signal to a switch to regulate a primary current flowing through a primary winding of the power converter, the primary current being associated with a peak magnitude during each modulation period corresponding to the modulation frequency; sampling the feedback signal to generate a first sampled signal during a first modulation period; sampling the feedback signal to generate a second sampled signal during a second modulation period, the second modulation period following the first modulation period; determining whether the first sampled signal minus the second sampled signal satisfies one or more first conditions; and The modulation frequency and the peak magnitude related to the primary current are increased if the one or more first conditions are met. 22. The method of claim 21, further comprising: determining whether the second sampled signal minus the first sampled signal satisfies one or more second conditions; If the one or more second conditions are met, then reducing the modulation frequency and the peak magnitude related to the primary current. 23. A system for switching power converters, the system comprising: A first comparator configured to receive a first input signal and a second input signal and generate a first comparison signal based at least on information associated with the first input signal and the second input signal, the first The input signal is associated with at least a feedback signal related to the output current of said power converter; a pulse width modulation generator configured to receive at least the first comparison signal and generate a modulation signal based on at least information associated with the first comparison signal, the modulation signal being associated with a modulation frequency; a driver component configured to receive the modulation signal and output a drive signal to a switch to regulate a primary current flowing through the primary winding of the power converter, the primary current being equal to the modulation frequency during each modulation period corresponding to the modulation frequency associated with the peak size of ; a voltage change rate detection component configured to sample the feedback signal to generate a first sampled signal during a first modulation period and sample the feedback signal to generate a second sampled signal during a second modulation period, the voltage the rate-of-change detection component is further configured to compare the magnitude of the first sampled signal to the second sampled signal, the second modulation period following the first modulation period; Wherein, the system for switching power converter is also configured as: determining whether the first sampled signal minus the second sampled signal is greater than a first threshold voltage, the first threshold voltage being greater than or equal to zero; increasing the modulation frequency and the peak magnitude related to the primary current if the first sampled signal minus the second sampled signal is determined to be greater than the first threshold voltage; determining whether the second sampled signal minus the first sampled signal is greater than a second threshold voltage, the second threshold voltage being greater than or equal to zero; and If the second sampled signal minus the first sampled signal is determined to be greater than the second threshold voltage, the modulation frequency and the peak magnitude related to the primary current are decreased. 24. The system of claim 23, further configured to: If the first sampled signal minus the second sampled signal is determined to be greater than the first threshold voltage, increasing the modulation frequency to a predetermined maximum frequency and increasing the peak magnitude to a predetermined maximum size; and If the second sampled signal minus the first sampled signal is determined to be greater than the second threshold voltage, then reduce the modulation frequency to a predetermined minimum frequency and reduce the peak magnitude to a predetermined minimum size. 25. A method for switching a power converter, the method comprising: receiving a first input signal and a second input signal; processing information associated with the first input signal and the second input signal; generating a first comparison signal based on at least information associated with the first input signal and the second input signal, the first input signal being associated with at least a feedback signal related to the output current of the power converter ; receiving at least the first comparison signal; processing information associated with the first comparison signal; generating a modulation signal based at least on information associated with the first comparison signal, the modulation signal being associated with a modulation frequency; receiving the modulated signal; processing information associated with the modulated signal, and generating a drive signal; outputting the drive signal to a switch to regulate a primary current flowing through a primary winding of the power converter, the primary current being associated with a peak magnitude during each modulation period corresponding to the modulation frequency; sampling the feedback signal to generate a first sampled signal during a first modulation period; sampling the feedback signal to generate a second sampled signal during a second modulation period, the second modulation period following the first modulation period; determining whether the first sampled signal minus the second sampled signal is greater than a first threshold voltage, the first threshold voltage being greater than or equal to zero; increasing the modulation frequency and the peak magnitude related to the primary current if the first sampled signal minus the second sampled signal is determined to be greater than the first threshold voltage; determining whether the second sampled signal minus the first sampled signal is greater than a second threshold voltage, the second threshold voltage being greater than or equal to zero; and If the second sampled signal minus the first sampled signal is determined to be greater than the second threshold voltage, the modulation frequency and the peak magnitude related to the primary current are decreased.

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