CN102916018B - The pad structure formed in dual openings in the dielectric layer - Google Patents
The pad structure formed in dual openings in the dielectric layer Download PDFInfo
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- CN102916018B CN102916018B CN201110350734.9A CN201110350734A CN102916018B CN 102916018 B CN102916018 B CN 102916018B CN 201110350734 A CN201110350734 A CN 201110350734A CN 102916018 B CN102916018 B CN 102916018B
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Abstract
A kind of image sensor devices includes: have the Semiconductor substrate of front and back；The first dielectric layer being positioned on Semiconductor substrate front；It is positioned at the metal pad in the first dielectric layer；It is positioned at the first dielectric layer and the second dielectric layer being positioned on Semiconductor substrate front；Penetrate the opening of Semiconductor substrate from the back side of Semiconductor substrate, wherein this opening includes Part I and Part II, and described Part I extends to expose a part of metal pad, and described Part II extends to expose a part of second dielectric layer；And in the Part I and Part II of opening formed metal level.Present invention also offers the pad structure formed in a kind of dual openings in the dielectric layer.
Description
Technical field
The present invention relates to pad structure, specifically, the present invention relates to the pad formed in dual openings
Structure.
Background technology
Back-illuminated type (BSI) image sensor chip due to its capture photon in terms of in hgher efficiency
Substitute frontlighting sensor chip.In the formation of BSI image sensor chip, at the silicon of wafer
Form imageing sensor and logic circuit on substrate, on the front of silicon, then form interconnection structure.
Interconnection structure includes that multiple metal level, the plurality of metal level include that bottom metal layer M1 is to top-level metallic
Layer Mtop.
Then wafer is turned.From the back side of silicon substrate, silicon substrate is implemented grinding back surface.Surplus
The back side of remaining silicon substrate can be formed above buffer oxide nitride layer, and formed the first opening with from
Buffer oxide nitride layer extends, and stops at shallow trench isolation (STI) pad, and this shallow trench pad is formed
In silicon substrate.Then the first open interior formed the second opening with further etching STI pad and
It is positioned at the interlayer dielectric layer (ILD) of the underface being etched part of STI pad, so that underlying metal
Metal pad in layer M1 comes out.Second opening is less than the first opening.Then at the first opening
With the second opening is formed aluminum bronze pad, and make the metal that aluminum bronze pad is electrically connected in metal level M1
Pad.Aluminum bronze pad may be used for engaging BSI chip.
Find that conventional connected structure is likely to occur film during ball shearing test and peels off.Bottom metal layer M1
In metal pad may be with following etching stopping layer layering, described metal pad connects with aluminum bronze pad
Close.Peel off that the cohesive that is likely due between metal pad and etching stopping layer is poor to be caused, erosion
Carve stop-layer generally to be formed by carborundum.
Summary of the invention
In order to solve problems of the prior art, according to an aspect of the invention, it is provided one
Plant image sensor devices, including: Semiconductor substrate, there is front and back；First dielectric layer,
It is positioned on the described front of described Semiconductor substrate；Metal pad, is positioned in described first dielectric layer；
Second dielectric layer, be positioned at described first dielectric layer and be positioned at described Semiconductor substrate described just
On face；Opening, penetrates described Semiconductor substrate from the described back side of described Semiconductor substrate, wherein,
Described opening includes Part I and Part II, and described Part I extends to expose a part described
Metal pad, described Part II extends to expose a part of described second dielectric layer；And metal level,
It is formed in described Part I and the described Part II of described opening.
In above-mentioned image sensor devices, wherein, described first dielectric layer is low k dielectric, with
And described second dielectric layer is non-low k dielectric.
In above-mentioned image sensor devices, farther including to isolate pad, described isolation pad is from institute
The described front stating Semiconductor substrate extends in described Semiconductor substrate, wherein said opening described
Part I penetrates a part of described isolation pad.
In above-mentioned image sensor devices, farther including adhesive layer, described adhesive layer is positioned at described
In the described Part I of opening and described Part II, wherein, described adhesive layer is formed at described gold
Belong between layer and the expose portion of described metal pad, and wherein, described adhesive layer is formed at described
Between the expose portion of metal level and described second dielectric layer.
In above-mentioned image sensor devices, wherein, described second dielectric layer includes unadulterated silicic acid
Salt glass (USG) layer.
In above-mentioned image sensor devices, wherein, described Part I and the institute of described opening it are positioned at
The described metal level stated in Part II is electrically connected to each other.
In above-mentioned image sensor devices, farther including projection, described projection is positioned at described opening
Described Part II in and be electrically connected to described metal pad by described metal level.
In above-mentioned image sensor devices, farther including passivation layer, described passivation layer is located at institute
State on metal level described in the part in the described Part I of opening.
According to a further aspect in the invention, additionally provide a kind of back side illumination image sensor device, including:
Semiconductor substrate；Shallow trench isolation (STI) pad, extends to institute from the front of described Semiconductor substrate
State in Semiconductor substrate；Low k dielectric, is positioned on the described front of described Semiconductor substrate；Gold
Belong to pad, be positioned in described low k dielectric；Non-low k dielectric, be positioned at described low k dielectric it
On；First opening, extends to from the back side of described Semiconductor substrate, described Semiconductor substrate, pass
Described STI pad also extends to expose a part of described metal pad；Second opening, partly leads from described
The described back side of body substrate extends in described Semiconductor substrate, through described low k dielectric and extend
To expose a part of described non-low k dielectric；And metal level, it is formed in described first opening,
And continuously extending to described second opening, wherein said metal level is electrically connected to described metal pad.
In above-mentioned back side illumination image sensor device, farther include adhesive layer, described adhesive layer position
In described first opening and continuously extend to described second opening, wherein, described adhesive layer is formed at
Between the expose portion of described metal level and described metal pad, and described adhesive layer is formed at described
Between the expose portion of metal level and described non-low k dielectric.
In above-mentioned back side illumination image sensor device, wherein, described metal pad comprises copper.
In above-mentioned back side illumination image sensor device, farther including projection, described projection is positioned at institute
State in the second opening and be electrically connected to described metal pad by described metal level.
In above-mentioned back side illumination image sensor device, farther include multiple low k dielectric, described
Multiple low k dielectrics are between described low k dielectric and described non-low k dielectric.
In above-mentioned back side illumination image sensor device, farther include imageing sensor, described image
Sensor is arranged on the described front of described Semiconductor substrate.
According to another aspect of the invention, additionally provide a kind of method, including: in Semiconductor substrate
Imageing sensor and isolation pad is formed on front；On the described front being positioned at described Semiconductor substrate
Described imageing sensor and the top of described isolation pad form multiple first dielectric layer, wherein in institute
State and one of multiple first dielectric layer is formed metal pad；Be positioned at described Semiconductor substrate described just
The plurality of first dielectric layer on face forms the second dielectric layer；The back of the body from described Semiconductor substrate
Face forms the first opening with through described isolation pad and expose a part of described metal pad；From described
The described back side of Semiconductor substrate forms the second opening with through described isolation pad and the plurality of first
Dielectric layer also exposes a part of described second dielectric layer；And open at described first opening and described second
Form metal level in Kou, wherein, described metal level is electrically connected to described metal pad.
In the above-mentioned methods, farther include: before forming described metal level, open described first
Mouthful and described second opening in form adhesive layer, wherein, described metal level and described metal pad it
Between form described adhesive layer, and wherein, in described metal level and the exposed portion of described second dielectric layer
/ described adhesive layer of formation.
In the above-mentioned methods, farther include: implement lead-in wire and engage to form projection, described projection position
It is electrically connected to described metal pad in described second opening and by described metal level.
In the above-mentioned methods, farther include: formed on described metal level in described first opening
Passivation layer.
In the above-mentioned methods, the step wherein forming described first opening includes: serve as a contrast from described quasiconductor
Semiconductor substrate described in the described back etched at the end is to expose a part of described isolation pad；Described half
Buffer oxide nitride layer is formed on the described back side of conductor substrate and the expose portion of described isolation pad；With
And etch described buffer oxide nitride layer and the expose portion of described isolation pad.
In the above-mentioned methods, wherein said first opening and described second opening are continuously connected to one another.
Accompanying drawing explanation
In order to be more fully understood by embodiment and advantage thereof, the following description work that accompanying drawing is carried out will be combined now
For reference, wherein:
Fig. 1 to Fig. 6 is in manufacture back-illuminated type (BSI) image sensor chip according to each embodiment
The profile in interstage of bond pad structure；And
Fig. 7 shows the top view of a part for the structure shown in Fig. 6.
Detailed description of the invention
The manufacture of the embodiment of the present invention described in detail below and use.It should be appreciated, however, that embodiment carries
Many applicable concepts that can realize in various specific environments are supplied.The specific embodiment discussed is only
It is only exemplary, rather than limits the scope of the present invention.
The pad structure for back-illuminated type (BSI) image sensor devices is provided according to each embodiment
And forming method thereof.Show the interstage forming BSI pad structure.Discuss the change of embodiment
Body.Running through each view and exemplary embodiment, identical Ref. No. is for indicating identical element.
Fig. 1 to Fig. 6 shows the section in the interstage manufacturing pad structure according to some embodiments
Figure.Fig. 1 shows that image sensor chip 20, image sensor chip 20 can be wafers 22
A part.Image sensor chip 20 includes that Semiconductor substrate 26, Semiconductor substrate 26 can be brilliant
Body silicon substrate or the Semiconductor substrate formed by other semi-conducting materials.Throughout the specification, face
26A is referred to as the front of Semiconductor substrate 26, and face 26B is referred to as the back side of Semiconductor substrate 26.
At the image forming surface sensor 24 of Semiconductor substrate 26, imageing sensor 24 can be photosensitive
MOS transistor or light sensitive diode.Therefore, wafer 22 can be imageing sensor wafer.?
In entire disclosure, the face at imageing sensor 24 place is referred to as the front of Semiconductor substrate 26, and
Opposing face is referred to as the back side of Semiconductor substrate 26.Dielectric pad 36, can be that shallow trench isolates (STI)
Pad, extends to Semiconductor substrate 26 from the end face (it is front 26A) of Semiconductor substrate 26.
Interconnection structure 28 is formed at the top of Semiconductor substrate 26, and is used for imageing sensor is electrically interconnected
Device in chip 20.Interconnection structure 28 is included in the interlayer dielectric formed above Semiconductor substrate 26
Layer (ILD) 25, wherein can form contact plug (not shown) in ILD25.Metal level bag
Include the metal wire/pad 32 and through hole 34 being positioned in dielectric layer 30.Imageing sensor 24 can be electrically connected
Metal pad/the line 32 being connected in metal level M1 to Mtop and through hole 34.
Metal level is labeled as M1, M2...... and Mtop, and wherein metal level M1 is interconnection structure 28
Bottom metal layer, and metal level Mtop is the top layer metallic layer of interconnection structure 28.In the reality illustrated
Execute in example, have 4 layers of metal level, and metal level Mtop is M4.But, wafer 22 can wrap
Include more or less metal level.In an embodiment, metal level M1 to M (top-1) is wherein formed
Metal wire 32 and the dielectric layer 30 of through hole 34 be low k dielectric, this low k dielectric has low k
Value, for example, less than about 3.0.Wherein form the metal wire 32 of top layer metallic layer Mtop and through hole 34
Dielectric layer 31, is formed by non-low k dielectric, this non-low k dielectric have more than 3.9 or
The k value of greater than about 4.5.In an embodiment, dielectric layer 31 is by the most unadulterated glassy silicate of oxide
Glass (USG), borosilicate glass (BSG), the silicate glass (PSG) of phosphorus doping or boron
The phosphosilicate glass (BPSG) of doping etc. are formed.
Passivation layer 38 is formed above top layer metallic layer Mtop.Passivation layer 38 can be more than by k value
The non-low k dielectric of 3.9 is formed.In an embodiment, passivation layer 38 is by silicon oxide layer and silicon oxide
On layer, silicon nitride layer is formed.
With reference to Fig. 2, wafer 22 is turned, and is connected to be positioned at the carrier below wafer 22 (not
Illustrate).Therefore, the end face of each such as the parts in Fig. 1 becomes bottom surface, and vice versa.Half
Conductor substrate 26 faces up.Enforcement grinding back surface is with thinning Semiconductor substrate 26, until such as wafer
The thickness of 22 is less than about 20 μm, or less than about 10 μm.The back of the body to the Semiconductor substrate 26 obtained
Face 26B is marked.Under this thickness, light can be from the back side (itself and the front of Semiconductor substrate 26
On the contrary) penetrate remaining Semiconductor substrate 26, and arrive imageing sensor 24.After thinning step,
Buffer oxide nitride layer 40 can be formed on the surface of Semiconductor substrate 26.In an embodiment, buffering
Oxide skin(coating) 40 includes silicon oxide layer, is positioned at the bottom antireflective coating (BARC) above silicon oxide layer
Layer, and it is positioned at another oxide skin(coating) above BARC layer, but cushion 40 can also have not
Same structure is also formed by different materials.
With reference to Fig. 3, it is etched forming opening to buffer oxide nitride layer 40 and Semiconductor substrate 26
41.In an etching step, STI pad 36 is used as etching stopping layer, and the bottom of opening 41 is stopped
On STI pad 36.Then, metallic shield 42 is formed.In an embodiment, metallic shield 42
Formation includes forming metal level, then patterned metal layer, so that metallic shield 42 is retained in part half
The top of conductor substrate 26, thus metallic shield 42 can stop light arrive device 27 (such as transistor,
Not shown) it is positioned at the part immediately below metallic shield 42.Metallic shield 42 can comprise aluminum and/or copper.
After forming metallic shield 42, form buffer oxide nitride layer 44.Buffer oxide nitride layer 44 can be by
The material similar to the material of buffer oxide nitride layer 40 is formed.Buffer oxide nitride layer 44 includes being positioned at half
Part I directly over conductor substrate 26, and extend to the Part II in opening 41.Second
Part farther includes the part being positioned on Semiconductor substrate 26 sidewall, and is positioned at STI pad 36
The part of surface.
It follows that as shown in Figure 4, form and pattern photoresist 46, and make with photoresist 46
As mask etching STI pad 36.Therefore, opening 48, and the bottom 48A of opening 48 are formed
It is bonded on metal pad 32A.During etching step, etch STI pad 36 and ILD 25 2
Person, and stop etching on metal pad 32A.In an embodiment, metal pad 32A is positioned at the end
In layer metal level M1, but it can also be positioned in other metal levels such as metal level M2 and M3.Knot
Really, metal pad 32A is exposed to opening 48.Then photoresist 46 is removed.
With reference to Fig. 5, form and pattern photoresist 50, and form opening 52.During etching, erosion
Cut through multiple low k dielectric 30, and flushing with the end face 31A of non-low k dielectric 31 or
Person's horizontal plane less than end face 31A stops etching.Therefore, the bottom surface 52A of opening 52 and quasiconductor
Vertical dimension V2 between substrate 26 is more than between bottom surface 48A and the Semiconductor substrate 26 of opening 48
Vertical dimension V1, and therefore bottom surface 52A than bottom surface 48A further from Semiconductor substrate 26.In reality
Execute in example, can stop etching when non-low k dielectric 31 is exposed to opening 52, and opening 52
Bottom surface 52A flush with the end face of non-low k dielectric 31.The corresponding end according to embodiment opening 52
Face 52A uses dotted line 53 to illustrate.Due to the side effect of over etching, the bottom of opening 52 can also
It is parked in the intermediate layer between the end face 31A and bottom surface 31B of non-low k dielectric 31.Optional real
Executing in example, the bottom of opening 52 can also flush or low with the bottom surface 31B of non-low k dielectric 31
Bottom surface 31B in non-low k dielectric 31.Therefore, during opening 52 can extend to layer 38.Etching
After step, remove photoresist 50.Notice, in order to illustrate the concrete structure in metal level, it is shown that
The aspect ratio of opening 52 more much bigger than the aspect ratio of actual aperture formed on entity wafer.Actual
The horizontal size that opening has can be noticeably greater than the height of opening 52, is the height of opening 52 sometimes
10 times.In the structure obtained, opening 41 (Fig. 3), opening 48 (Fig. 4) and opening 52
Form continuous print opening.
Fig. 6 shows adhesive layer 54 (it is also barrier layer) and the formation of metal level 56 and patterning.
Formation process includes depositing (conformal) adhesive layer, in adhesive layer disposed thereon metal welding disc layer and scheme
Case adhesive layer and metal welding disc layer are to form the structure shown in Fig. 6.Adhesive layer 54 can by tantalum,
Tantalum nitride, titanium or titanium nitride etc. are formed.Metal level 56 can by containing aluminum metal material (such as its
Can be aluminum bronze) formed, but other metals and metal alloy can also be used.
Fig. 6 also show the formation of passivation layer 62, and passivation layer 62 is formed by dielectric material.Implementing
In example, passivation layer 62 includes silicon oxide layer and is positioned at the nitride layer above silicon oxide layer, but its
Can also be formed by other dielectric material such as USG.Patterned passivation layer 62, so that metal level 56 exists
Part in opening 52 comes out, simultaneously the metal level 56 part in opening 48 and metal level
56 parts directly over metallic shield 42 are passivated layer 62 and cover.Can also be from imageing sensor 24
Directly over remove passivation layer 62 so that can the surface of imageing sensor 24 formed color filter and
Lens (not shown).Therefore, light (representing with the arrow 68 of bending) can penetrate buffer oxide
Layer 40 and 44 and Semiconductor substrate 26 arrive imageing sensor 24, imageing sensor 24 is configured
For converting the light to the signal of telecommunication.
Fig. 7 shows the top view of a part for the structure shown in Fig. 6.It shows opening 48 He
In 52 borders being formed at opening 41.It is each that STI pad 36 includes in the opening 48 and 52
Individual part.
Referring back to Fig. 6, in an embodiment, implement lead-in wire and engage to form lead-in wire engagement protrusion 64,
Lead-in wire engagement protrusion 64 is engaged to the bond pad formed by metal level 56.Lead-in wire engagement protrusion 64
Gold or aluminum etc. can be comprised.Can implement to draw after wafer 22 is cut into image sensor chip
Wire bonding.In the structure obtained, lead-in wire engagement protrusion 64 is electrically connected to metal pad 32A, will
Metal pad 32A is further electrically coupled to other devices such as imageing sensor 24 and/or is positioned at metal screen
Cover the device 27 immediately below 42.
In an embodiment, each in adhesive layer 54 and metal level 56 includes three parts, bag
The Part II include the Part I being positioned in opening 48, being positioned in opening 52 and interconnection first
Part and the Part III of Part II.Part I is illustrated schematically as online 102 and 104 it
Between labelling region in.Part II is illustrated schematically as the district of labelling between online 106 and 108
In territory.Part III is illustrated schematically as between online 104 and 106 in the region of labelling.Bonding
The layer Part I of 54 and the Part I of metal level 56 are formed with metal pad 32A and electrically connect.Viscous
The Part II of the Part II and metal level 56 that close layer 54 forms the bond pad for engaging.The
Three parts serve as the electrical connector between the first and second parts.Because implementing to engage to Part II,
Part II is engaged on non-low k dielectric such as non-low k dielectric 31, so reducing film layering
Probability.Adhesive layer 54 has good gluing to metal level 56 and non-low k dielectric 31 both of which
Conjunction property, and adhesive layer 54 and lead-in wire engagement protrusion above and the stripping of non-low k dielectric 31 can
Energy property is less.On the other hand, it is electrically connected yet by metal pad 32A.
According to embodiment, image sensor devices includes the Semiconductor substrate with front and back；Position
The first dielectric layer on Semiconductor substrate front；It is positioned at the metal pad in the first dielectric layer；It is positioned at
First dielectric layer and the second dielectric layer being positioned on Semiconductor substrate front；From Semiconductor substrate
The back side penetrate the opening of Semiconductor substrate, wherein this opening includes Part I and Part II, institute
Stating Part I to extend to expose a part of metal pad, described Part II extends to expose a part
Second dielectric layer；And in the Part I and Part II of opening formed metal level.
According to other embodiments, back side illumination image sensor device includes Semiconductor substrate；From quasiconductor
The front of substrate extends to the STI pad in Semiconductor substrate；It is positioned on the front of Semiconductor substrate
Low k dielectric；The metal pad being arranged in low k dielectric；It is positioned on low k dielectric
Non-low k dielectric；Extend to Semiconductor substrate from the back side of Semiconductor substrate, through STI pad
And extend to expose the first opening of a part of metal pad；Half is extended to from the back side of Semiconductor substrate
In conductor substrate, through low k dielectric and extend to expose the second of a part of non-low k dielectric and open
Mouthful；And formed in the first opening, and continuously extend to the metal level of the second opening, wherein by gold
Belong to layer and be electrically connected to metal pad.
According to other embodiment, a kind of method includes: form image on the front of Semiconductor substrate
Sensor and isolation pad；Multiple first dielectric layer is formed above imageing sensor and isolation pad；
Metal pad is formed in one of multiple first dielectric layers；Second is formed at multiple first dielectric layer
Dielectric layer；Form the first opening to extend from the back side of Semiconductor substrate with through isolating pad and exposing
A part of metal pad；The second opening is formed with through isolating pad with many from the back side of Semiconductor substrate
Individual first dielectric layer also exposes a part of second dielectric layer；And in the first opening and the second opening shape
Become metal level, wherein metal level is electrically connected to metal pad.
Although the embodiment of having describe in detail and advantage thereof, it is to be understood that can be without departing substantially from appended
Claim limit embodiment spirit and scope in the case of, carry out various different change, replacement and
Change.And, scope of the present application be not limited in the technique described in this specification, machine, manufacture,
Material component, device, the specific embodiment of method and steps.As those of ordinary skill in the art from this
It can be readily appreciated that existing or the technique of Future Development, machine, system can be utilized according to the present invention in bright
Make, material component, device, method or step, for performing and corresponding embodiment substantially phase described herein
With function or obtain substantially the same result.Therefore, claims are it is contemplated that include in the range of it
Such technique, machine, manufacture, material component, device, method or step.Additionally, every right is wanted
Seek the single embodiment of composition, and the combination of multiple claim and embodiment is within the scope of the invention.
Claims (13)
1. an image sensor devices, including:
Semiconductor substrate, has front and back；
For the first dielectric layer of low k dielectric, it is positioned on the described front of described Semiconductor substrate；
Metal pad, is positioned in described first dielectric layer；
For the second dielectric layer of non-low k dielectric, it is positioned at described first dielectric layer and is positioned at institute
State on the described front of Semiconductor substrate；
Opening, penetrates described Semiconductor substrate, wherein, institute from the described back side of described Semiconductor substrate
Stating opening and include Part I and Part II, described Part I extends to expose a part of described gold
Belonging to pad, described Part II extends to expose a part of described second dielectric layer；
Metal level, is formed in described Part I and the described Part II of described opening；
Adhesive layer, described adhesive layer is positioned in described Part I and the described Part II of described opening,
Wherein, described adhesive layer is formed between the expose portion of described metal level and described metal pad, and
And wherein, described adhesive layer is formed between the expose portion of described metal level and described second dielectric layer；
And
Projection, described projection is positioned in the described Part II of described opening and by described metal level electricity
It is connected to described metal pad.
Image sensor devices the most according to claim 1, farther includes to isolate pad, institute
State isolation pad and extend to described Semiconductor substrate from the described front of described Semiconductor substrate, wherein
The described Part I of described opening penetrates a part of described isolation pad.
Image sensor devices the most according to claim 1, wherein, described second dielectric layer bag
Include unadulterated silicate glass (USG) layer.
Image sensor devices the most according to claim 1, wherein, is positioned at the institute of described opening
The described metal level stated in Part I and described Part II is electrically connected to each other.
Image sensor devices the most according to claim 1, farther includes passivation layer, described
Passivation layer is located on metal level described in the part in the described Part I of described opening.
6. a back side illumination image sensor device, including:
Semiconductor substrate；
Shallow trench isolation pad, extends to described Semiconductor substrate from the front of described Semiconductor substrate；
Low k dielectric, is positioned on the described front of described Semiconductor substrate；
Metal pad, is positioned in described low k dielectric；
Non-low k dielectric, is positioned on described low k dielectric；
First opening, extends to from the back side of described Semiconductor substrate, described Semiconductor substrate, pass
Described shallow trench isolation pad also extends to expose a part of described metal pad；
Second opening, extends to described Semiconductor substrate from the described back side of described Semiconductor substrate,
Through described low k dielectric and extend to expose a part of described non-low k dielectric；
Metal level, is formed in described first opening, and continuously extends to described second opening, wherein
Described metal level is electrically connected to described metal pad；
Adhesive layer, described adhesive layer is positioned in described first opening and continuously extends to described second opening,
Wherein, described adhesive layer is formed between the expose portion of described metal level and described metal pad, and
And described adhesive layer is formed between the expose portion of described metal level and described non-low k dielectric；With
And
Projection, described projection is positioned in described second opening and is electrically connected to by described metal level described
Metal pad.
Back side illumination image sensor device the most according to claim 6, wherein, described metal welding
Dish comprises copper.
Back side illumination image sensor device the most according to claim 6, farther includes multiple low
K dielectric layer, the plurality of low k dielectric is positioned at described low k dielectric and described non-low k dielectric
Between.
Back side illumination image sensor device the most according to claim 6, farther includes image and passes
Sensor, described imageing sensor is arranged on the described front of described Semiconductor substrate.
10. the method forming back side illumination image sensor device, including:
The front of Semiconductor substrate is formed imageing sensor and isolation pad；
Described imageing sensor on the described front being positioned at described Semiconductor substrate and described isolation weldering
The top of dish is formed as multiple first dielectric layers of low k dielectric, wherein in the plurality of first dielectric
One of layer is formed metal pad；
The plurality of first dielectric layer on the described front being positioned at described Semiconductor substrate is formed
The second dielectric layer for non-low k dielectric；
The first opening is formed with through described isolation pad and expose one from the back side of described Semiconductor substrate
The described metal pad of part；
The second opening is formed with through described isolation pad and institute from the described back side of described Semiconductor substrate
State multiple first dielectric layer and expose a part of described second dielectric layer；And
Metal level is formed, wherein, by described metal level in described first opening and described second opening
It is electrically connected to described metal pad,
Wherein, before forming described metal level, shape in described first opening and described second opening
Become adhesive layer, wherein, between described metal level and described metal pad, form described adhesive layer, and
And wherein, between the expose portion of described metal level and described second dielectric layer, form described adhesive layer；
Farther include: implementing lead-in wire and engage to form projection, described projection is positioned at described second opening
In and be electrically connected to described metal pad by described metal level.
The method of 11. formation back side illumination image sensor devices according to claim 10, enters one
Step includes: form passivation layer in described first opening on described metal level.
The method of 12. formation back side illumination image sensor devices according to claim 10, wherein
The step forming described first opening includes:
Described to expose a part from Semiconductor substrate described in the described back etched of described Semiconductor substrate
Isolation pad；
The expose portion of the described back side of described Semiconductor substrate and described isolation pad is formed buffering
Oxide skin(coating)；And
Etch described buffer oxide nitride layer and the expose portion of described isolation pad.
The method of 13. formation back side illumination image sensor devices according to claim 10, wherein
Described first opening and described second opening are continuously connected to one another by described metal level.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/198,057 | 2011-08-04 | ||
| US13/198,057 US8987855B2 (en) | 2011-08-04 | 2011-08-04 | Pad structures formed in double openings in dielectric layers |
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| Publication Number | Publication Date |
|---|---|
| CN102916018A CN102916018A (en) | 2013-02-06 |
| CN102916018B true CN102916018B (en) | 2016-12-14 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101840925A (en) * | 2009-03-19 | 2010-09-22 | 索尼公司 | Semiconductor device and manufacture method thereof and electronic equipment |
| CN102054849A (en) * | 2009-10-29 | 2011-05-11 | 索尼公司 | Semiconductor device, manufacturing method thereof, and electronic apparatus |
| CN102110700A (en) * | 2009-12-25 | 2011-06-29 | 索尼公司 | Semiconductor device and method of manufacturing the same, and electronic apparatus |
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101840925A (en) * | 2009-03-19 | 2010-09-22 | 索尼公司 | Semiconductor device and manufacture method thereof and electronic equipment |
| CN102054849A (en) * | 2009-10-29 | 2011-05-11 | 索尼公司 | Semiconductor device, manufacturing method thereof, and electronic apparatus |
| CN102110700A (en) * | 2009-12-25 | 2011-06-29 | 索尼公司 | Semiconductor device and method of manufacturing the same, and electronic apparatus |
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