CN102904576A - Successive approximation tuning analog to digital conversion (ADC) circuit with variable quantification range - Google Patents

Abstract

The invention discloses a successive approximation tuning analog to digital conversion (ADC) circuit with a variable quantification range. A method comprises the following steps of: providing various pulse sequence signals with various pulse widths, wherein the pulse widths of the pulse sequence signals are gradually reduced; providing a pull-up current source and a pull-down current source, wherein the pull-up current source is used for providing constant charging current, and the pull-down current source is used for providing constant discharging current; providing a capacitor for storing charging charges and discharging charges to form reference voltage; providing a resetting signal, wherein resetting of the resetting signal is ineffective unless the resetting signal is positioned behind a first pulse of the pulse sequence signal; providing a resetting circuit for discharging the charges stored in the capacitor according to the resetting signal; providing a comparator for comparing input voltage and the reference voltage; providing a sampling trigger signal, wherein a triggering edge of the sampling trigger signal is positioned between pulse sequence intervals of the pulse sequence signals; and providing a sampling circuit for sampling a comparison result of the comparator according to the sampling trigger signal, and providing a charging and discharging control circuit for controlling the charging current and the discharging current according to the pulse sequence signals and an output signal of the sampling circuit.

Description

A kind of quantizing range is variable approaches tuning adc circuit one by one

Technical field

The present invention is mainly concerned with voltage in the broadcast receiver system to the conversion circuit design field of FREQUENCY CONTROL code, refer in particular to a kind of quantizing range variable approach one by one tuning adc circuit.

Background technology

In the broadcast receiver system based on DSP, the analog voltage that channel is listened in control need to be converted into corresponding digital code and just can process, and aanalogvoltage to the transferring structure block diagram of digital code as shown in Figure 1.It is ADC that analog voltage is converted into the common circuit that adopts of digital code, and tuning ADC in the broadcast receiver system is referred to as tuning ADC for this special applications.In the ADC of the various structures of routine, its basic function can both satisfy the requirement of tuning ADC, but the difference that still exists some specific performances to require.In the broadcast receiver system, tuning adc circuit is not positioned on the signal link of core, so wish that usually modern valency is more low better in fact; It is not high to the accuracy requirement of the conversion of digital code to aanalogvoltage, and the digital code in order to respective frequencies point that only need to produce enough numbers gets final product, and namely tuning ADC is very low to the requirement of the linearity; The common battery of the power supply of broadcast receiver system provides, so can change along with the decline of supply voltage in order to tuning aanalogvoltage, this just requires the quantizing range of tuning ADC to change.

Therefore, the tuning ADC that is applied to the broadcast receiver system needs a kind of special structure, and modern valency is low as far as possible in fact, and quantizing range is variable.

Summary of the invention

In one embodiment of the invention, a kind of method comprises the pulse sequence signal that multiple pulsewidth is provided, and the pulsewidth of pulse sequence signal is successively decreased successively.Pull-up current source and the pull-down current source of providing is provided the method, and the pull-up current source is in order to provide constant charging current, and the pull-down current source is in order to provide constant discharging current.The method comprises provides electric capacity, discharges and recharges electric charge in order to storage and forms reference voltage.The method comprises provides reset signal, and resetting of reset signal effectively must be positioned at before first pulse of pulse sequence signal.The method comprises provides reset circuit, according to reset signal the electric charge of storing in the electric capacity is released.The method comprises provides comparator, in order to compare input voltage and reference voltage.The method comprises provides sampling trigger signal, and the triggering of sampling trigger signal is along between the pulse sequence interval of pulse sequence signal.The method also comprises provides sample circuit, to the maintenance of sampling of the comparative result of comparator, and provides charge-discharge control circuit according to sampling trigger signal, controls charging and discharging currents according to the output signal of pulse sequence signal and sample circuit.

To understand advantage of the present invention and further feature from following accompanying drawing with describing.

Description of drawings

Fig. 1 is the tuning schematic diagram of aanalogvoltage in the broadcast receiver system;

Fig. 2 be quantizing range according to an embodiment of the invention variable approach one by one tuning adc circuit block diagram;

Fig. 3 is the working waveform figure schematic diagram of tuning ADC;

Embodiment

The invention will be further described below with reference to accompanying drawing and implementation.

With reference to Fig. 2, charging current source 201 equates with the electric current in discharging current source 202, supposes that its current value is I.When charge-discharge control circuit is high at D_OUT, electric capacity is charged, on the contrary then to capacitor discharge, wherein D_OUT is the comparative result of last comparator.The appearance value of supposing electric capacity is C.The expression formula that can obtain reference voltage 207 according to the parameter of supposing is:

$V_i=\underset{k=N-1}{\overset{i}{\mathrm{\Σ}}}{(-1)}^a\frac{1}{C}{\∫}_0^{2^{K}T}\mathrm{Idt}$

Wherein i represents the corresponding position of the digital code of tuning ADC, is N-1～0 for its span of tuning ADC of N position, V _iThe reference voltage level that represents the i position, a are the add-subtract control parameter, and as D_OUT when being high, a is 0, and then a is that 1, T is the narrowest pulse duration on the contrary, i.e. the width of last pulse in the pulse train.

Comparator 205 comparison reference voltage 207 and input voltage VIN, obtain the result of corresponding positions, the output of sampling of the comparative result of 206 pairs of comparators of sample circuit, obtaining the N digit numeric code of serial, is that simply to go here and there the N that turns and just can obtain tuning ADC output be digital code to digital code with the N of serial.

To further specify its course of work with reference to figure 3 in conjunction with Fig. 2.The quantizing range of supposing this tuning ADC is 1V, and according to the reference voltage generation order of tuning ADC, reference voltage should be 0.5V for the first time.The waveform of supposing again input voltage VIN is 301, and the value of input voltage is 0.7V, and calculating for the first time, reference voltage is:

$V_{N-1}=2^{N-1}T\frac{I}{C}=0.5V,$

The value that is waveform 302 correspondences is 0.5V, and the digital code that relatively obtains the N-1 position with reference to voltage and input voltage is 1, calculates secondary reference voltage according to the result of N-1 position to be:

$V_{N-2}=2^{N-1}T\frac{I}{C}+2^{N-2}T\frac{I}{C}=1.5\left(2^{N-1}T\frac{I}{C}\right)=0.75V$

The value that is waveform 303 correspondences is 0.75V, and the digital code that relatively obtains the N-2 position with reference to voltage and input voltage is 0, and the reference voltage that calculates for the third time according to the result of N-2 position is:

$V_{N-3}=2^{N-1}T\frac{I}{C}+2^{N-2}T\frac{I}{C}-2^{N-3}T\frac{I}{C}=1.25\left(2^{N-1}T\frac{I}{C}\right)=0.625V$

The value that is waveform 304 correspondences is 0.625V, and the digital code that relatively obtains the N-3 position with reference to voltage and input voltage is 1, continues the numeric results that above-mentioned steps can obtain the tuning ADC of N position.

According to above-mentioned analysis, the ceiling voltage that this tuning ADC quantizes is

By adjusting the value of T, can realize the adjustment to the quantizing range of tuning ADC.

Claims (10)

1. method comprises:

The pulse sequence signal of multiple pulsewidth is provided, and the pulsewidth of described pulse sequence signal is successively decreased successively;

Pull-up current source and pull-down current source are provided, and described pull-up current source is in order to provide constant charging current, and described pull-down current source is in order to provide constant discharging current;

Electric capacity is provided, discharges and recharges electric charge in order to storage and form reference voltage;

Reset signal is provided, and resetting of described reset signal effectively must be positioned at before first pulse of pulse sequence signal;

Reset circuit is provided, according to reset signal the electric charge of storing in the electric capacity is released;

Provide comparator, in order to compare input voltage and reference voltage;

Sampling trigger signal is provided, and the triggering of described sampling trigger signal is along between the pulse sequence interval of pulse sequence signal;

Sample circuit is provided, described sample circuit according to sampling trigger signal to the maintenance of sampling of the comparative result of comparator;

Charge-discharge control circuit is provided, and described charge-discharge control circuit is controlled charging and discharging currents according to the output signal of pulse sequence signal and sample circuit.

2. the method for claim 1, the pulse duration of wherein said pulse train satisfies formula: 2KT, wherein K is the integer between the N-1 to 0, comprises that N-1 and 0, N are the bit wide of ADC, T is minimum pulse width; Adjust the quantizing range of ADC by adjusting minimum pulse width T.

3. the method for claim 1, wherein said charge-discharge control circuit is controlled the time that discharges and recharges according to the pulse duration of pulse sequence signal, and judging according to the output signal of sample circuit should charge or discharge.

4. the method for claim 1, charge-discharge control circuit produces the reference voltage that comparator compares next time by control to discharging and recharging of electric capacity, and the generation order of its reference voltage is identical with the reference voltage generation order of common successive approximation analog to digital C.

5. method as claimed in claim 3, charging and discharging currents size wherein is subjected to the control in pull-up current source and pull-down current source; Pull-up current source wherein and the electric current in pull-down current source equate.

6. the method for claim 1, the output signal of wherein said sample circuit is the Output rusults of the N position ADC of serial.

7. a quantizing range is variable approaches tuning adc circuit one by one, comprising:

Pull-up current source and pull-down current source, described pull-up current source provides constant charge current, and described pull-down current source provides constant discharging current;

Electric capacity, storage discharges and recharges electric charge and forms reference voltage;

Reset circuit, the electric charge of storing in the electric capacity of releasing;

Comparator, more described reference voltage and input voltage;

Sample circuit, the Output rusults of sampling comparator is to provide the output of tuning ADC;

Charge-discharge control circuit, received pulse sequence signal, and being applicable to: determine time of charging and discharging currents according to the pulse duration of pulse sequence signal, judging according to the comparative result of comparator last time should charge or discharge.

8. circuit as claimed in claim 7, wherein said charge-discharge control circuit comprises charging control circuit and charge/discharge control circuit.

9. circuit as claimed in claim 8, wherein said charging control circuit comprises a charge switch and charge switch control logic, charge/discharge control circuit comprises a discharge switch and discharge switch control logic, the charge switch control logic is opposite with the discharge switch control logic, only carries out charge or discharge at synchronization.

10. circuit as claimed in claim 7, wherein said charge-discharge control circuit obtains the reference voltage of comparator by control to discharging and recharging of electric capacity, and the generation order of its reference voltage is identical with the reference voltage generation order of common successive approximation analog to digital C.

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