CN102891104B - A kind of method improving Cu CMP efficiency - Google Patents
A kind of method improving Cu CMP efficiency Download PDFInfo
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- CN102891104B CN102891104B CN201210341662.6A CN201210341662A CN102891104B CN 102891104 B CN102891104 B CN 102891104B CN 201210341662 A CN201210341662 A CN 201210341662A CN 102891104 B CN102891104 B CN 102891104B
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Abstract
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of method improving Cu CMP efficiency.The present invention proposes a kind of method improving Cu CMP efficiency, by carrying out electrolytic treatments to the copper film formed after plated metal copper, removal part copper film that can be controlled, to meet Cu CMP demand, thus simplify Cu CMP grinding technics step, reduce the Cu CMP time, save grinding cost, improve output capacity, the technological effect of Cu CMP can not only be ensured, also compatible with traditional C u CMP.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of method improving Cu CMP efficiency.
Background technology
Along with developing rapidly of semiconductor technology, the copper cash interconnection technique of double damask structure has become the major way of integrated circuit interconnection line formation.In copper cash interconnection technology, after photoetching, being etched with formation line groove, through copper plating (Electro-plating, be called for short ECP) and annealing (anneal) directly enter chemomechanical copper grinding (Chemical Mechanical Polishing afterwards, be called for short CMP) technique, and finally define copper cash.
Fig. 1-5 is traditional copper interconnection line process flow diagrams in background technology of the present invention; As Figure 1-5, sequentially be coated with etching barrier layer (etch stop) 12, low dielectric coefficient medium layer 13 and metal hard mask 14 successively from bottom to up at the upper surface of interlayer dielectric layer 11, through hole 15 runs through the upper surface of low dielectric coefficient medium layer 13 and metal hard mask 14 to etching barrier layer 12; First, fill also electro-coppering 16 and be full of the upper surface of through hole 15 the hard mask 14 of covering metal, because graphics shape has certain height change, make the upper surface out-of-flatness of electro-coppering 16; Secondly, adopt quick grinding technics (CMP) to remove the surperficial most of copper film of copper 16 tentatively to reach smooth, and continue to adopt the grinding technics of low speed to remove the upper surface of residual copper 161 to metal hard mask 14; Then, remove metal hard mask 14, and carry out planarization to again grinding residual copper 162, finally form copper interconnecting line 163.
Copper due to plating needs annealing could meet the relevant parameter of production technology needs, and annealing needs certain copper cash thickness just can get a desired effect, so the thickness of the copper film of plating grinds the copper film thickness of actual needs plating much larger than Cu CMP.This adds increased the grinding load of Cu CMP, the grinding holistic cost of raising, reduce production efficiency (Throughput).
Summary of the invention
The invention discloses a kind of method improving Cu CMP efficiency, wherein, comprise the following steps:
Step S1: on the damascene structure with interconnection line through hole, plated metal copper film is full of described through hole and covers the upper surface of described semiconductor structure, and the upper surface out-of-flatness of described copper film;
Step S2: remove the described copper film of part according to process requirements electrolysis, after carrying out planarization to described copper film, electrolysis residual copper film thickness meets subsequent CMP low speed fine gtinding process requirements, and continue cmp planarization metallization processes formation copper interconnection line.
The method of above-mentioned raising Cu CMP efficiency, wherein, described damascene structure also comprises semiconductor substrate, interlayer dielectric layer, etching barrier layer, low dielectric coefficient medium layer and metal hard mask, and described semiconductor substrate is coated with described interlayer dielectric layer, etching barrier layer, low dielectric coefficient medium layer and metal hard mask from bottom to up in passing successively.
The method of above-mentioned raising Cu CMP efficiency, wherein, described interconnection line through hole runs through described metal hard mask and the described low dielectric coefficient medium layer upper surface to described etching barrier layer.
The method of above-mentioned raising Cu CMP efficiency, wherein, described copper film covers the upper surface of described metal hard mask.
The method of above-mentioned raising Cu CMP efficiency, wherein, after removing the described copper film of part according to process requirements electrolysis in described step S2, adopts CMP low speed grinding technics to remove the upper surface of the described copper film of part to described metal hard mask.
The method of above-mentioned raising Cu CMP efficiency, wherein, after adopting CMP low speed grinding technics to remove the described copper film of part to the upper surface of described metal hard mask, described hard mask is removed, and continue to adopt cmp planarization metallization processes to carry out planarization, to form copper interconnection line to grinding residue copper film.
In sum, owing to have employed technique scheme, the present invention proposes a kind of method improving Cu CMP efficiency, by carrying out electrolytic treatments to the copper film formed after plated metal copper, removal part copper film that can be controlled, to meet Cu CMP demand, thus simplify Cu CMP grinding technics step, reduce the Cu CMP time, save grinding cost, improve output capacity, the technological effect of Cu CMP can not only be ensured, also compatible with traditional C u CMP.
Accompanying drawing explanation
Fig. 1-5 is traditional copper interconnection line process flow diagrams in background technology of the present invention;
Fig. 6-13 is flowage structure schematic diagrames that the present invention improves the method for Cu CMP efficiency.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described:
Fig. 6-13 is flowage structure schematic diagrames that the present invention improves the method for Cu CMP efficiency;
As shown in figs. 6-13, first, at upper surface order interlayer dielectric layer 21, etching barrier layer 22, low dielectric coefficient medium layer 23 and the metal hard mask 24 successively from bottom to up of semiconductor substrate 2.
Secondly, the upper surface of the hard mask 24 of spin coating photoresist covering metal, after exposure, development, remove unnecessary photoresist, form photoresistance, and with this photoresistance for mask etches the upper surface of metal hard mask 24 and low-dielectric constant layer 23 to etching barrier layer 22 successively, after removing photoresistance, form interconnection line through hole 25.
Afterwards, plated metal copper film 26 is full of interconnection line through hole 25 and covers the upper surface of the hard mask 241 of residual metallic; Because image has height structure, make the upper surface of the copper film 26 formed uneven.
Then, in a cell according to follow-up CMP low speed fine gtinding process requirements, adopt the exact controllability electrolysis unit of copper to carry out electrolysis process 3 electrolysis and remove part copper film 26, to carry out preliminary planarization to the upper surface of copper film 26, and get rid of unnecessary part copper film; Owing to adopting electrolysis process 3, preliminary planarization is carried out to the copper film 26 with uneven upper surface, removal part copper film that can be controlled, not only simplify Cu CMP grinding technics step, also effectively decrease the Cu CMP time, and then improve output capacity.
Finally, adopt CMP low speed fine gtinding technique to grind again and remove the upper surface that partial electrolyte remains the hard mask 241 of copper film 261 to residual metallic, after removing the hard mask 241 of residual metallic, continue to adopt cmp planarization metallization processes to carry out the upper surface of planarization to residue low dielectric coefficient medium layer 231 to grinding residue copper film 262, form the copper interconnection line 263 meeting process requirements.
In sum, owing to have employed technique scheme, the embodiment of the present invention proposes a kind of method improving Cu CMP efficiency, by carrying out electrolytic treatments to the copper film with rough and uneven in surface upper surface formed after plated metal copper, and removal part copper film that can be controlled, and then meet Cu CMP demand, not only simplify Cu CMP grinding technics step, also reduce the Cu CMP time, improve output capacity, ensure the technological effect of Cu CMP, and compatible with traditional C u CMP.
By illustrating and accompanying drawing, giving the exemplary embodiments of the ad hoc structure of embodiment, based on the present invention's spirit, also can do other conversion.Although foregoing invention proposes existing preferred embodiment, but these contents are not as limitation.
For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should regard the whole change and correction of containing true intention of the present invention and scope as.In Claims scope, the scope of any and all equivalences and content, all should think and still belong to the intent and scope of the invention.
Claims (3)
1. improve a method for Cu CMP efficiency, it is characterized in that, comprise the following steps:
Step S1: on the damascene structure with interconnection line through hole, plated metal copper film is full of described through hole and covers the upper surface of described damascene structure, and the upper surface out-of-flatness of described copper film;
Step S2: adopt the exact controllability electrolysis unit of copper to remove the described copper film of part according to process requirements electrolysis, after planarization is carried out to described copper film, electrolysis residual copper film thickness meets subsequent CMP low speed fine gtinding process requirements, and continues cmp planarization metallization processes formation copper interconnection line;
Described damascene structure comprises metal hard mask, and described copper film covers the upper surface of described metal hard mask;
Wherein, the step continuing cmp planarization metallization processes formation copper interconnection line comprises:
Carry out cmp planarization metallization processes and remove the upper surface of described electrolysis residue copper film to described metal hard mask;
And after the described metal hard mask of removal, proceed cmp planarization metallization processes and form described copper interconnection line.
2. the method for raising Cu CMP efficiency according to claim 1, it is characterized in that, described damascene structure also comprises semiconductor substrate, interlayer dielectric layer, etching barrier layer, low dielectric coefficient medium layer, and on described semiconductor substrate, order is coated with described interlayer dielectric layer, etching barrier layer, low dielectric coefficient medium layer and metal hard mask successively from bottom to up.
3. the method for raising Cu CMP efficiency according to claim 2, is characterized in that, described interconnection line through hole runs through described metal hard mask and the described low dielectric coefficient medium layer upper surface to described etching barrier layer.
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| CN102891104B true CN102891104B (en) | 2015-07-29 |
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| CN105336679B (en) * | 2014-08-07 | 2018-08-21 | 中芯国际集成电路制造(上海)有限公司 | A method of forming metal interconnection structure |
Citations (8)
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| CN1411039A (en) * | 2001-10-03 | 2003-04-16 | 株式会社东芝 | Electrolysis polishing method |
| CN1719606A (en) * | 2004-07-09 | 2006-01-11 | 国际商业机器公司 | Conducting material and mfg. method thereof |
| CN1759479A (en) * | 2003-03-07 | 2006-04-12 | 先进微装置公司 | Method for manufacturing a semiconductor component having a barrier-lined opening |
| CN1842577A (en) * | 2003-06-06 | 2006-10-04 | 应用材料公司 | Polishing composition and method for polishing a conductive material |
| CN101101861A (en) * | 2002-05-17 | 2008-01-09 | 株式会社荏原制作所 | Substrate processing apparatus and substrate processing method |
| CN101256977A (en) * | 2007-03-01 | 2008-09-03 | 台湾积体电路制造股份有限公司 | Semiconductor structure and forming method of semiconductor structure |
| CN102315194A (en) * | 2010-06-22 | 2012-01-11 | 富士胶片株式会社 | Microstructure and fine structure preparation |
| CN102446824A (en) * | 2011-09-15 | 2012-05-09 | 上海华力微电子有限公司 | Damascus integration method |
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2012
- 2012-09-17 CN CN201210341662.6A patent/CN102891104B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1411039A (en) * | 2001-10-03 | 2003-04-16 | 株式会社东芝 | Electrolysis polishing method |
| CN101101861A (en) * | 2002-05-17 | 2008-01-09 | 株式会社荏原制作所 | Substrate processing apparatus and substrate processing method |
| CN1759479A (en) * | 2003-03-07 | 2006-04-12 | 先进微装置公司 | Method for manufacturing a semiconductor component having a barrier-lined opening |
| CN1842577A (en) * | 2003-06-06 | 2006-10-04 | 应用材料公司 | Polishing composition and method for polishing a conductive material |
| CN1719606A (en) * | 2004-07-09 | 2006-01-11 | 国际商业机器公司 | Conducting material and mfg. method thereof |
| CN101256977A (en) * | 2007-03-01 | 2008-09-03 | 台湾积体电路制造股份有限公司 | Semiconductor structure and forming method of semiconductor structure |
| CN102315194A (en) * | 2010-06-22 | 2012-01-11 | 富士胶片株式会社 | Microstructure and fine structure preparation |
| CN102446824A (en) * | 2011-09-15 | 2012-05-09 | 上海华力微电子有限公司 | Damascus integration method |
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