CN102890234B - A kind of SRAM type FPGA application verification system and application verification method - Google Patents
A kind of SRAM type FPGA application verification system and application verification method Download PDFInfo
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Abstract
A kind of SRAM type FPGA application verification system and application verification method, verification system comprises PC, single-chip microcomputer, control FPGA, controlled clock unit, controllable electric power unit, temperature data samwpling unit, electric current and voltage data acquisition unit and tested FPGA dispensing unit, this system achieves the integrated verification to the various function of tested fpga chip, application verification method is also had based on this verification system, verification method comprises the basic function application verification for fpga chip, power adaptation application verification, the functional verification of four aspects such as the checking of surface temperature dynamic application and dynamic power consumption application verification.The present invention can according to the needs of FPGA device application checking, at any time adjustment and measurement is carried out to Verification Project or method, application verification for SRAM type FPGA is significant, and the present invention can to compare test to the device function performance of different factory easily.
Description
Technical field
The present invention relates to a kind of SRAM type FPGA application verification system and application verification method.
Background technology
In the last few years, SRAM type FPGA, as reconfigurable LSI devices, used more and more in satellite development.Because the working environment of satellite is special, such as: can not to change in device operation, the condition such as space radiation, this requires that FPGA possesses higher reliability on the one hand, requires that FPGA possesses the adaptability to space environment on the other hand.Further, in order to ensure satellite spatial application reliability, before FPGA is formally applied to space flight model task, testing experiment FPGA being carried out to the closely-related functional performance with application state is needed, i.e. the application verification of FPGA.
Before this, FPGA application comparatively disperses, and along with increasing of FPGA application, the FPGA carried out separately verifies that first work have more overlapped contents, causes the wasting of resources; The second, different to the requirement of FPGA, checking stresses in a certain respect more, and checking work is not comprehensive; The dispersion checking of the three, FPGA will produce multi-standard, be difficult to form general selection standard, be unfavorable for the unified control and management of FPGA.Therefore, in order to saving resource, raise the efficiency, propose a set of effective verification method comprehensively, the unified checking work carried out FPGA, and instruct the application of FPGA very necessary with this.
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, the application verification for SRAM type FPGA provide a set of Verification Project comprehensively, the SRAM type FPGA application verification system of highly versatile and application verification method.
Technical solution of the present invention is:
A kind of SRAM type FPGA application verification system, comprises PC, single-chip microcomputer, control FPGA, controlled clock unit, controllable electric power unit, temperature data samwpling unit, electric current and voltage data acquisition unit and tested FPGA dispensing unit;
PC is according to the tested FPGA configuration file preset, by tested FPGA dispensing unit, tested fpga chip is configured, PC also sending controling instruction to single-chip microcomputer, send into after single-chip microcomputer format transformation among control FPGA, control FPGA adjusts according to the condition of work of the steering order received to tested fpga chip, that is: control FPGA by controlled clock unit adjust tested fpga chip clock input and control FPGA adjust the supply voltage of tested fpga chip by controllable electric power unit; Described tested fpga chip is SRAM type FPGA;
Control FPGA directly gathers the I/O output signal of tested fpga chip, temperature data samwpling unit gathers the surface temperature of tested fpga chip and exports to control FPGA, the outputting drive voltage of the tested fpga chip of electric current and voltage data acquisition unit acquires, core voltage, output driving current and core current, and result is outputted among control FPGA, the I/O of the tested fpga chip collected exports by control FPGA, surface temperature data, outputting drive voltage, core voltage, output driving current and core current send to PC to show by single-chip microcomputer.
Described temperature data samwpling unit is the surface temperature being gathered tested fpga chip by thermopair.
Described SRAM type FPGA application verification method comprises basic function application verification, power adaptation application verification, the checking of surface temperature dynamic application and dynamic power consumption application verification;
Basic function application verification step is as follows:
A () internal element to tested fpga chip arranges its configuration file, and estimate the I/O output of the tested fpga chip under this configuration file according to configuration file; Described internal element comprises input-output unit IOB, programmed logical module CLB, clock unit DLL and embedded functional module BRAM;
B () PC is according to the tested FPGA configuration file preset in step (a), by tested FPGA dispensing unit, tested fpga chip is configured, described SRAM type FPGA application verification system is tested tested fpga chip afterwards, and the I/O gathering tested fpga chip exports and delivers in PC;
C I/O Output rusults that () compares the actual measurement under each configuration file estimates I/O output accordingly with it, if all identical, then shows that the basic function of tested fpga chip is normal, otherwise, show the basic function existing problems of tested fpga chip;
The step of power adaptation application verification is as follows:
(1) in the operating voltage range of tested fpga chip, choose core voltage Vccint and outputting drive voltage Vcco, by controllable electric power unit, tested fpga chip is powered;
(2) tested fpga chip is configured to counter logic by tested FPGA dispensing unit by PC;
(3) keep tested fpga chip under operation, do not change the value of outputting drive voltage Vcco, core voltage Vccint is reduced 0.1V at every turn, until core voltage electricity shortage causes counter output error;
(4) magnitude of voltage of the core voltage Vccint that record is last, is the minimum core operating voltage of tested fpga chip;
(5) step (1) and (2) are re-executed;
(6) keep tested fpga chip under operation, do not change the value of outputting drive voltage Vcco, core voltage Vccint is increased 0.1V at every turn, until core voltage is powered and excessively caused counter output error;
(7) magnitude of voltage of the core voltage Vccint that record is last, is the maximum core operational voltage of tested fpga chip;
(8) step (1) and (2) are re-executed;
(9) keep tested fpga chip under operation, do not change the value of outputting drive voltage Vcco, core voltage Vccint is reduced 0.1V at every turn, until counter function lost efficacy;
(10) magnitude of voltage of the core voltage Vccint that record is last, the minimum data being tested fpga chip keeps voltage;
(11) counter logic described in step (2) is written in tested FPGA dispensing unit;
(12) in the operating voltage range of tested fpga chip, choose the value of core voltage Vccint and outputting drive voltage Vcco;
(13) slope that powers on of modern outputting drive voltage Vcco remains unchanged, and the slope that powers on of core voltage Vccint is set to 0.1V/50ms;
(14) be the supply voltage under tested fpga chip load step (12) and (13) condition, whether the counter logic detecting tested fpga chip exports the electric current that powers on of whether normal and tested fpga chip more than 2A, if the counter logic of tested fpga chip exports the normal and electric current that powers on of tested fpga chip more than 2A, then think that the minimum voltage slope that powers on of tested fpga chip is 0.1V/50ms, otherwise, make that core voltage Vccint's power on slope on the basis of 0.1V/50ms, increase progressively 0.2V/50ms at every turn, until the counter logic meeting tested fpga chip exports the normal and condition of electric current more than 2A that power on of tested fpga chip, be the minimum voltage slope that powers on of tested fpga chip,
(15) make the slope that powers on of outputting drive voltage Vcco remain unchanged, the slope that powers on of core voltage Vccint is set to 10V/50ms;
(16) be the supply voltage under tested fpga chip load step (12) and (15) condition, whether the counter logic detecting tested fpga chip exports the electric current that powers on of whether normal and tested fpga chip more than 2A, if the counter logic of tested fpga chip exports the normal and electric current that powers on of tested fpga chip more than 2A, then think that the maximum voltage slope that powers on of tested fpga chip is 10V/50ms, otherwise, make that core voltage Vccint's power on slope on the basis of 10V/50ms, successively decrease 0.2V/50ms at every turn, until the counter logic meeting tested fpga chip exports the normal and condition of electric current more than 2A that power on of tested fpga chip, be the maximum voltage slope that powers on of tested fpga chip,
Surface temperature dynamic application verification step is as follows:
(T1) consider that the IO of tested fpga chip accounts for frequency, resource utilization and frequency of operation three kinds of factors, design three kinds of configuration files;
(T2) according to the configuration file in step (T1), PC is tested fpga chip loading configuration file one by one by tested FPGA dispensing unit;
(T3) surface temperature of the tested fpga chip of serviceability temperature data acquisition unit acquires, and record data;
(T4) tested fpga chip surface temperature and the relation curve between its IO occupancy, resource utilization and frequency of operation is drawn according to data;
Dynamic power consumption application verification step is as follows:
(M1) consider the IO occupancy of tested fpga chip, resource utilization and frequency of operation three kinds of factors, design three kinds of configuration files;
(M2) according to the configuration file in step (M1), PC is tested fpga chip loading configuration file one by one by tested FPGA dispensing unit;
(M3) use voltage and current data collecting unit to gather core voltage Vccint, the core current Iccint of tested fpga chip, the value of outputting drive voltage Vcco and output driving current Icco, record data and calculate the total power consumption of tested fpga chip;
(M4) tested fpga chip total power consumption and the relation curve between its IO occupancy, resource utilization and frequency of operation is drawn according to data.
The present invention's advantage is compared with prior art:
(1) the invention provides one completely, dynamic SRAM type FPGA application verification system, can according to the needs of device application checking, carry out adjustment and measurement to Verification Project or method at any time, the application verification for SRAM type FPGA is significant.
(2) the present invention can be general for the SRAM type FPGA of domestic different factories same specification, and also can be general for the SRAM type FPGA of external Xilinx company same specification, can to compare test to the device function performance of different factory easily.
Accompanying drawing explanation
Fig. 1 SRAM type FPGA verification system schematic diagram;
Fig. 2 SRAM type FPGA application verification method schematic diagram;
Embodiment
As shown in Figure 1, the invention provides a kind of SRAM type FPGA application verification system, comprise PC, single-chip microcomputer, control FPGA, controlled clock unit, controllable electric power unit, temperature data samwpling unit, electric current and voltage data acquisition unit and tested FPGA dispensing unit;
PC is according to the tested FPGA configuration file preset, by tested FPGA dispensing unit, tested fpga chip is configured, PC also sending controling instruction to single-chip microcomputer, send into after single-chip microcomputer format transformation among control FPGA, control FPGA adjusts according to the condition of work of the steering order received to tested fpga chip, that is: control FPGA by controlled clock unit adjust tested fpga chip clock input and control FPGA adjust the supply voltage of tested fpga chip by controllable electric power unit; Described tested fpga chip is SRAM type FPGA;
Control FPGA directly gathers the I/O output signal of tested fpga chip, temperature data samwpling unit gathers the surface temperature of tested fpga chip and exports to control FPGA, the outputting drive voltage of the tested fpga chip of electric current and voltage data acquisition unit acquires, core voltage, output driving current and core current, and result is outputted among control FPGA, the I/O of the tested fpga chip collected exports by control FPGA, surface temperature data, outputting drive voltage, core voltage, output driving current and core current send to PC to show by single-chip microcomputer.
Described temperature data samwpling unit is the surface temperature being gathered tested fpga chip by thermopair.
As shown in Figure 2, SRAM type FPGA application verification method comprises basic function application verification, power adaptation application verification, the checking of surface temperature dynamic application and dynamic power consumption application verification;
Basic function application verification step is as follows:
A () internal element to tested fpga chip arranges its configuration file, and estimate the I/O output of the tested fpga chip under this configuration file according to configuration file; Described internal element comprises input-output unit IOB, programmed logical module CLB, clock unit DLL and embedded functional module BRAM;
B () PC is according to the tested FPGA configuration file preset in step (a), by tested FPGA dispensing unit, tested fpga chip is configured, described SRAM type FPGA application verification system is tested tested fpga chip afterwards, and the I/O gathering tested fpga chip exports and delivers in PC;
C I/O Output rusults that () compares the actual measurement under each configuration file estimates I/O output accordingly with it, if all identical, then shows that the basic function of tested fpga chip is normal, otherwise, show the basic function existing problems of tested fpga chip;
The step of power adaptation application verification is as follows:
(1) in the operating voltage range of tested fpga chip, choose core voltage Vccint be 2.50V and outputting drive voltage Vcco is 3.30V, is powered to tested fpga chip by controllable electric power unit;
(2) tested fpga chip is configured to counter logic by tested FPGA dispensing unit by PC;
(3) keep tested fpga chip under operation, outputting drive voltage keeps Vcco=3.30V, core voltage Vccint is reduced 0.1V at every turn, until core voltage electricity shortage causes counter output error;
(4) magnitude of voltage of the core voltage Vccint that record is last, is the minimum core operating voltage of tested fpga chip;
(5) step (1) and (2) are re-executed;
(6) keep tested fpga chip under operation, outputting drive voltage keeps Vcco=3.30V, and core voltage Vccint is increased 0.1V at every turn, until core voltage is powered and excessively caused counter output error;
(7) magnitude of voltage of the core voltage Vccint that record is last, is the maximum core operational voltage of tested fpga chip;
(8) step (1) and (2) are re-executed;
(9) keep tested fpga chip under operation, do not change the value of outputting drive voltage Vcco, core voltage Vccint is reduced 0.1V at every turn, until counter function lost efficacy;
(10) magnitude of voltage of the core voltage Vccint that record is last, the minimum data being tested fpga chip keeps voltage;
(11) counter logic described in step (2) is written in tested FPGA dispensing unit;
(12) in the operating voltage range of tested fpga chip, choose the value of core voltage Vccint and outputting drive voltage Vcco;
(13) make the slope that powers on of outputting drive voltage Vcco remain unchanged, the slope that powers on of core voltage Vccint is set to 0.1V/50ms;
(14) be the supply voltage under tested fpga chip load step (12) and (13) condition, whether the counter logic detecting tested fpga chip exports the electric current that powers on of whether normal and tested fpga chip more than 2A, if the counter logic of tested fpga chip exports the normal and electric current that powers on of tested fpga chip more than 2A, then think that the minimum voltage slope that powers on of tested fpga chip is 0.1V/50ms, otherwise, make that core voltage Vccint's power on slope on the basis of 0.1V/50ms, increase progressively 0.2V/50ms at every turn, until the counter logic meeting tested fpga chip exports the normal and condition of electric current more than 2A that power on of tested fpga chip, be the minimum voltage slope that powers on of tested fpga chip,
(15) slope that powers on of modern outputting drive voltage Vcco remains unchanged, and the slope that powers on of core voltage Vccint is set to 10V/50ms;
(16) be the supply voltage under tested fpga chip load step (12) and (15) condition, whether the counter logic detecting tested fpga chip exports the electric current that powers on of whether normal and tested fpga chip more than 2A, if the counter logic of tested fpga chip exports the normal and electric current that powers on of tested fpga chip more than 2A, then think that the maximum voltage slope that powers on of tested fpga chip is 10V/50ms, otherwise, make that core voltage Vccint's power on slope on the basis of 10V/50ms, successively decrease 0.2V/50ms at every turn, until the counter logic meeting tested fpga chip exports the normal and condition of electric current more than 2A that power on of tested fpga chip, be the maximum voltage slope that powers on of tested fpga chip,
Wherein, step (3) and (6) although described in counter output error refer to that counter is in work, there is mistake in count results; Counter function described in step (9) lost efficacy and referred to that counter lost its tally function completely.
Surface temperature dynamic application verification step is as follows:
(T1) consider the IO occupancy of tested fpga chip, resource utilization and frequency of operation three kinds of factors, design three kinds of configuration files;
(T2) according to the configuration file in step (T1), PC is tested fpga chip loading configuration file one by one by tested FPGA dispensing unit;
(T3) surface temperature of the tested fpga chip of serviceability temperature data acquisition unit acquires, and record data;
(T4) tested fpga chip surface temperature and the relation curve between its IO occupancy, resource utilization and frequency of operation is drawn according to data;
Wherein, IO occupancy aspect is 50% in the resource utilization of tested fpga chip, and input clock frequency is under the condition of 40MHz, respectively IO occupancy be 10%, 30%, 50%, 70% and 90% 5 kind of situation under design configuration file, to test; Resource utilization aspect, the resource utilization of tested fpga chip is equivalent to the utilization rate of the programmed logical module CLB of tested fpga chip inside, be 40MHz at the input clock frequency of tested fpga chip, IO occupancy is under the condition of 10%, respectively resource utilization be 10%, 30%, 50%, 70% and 90% 5 kind of situation under design configuration file, to test; Frequency of operation aspect, be 10% in the IO occupancy of tested fpga chip, resource utilization is design configuration file under the condition of 50%, tests respectively under input clock frequency is 40Mhz, 50Mhz, 60Mhz, 80Mhz, 100Mhz and 120Mhz six kinds of situations.
Dynamic power consumption application verification step is as follows:
(M1) consider the IO occupancy of tested fpga chip, resource utilization and frequency of operation three kinds of factors, design three kinds of configuration files;
(M2) according to the configuration file in step (M1), PC is tested fpga chip loading configuration file one by one by tested FPGA dispensing unit;
(M3) use voltage and current data collecting unit to gather core voltage Vccint, the core current Iccint of tested fpga chip, the value of outputting drive voltage Vcco and output driving current Icco, record data and calculate the total power consumption of tested fpga chip;
(M4) tested fpga chip total power consumption and the relation curve between its IO occupancy, resource utilization and frequency of operation is drawn according to data.
Wherein, the setting of IO occupancy, resource utilization and frequency of operation three kinds of factors verify with surface temperature dynamic application in arrange identical.
Claims (1)
1. a SRAM type FPGA application verification method, is characterized in that: comprise basic function application verification, power adaptation application verification, the checking of surface temperature dynamic application and dynamic power consumption application verification;
Basic function application verification step is as follows:
A () internal element to tested fpga chip arranges its configuration file, and estimate the I/O output of the tested fpga chip under this configuration file according to configuration file; Described internal element comprises input-output unit IOB, programmed logical module CLB, clock unit DLL and embedded functional module BRAM;
B () PC is according to the tested FPGA configuration file preset in step (a), by tested FPGA dispensing unit, tested fpga chip is configured, described SRAM type FPGA application verification system is tested tested fpga chip afterwards, and the I/O gathering tested fpga chip exports and delivers in PC;
C I/O Output rusults that () compares the actual measurement under each configuration file estimates I/O output accordingly with it, if all identical, then shows that the basic function of tested fpga chip is normal, otherwise, show the basic function existing problems of tested fpga chip;
The step of power adaptation application verification is as follows:
(1) in the operating voltage range of tested fpga chip, choose core voltage Vccint and outputting drive voltage Vcco, by controllable electric power unit, tested fpga chip is powered;
(2) tested fpga chip is configured to counter logic by tested FPGA dispensing unit by PC;
(3) keep tested fpga chip under operation, do not change the value of outputting drive voltage Vcco, core voltage Vccint is reduced 0.1V at every turn, until core voltage electricity shortage causes counter output error;
(4) magnitude of voltage of the core voltage Vccint that record is last, is the minimum core operating voltage of tested fpga chip;
(5) step (1) and (2) are re-executed;
(6) keep tested fpga chip under operation, do not change the value of outputting drive voltage Vcco, core voltage Vccint is increased 0.1V at every turn, until core voltage is powered and excessively caused counter output error;
(7) magnitude of voltage of the core voltage Vccint that record is last, is the maximum core operational voltage of tested fpga chip;
(8) step (1) and (2) are re-executed;
(9) keep tested fpga chip under operation, do not change the value of outputting drive voltage Vcco, core voltage Vccint is reduced 0.1V at every turn, until counter function lost efficacy;
(10) magnitude of voltage of the core voltage Vccint that record is last, the minimum data being tested fpga chip keeps voltage;
(11) counter logic described in step (2) is written in tested FPGA dispensing unit;
(12) in the operating voltage range of tested fpga chip, choose the value of core voltage Vccint and outputting drive voltage Vcco;
(13) make the slope that powers on of outputting drive voltage Vcco remain unchanged, the slope that powers on of core voltage Vccint is set to 0.1V/50ms;
(14) be the supply voltage under tested fpga chip load step (12) and (13) condition, whether the counter logic detecting tested fpga chip exports the electric current that powers on of whether normal and tested fpga chip more than 2A, if the counter logic of tested fpga chip exports the normal and electric current that powers on of tested fpga chip more than 2A, then think that the minimum voltage slope that powers on of tested fpga chip is 0.1V/50ms, otherwise, make that core voltage Vccint's power on slope on the basis of 0.1V/50ms, increase progressively 0.2V/50ms at every turn, until the counter logic meeting tested fpga chip exports the normal and condition of electric current more than 2A that power on of tested fpga chip, be the minimum voltage slope that powers on of tested fpga chip,
(15) make the slope that powers on of outputting drive voltage Vcco remain unchanged, the slope that powers on of core voltage Vccint is set to 10V/50ms;
(16) be the supply voltage under tested fpga chip load step (12) and (15) condition, whether the counter logic detecting tested fpga chip exports the electric current that powers on of whether normal and tested fpga chip more than 2A, if the counter logic of tested fpga chip exports the normal and electric current that powers on of tested fpga chip more than 2A, then think that the maximum voltage slope that powers on of tested fpga chip is 10V/50ms, otherwise, make that core voltage Vccint's power on slope on the basis of 10V/50ms, successively decrease 0.2V/50ms at every turn, until the counter logic meeting tested fpga chip exports the normal and condition of electric current more than 2A that power on of tested fpga chip, be the maximum voltage slope that powers on of tested fpga chip,
Surface temperature dynamic application verification step is as follows:
(T1) consider the IO occupancy of tested fpga chip, resource utilization and frequency of operation three kinds of factors, design three kinds of configuration files;
(T2) according to the configuration file in step (T1), PC is tested fpga chip loading configuration file one by one by tested FPGA dispensing unit;
(T3) surface temperature of the tested fpga chip of serviceability temperature data acquisition unit acquires, and record data;
(T4) tested fpga chip surface temperature and the relation curve between its IO occupancy, resource utilization and frequency of operation is drawn according to data;
Dynamic power consumption application verification step is as follows:
(M1) consider the IO occupancy of tested fpga chip, resource utilization and frequency of operation three kinds of factors, design three kinds of configuration files;
(M2) according to the configuration file in step (M1), PC is tested fpga chip loading configuration file one by one by tested FPGA dispensing unit;
(M3) use voltage and current data collecting unit to gather core voltage Vccint, the core current Iccint of tested fpga chip, the value of outputting drive voltage Vcco and output driving current Icco, record data and calculate the total power consumption of tested fpga chip;
(M4) tested fpga chip total power consumption and the relation curve between its IO occupancy, resource utilization and frequency of operation is drawn according to data.
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| CN103439644B (en) * | 2013-08-13 | 2015-09-23 | 哈尔滨工业大学 | A kind of SRAM-based FPGA degradation testing system |
| CN104808136A (en) * | 2015-05-18 | 2015-07-29 | 杭州士兰微电子股份有限公司 | Device for testing relevance between chip temperature and current intensity |
| CN106569124A (en) * | 2016-11-09 | 2017-04-19 | 中国空间技术研究院 | Universal dynamic aging system for Virtex-5 FPGAs (field programmable gate arrays) |
| CN111123083B (en) * | 2019-12-06 | 2022-04-29 | 国家电网有限公司 | Test system and method for FPGA PLL IP core |
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