CN102880750A - Calculation method for measuring DC (direct current) fault ride-through capabilities of different multilevel converters - Google Patents

Abstract

The invention discloses a calculation method for measuring the DC (direct current) fault ride-through capabilities of multilevel converters in the technical field of power transmission and distribution. The technical scheme of the calculation method comprises the following steps: an MMC-HVDC system model of an actual project is established in a PSCAD/EMTD electromagnetic transient simulation software, and different time-points are set; curves of current injected under different conditions are obtained through simulation; the curves of current obtained are integrated to get corresponding integration areas; ratios between different integration areas are calculated to get the DC fault ride-through capability of a multilevel converter. The invention has the benefits that the calculation method for measuring DC fault ride-through capabilities of different multilevel converters MMC is provided, and the DC short circuit inhibiting ability of a modularized multilevel converter MMC can be accurately calculated.

Description

A kind of computing method of weighing different multilevel converter DC Line Fault ride-through capabilities

Technical field

The invention belongs to the power transmission and distribution technical field, relate in particular to a kind of computing method of weighing multilevel converter DC Line Fault ride-through capability.

Background technology

Modularization multi-level converter MMC successfully has been applied in the power current inverter, mainly is to be applied in high voltage direct current HVDC transmission system at present.With tradition based on the VSC-HVDC of voltage source converter Comparatively speaking, HVDC (High Voltage Direct Current) transmission system MMC-HVDC based on modularization multi-level converter has plurality of advantages: the fully control of AC and DC side, dc bus need not capacitor, redundancy running ability during the power electronic equipment fault need not wave filter etc.2010, first business-like MMC-HVDC engineering " Trans Bay Cable Project (TBC) " put into operation in the U.S., its DC voltage of high operation be ± 200kV, the maximum 400MW of transmission capacity.In addition, there are 4 HVDC (High Voltage Direct Current) transmission system MMC-HVDC engineerings based on modularization multi-level converter of surpassing to put into operation in 2013 all over the world.Wherein, can transmit the rated power of 2 * 1000MW to Hispanic engineering " INELFE " from France.But nearly all MMC-HVDC engineering all is to adopt half-bridge submodule HBSM topological structure.Except half-bridge submodule HBSM, the part document has also proposed the inside submodule SM structure of two kinds of alternative modularization multi-level converter MMC: full-bridge submodule FBSM and two clamped submodule CDSM.

DC Line Fault is the most common a kind of fault of MMC-HVDC system, and its impact and the extent of injury are also serious.Simultaneously, modularization multi-level converter MMC has again plurality of optional to select different submodule SM structures, but for the DC Line Fault ride-through capability of the modularization multi-level converter MMC of different submodule SM, also not have well to weigh the computing method of comparison at present.

For this problem, the part document analysis DC Line Fault mechanism before and after the converter blocking, inquired into the circuit model of analyzing for submodule SM excess current.Yet these documents have only been considered based on the half-bridge submodule HBSM among the modularization multi-level converter MMC, particularly when the DC Line Fault ride-through capability of the different submodule SM structure of contrast, have not provided a clear and definite evaluation index.Although the equivalent electrical circuit of disparate modules multilevel converter MMC is different with the transverter model before and after modularization multi-level converter MMC locking, it also can be inquired into the similar analysis method.In addition, from the angle of engineering, the theoretical analysis of circuit is very complicated after the locking, and this theoretical analysis also there is no need in engineering, and Engineering Simulation can be considered more more fully influence factors, is to solve the better method of problems.

Inventive method

The present invention is directed to the problem that the modularization multi-level converter MMC DC Line Fault ride-through capability of the different sub modular structures described in the background technology can't Quantitative Comparative, proposed a kind of computing method of weighing multilevel converter DC Line Fault ride-through capability.

A kind of computing method of weighing multilevel converter DC Line Fault ride-through capability is characterized in that, specifically may further comprise the steps:

Step 1: the system model of setting up the MMC-HVDC of Practical Project;

Step 2: system is arranged the different moment;

Step 3: after DC Line Fault occured, the artificial pressure arranged under the condition of not locking of transverter, and emulation obtains injecting the first current curve F (t) of trouble spot;

Step 4: converter blocking behind the DC Line Fault, emulation obtain injecting the second current curve G (t) of trouble spot;

Step 5: calculate first integral area S ₁

Step 6: calculate second integral area S ₂

Step 7: calculate the first area S ₁With second area S ₂Ratio value representation transverter DC Line Fault ride-through capability.

In the step 1: the MMC-HVDC system modelling

In electromagnetic transient simulation software PSCAD/EMTDC, set up the MMC system model of Practical Project, if the MMC of more different submodules only, and the parameter of MMC-HVDC systematic parameter, transformer and proportional integral PI parameter are consistent;

In the step 2: system is arranged the different moment

According to requirement of engineering be set the different moment, comprise constantly t of DC Line Fault _F, the MMC locking is t constantly _BAnd the descendant occurs and do not take any safeguard measure for transverter is set in DC Line Fault, namely artificially forces to arrange the transverter moment t that AC circuit breaker does not move under the barring condition _T, depend on the time-delay of measuring system and the reaction time of protective device, general t _T=t _F+ 60ms;

In the step 3: ask for the first current curve F (t)

The descendant occurs and does not take any safeguard measure for transverter is set in DC Line Fault; i.e. artificial pressure arranges not locking of transverter; emulation obtains injecting the first current curve F (t) of trouble spot; be that DC Line Fault generation descendant does not take any safeguard measure for transverter is set; namely artificial the pressure arranges under the condition of not locking of transverter, the fault current I that the trouble spot is injected under the MMC-HVDC system DC Line Fault _ShortCurve;

In the step 4: ask for the second current curve G (t)

After DC Line Fault occurs, converter blocking, emulation obtains injecting the second current curve G (t) of trouble spot, namely under the condition of MMC-HVDC converter blocking under DC Line Fault, the fault current I that the trouble spot is injected _ShortCurve, wherein MMC is at t _BConstantly locking;

In the step 5: calculate first integral area S ₁

Calculating is from moment t _FTo moment t _TThe first current curve F (t) is carried out integration, calculate the first area S ₁

In the step 6: calculate second integral area S ₂

Calculating is from moment t _FTo moment t _TThe second current curve G (t) is carried out integration, calculate second area S ₂

In the step 7: calculate transverter DC Line Fault ride-through capability

Ask first integral area S ₁With second integral area S ₂Ratio, be denoted as DFRTI among the present invention, namely calculate by following definition

$\mathrm{DFRTI}=\frac{S_1}{S_1}=\frac{{\∫}_{t_F}^{t_T}F\left(t\right)\mathrm{dt}}{{\∫}_{t_F}^{t_T}G\left(t\right)\mathrm{dt}}$

Wherein, DFRTI can represent the DC Line Fault ride-through capability of MMC, t _TThe moment of expression AC circuit breaker action, t _FThe expression DC Line Fault moment, and this method also is applicable to the multilevel converter of other type.

The invention has the beneficial effects as follows, a kind of computing method of weighing the DC Line Fault ride-through capability of different multilevel converters have been proposed, it is a kind of effective DC Line Fault ride-through capability computing method, the method can accurate Calculation modularization multi-level converter MMC in direct-current short circuit suppress ability, it can estimate any based on the quality with disparate modules multilevel converter MMC DC Line Fault ride-through capability in the MMC-HVDC system of running parameter.

Description of drawings

Fig. 1 is modularization multi-level converter MMC topology diagram provided by the invention;

Fig. 2 is half-bridge submodule HBSM topology diagram provided by the invention;

Fig. 3 is full-bridge submodule FBSM submodule topology diagram provided by the invention;

Fig. 4 is two clamped submodule CDSM submodule topology diagram provided by the invention;

Fig. 5 is two ends MMC-HVDC DC bipolar fault current I provided by the invention _ShortSchematic diagram;

Fig. 6 is a kind of schematic diagram of weighing the computing method of multilevel converter DC Line Fault ride-through capability provided by the invention.

Embodiment

Below in conjunction with accompanying drawing, preferred embodiment is elaborated.Should be emphasized that following explanation only is exemplary, rather than in order to limit the scope of the invention and to use.

Fig. 1 is modularization multi-level converter MMC topology diagram provided by the invention.Among Fig. 1, A, B, C, expression MMC transverter AC three-phase; SM1, SM2 ..., SMn, in the expression MMC brachium pontis the 1st, 2 ..., n submodule; L represents the brachium pontis reactor; U _DcVoltage difference between expression MMC both positive and negative polarity dc bus.

Fig. 2 is half-bridge submodule HBSM topology diagram provided by the invention.Among Fig. 2, T ₁And T ₂Represent respectively up and down two insulated gate bipolar transistor IGBTs of half-bridge submodule HBSM, D ₁And D ₂The anti-paralleled diode that represents respectively corresponding insulated gate bipolar transistor IGBT; C ₀Capacitor in the expression half-bridge submodule; U _CExpression submodule capacitance voltage; U _SMExpression submodule port output voltage.

Fig. 3 is full-bridge submodule FBSM submodule topology diagram provided by the invention.Among Fig. 3, T ₁, T ₂, T ₃, T ₄Represent respectively four IGBT among the FBSM, D ₁, D ₂, D ₃, D ₄The anti-paralleled diode that represents respectively corresponding insulated gate bipolar transistor IGBT; C ₀Capacitor in the expression full-bridge submodule; U _CExpression submodule capacitance voltage; U _SMExpression submodule port output voltage.

Fig. 4 is two clamped submodule CDSM submodule topology diagram provided by the invention.Among Fig. 4, T ₁, T ₂, T ₃, T ₄, T ₅Represent respectively five insulated gate bipolar transistor IGBTs in two clamped submodule CDSM submodules, D1, D2, D3, D4, D5 represent respectively the anti-paralleled diode of corresponding insulated gate bipolar transistor IGBT; 2 separate diode D6 and D7, C ₀Capacitor in the expression full-bridge submodule; Uc represents the submodule capacitance voltage; U _SMExpression submodule port output voltage.

Fig. 5 is two ends MMC-HVDC DC bipolar fault current I provided by the invention _ShortSchematic diagram.Among Fig. 5, MMC1 and MMC2 are the two ends multilevel converter in the MMC-HVDC system of two ends, I _ShortElectric current for the inflow of DC bipolar trouble spot, be described as an example of the MMC-HVDC both-end example herein, but in essence for single MMC, single-ended or multi-terminal system also is same applicable, thus computing method of the present invention to portray to liking the DC Line Fault ride-through capability of MMC itself.

Fig. 6 is a kind of schematic diagram of weighing the computing method of multilevel converter DC Line Fault ride-through capability provided by the invention.Among Fig. 6, I _ShortElectric current (single-ended, among both-end or the multiterminal MMC-HVDC) for the inflow of DC bipolar trouble spot; S ₁From moment t _FTo moment t _TArea under the curve F (t); S ₂From moment t _FTo moment t _TArea under the curve G (t); F (t) does not take under the condition of any safeguard measure (i.e. artificial pressure arranges not locking of transverter) the fault current I that the trouble spot is injected under the MMC-HVDC system DC Line Fault for the descendant occurs DC Line Fault for transverter is set _ShortCurve; G (t) be MMC-HVDC under DC Line Fault, the fault fault current I that the trouble spot is injected under the condition of converter blocking _ShortCurve; t _FBe the moment of DC Line Fault generation; t _BBe the MMC locking moment; t _MFor F (t) reaches its peaked moment; t _TFor the descendant does not take AC circuit breaker action under any safeguard measure (i.e. artificial pressure arranges not locking of transverter) condition for transverter is set the moment occurs in DC Line Fault; I _MMaximal value for F (t); I _BFor at t _BThe value of moment G (t).

Embodiment

Step 1:MMC-HVDC system modelling

In PSCAD/EMTDC, set up the MMC system model of Practical Project, if the MMC of more different submodules only is consistent its other parameter of MMC-HVDC system, for example control system and PI parameter;

Step 2: arrange constantly different

According to requirement of engineering be set the different moment, comprise constantly t of DC Line Fault _F, the MMC locking is t constantly _BAnd the descendant occurs and do not take any safeguard measure for transverter is set in DC Line Fault, namely artificially forces to arrange the transverter moment t that AC circuit breaker does not move under the barring condition _T, depend on the time-delay of measuring system and the reaction time of protective device, general t _T=t _F+ 60ms;

Step 3: ask for the first current curve F (t)

The descendant occurs and does not take any safeguard measure for transverter is set in DC Line Fault; i.e. artificial pressure arranges not locking of transverter; emulation obtains injecting the first current curve F (t) of trouble spot; be that DC Line Fault generation descendant does not take any safeguard measure for transverter is set; namely artificial the pressure arranges under the condition of not locking of transverter, the fault current I that the trouble spot is injected under the MMC-HVDC system DC Line Fault _ShortCurve;

Step 4: ask for the second current curve G (t)

After DC Line Fault occurs, converter blocking, emulation obtains injecting the second current curve G (t) of trouble spot, namely under the condition of MMC-HVDC converter blocking under DC Line Fault, the fault current I that the trouble spot is injected _ShortCurve, wherein MMC is at t _BConstantly locking;

Step 5: calculate the first area S ₁

Calculating is from moment t _FTo moment t _TThe first current curve F (t) is carried out integration, calculate the first area S ₁

Step 6: calculate S ₂

Calculating is from moment t _FTo moment t _TThe second current curve G (t) is carried out integration, calculate second area S ₂

Step 7: calculate transverter DC Line Fault ride-through capability

Ask the first area S ₁With second area S ₂Ratio, be denoted as DFRTI among the present invention, namely calculate by following definition

$\mathrm{DFRTI}=\frac{S_1}{S_1}=\frac{{\∫}_{t_F}^{t_T}F\left(t\right)\mathrm{dt}}{{\∫}_{t_F}^{t_T}G\left(t\right)\mathrm{dt}}$

Wherein, DFRTI can represent the DC Line Fault ride-through capability of MMC, and this method also is applicable to the multilevel converter of other type.

The above; only for the better embodiment of the present invention, but protection scope of the present invention is not limited to this, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claim.

Claims (6)

1. computing method of weighing multilevel converter DC Line Fault ride-through capability is characterized in that, specifically may further comprise the steps:

Step 1: the system model of setting up the MMC-HVDC of Practical Project;

Step 2: system is arranged the different moment;

Step 3: DC Line Fault arranges under the condition of not locking of transverter after occuring, and emulation obtains injecting the first current curve F (t) of trouble spot;

Step 4: after DC Line Fault occurs, converter blocking, emulation obtains injecting the second current curve G (t) of trouble spot;

Step 5: calculate first integral area S ₁

Step 6: calculate second integral area S ₂

Step 7: calculate the first area S ₁With second area S ₂Ratio value representation transverter DC Line Fault ride-through capability.

2. a kind of computing method of weighing multilevel converter DC Line Fault ride-through capability according to claim 1, it is characterized in that, the described system model process of setting up the MMC-HVDC of Practical Project is: set up the MMC system model of Practical Project in electromagnetic transient simulation software PSCAD/EMTDC, and the parameter of MMC-HVDC systematic parameter, transformer and proportional integral PI parameter are consistent.

3. a kind of computing method of weighing multilevel converter DC Line Fault ride-through capability according to claim 1 is characterized in that, the described moment comprises constantly t of DC Line Fault _F, MMC locking t constantly _BMoment t with the AC circuit breaker action _Tt _T=t _F+ 60ms.

4. a kind of computing method of weighing multilevel converter DC Line Fault ride-through capability according to claim 3 is characterized in that, in the described step 5, calculate first integral area S ₁Method be to calculate from moment t _FTo moment t _TThe first current curve F (t) is carried out integration.

5. a kind of computing method of weighing multilevel converter DC Line Fault ride-through capability according to claim 3 is characterized in that, in the described step 6, calculate second integral area S ₂Method be to calculate from moment t _FTo moment t _TThe second current curve G (t) is carried out integration.

6. a kind of computing method of weighing multilevel converter DC Line Fault ride-through capability according to claim 1 is characterized in that step 7: the computing method of calculating transverter DC Line Fault ride-through capability are: ask the first area S ₁With second area S ₂Ratio be denoted as DFRTI, namely calculate by following definition:

$\mathrm{DFRTI}=\frac{S_1}{S_1}=\frac{{\∫}_{t_F}^{t_T}F\left(t\right)\mathrm{dt}}{{\∫}_{t_F}^{t_T}G\left(t\right)\mathrm{dt}}$

Wherein, DFRTI can represent the DC Line Fault ride-through capability of MMC, t _TThe moment of expression AC circuit breaker action, t _FThe expression DC Line Fault constantly.

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