CN102880511B - Embedded multi-microcontroller core switch chain structure and operating method thereof - Google Patents
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Abstract
The invention discloses an embedded multi-microcontroller core switch chain structure comprising at least two microcontroller cores. The microcontroller cores process data in a multi-microcontroller core system and are arranged according to static leakage current, and the smaller the static leakage current is, the toper the microcontroller cores are. The microcontroller cores are connected in series. The invention further discloses an operating method of the embedded multi-microcontroller core switch chain structure. Energy efficiency is improved under ultra-deep submicron process, so that effective utilization rate of energy sources such as batteries can be improved.
Description
Technical field
The present invention relates to chip system field on sheet, particularly relate to a kind of embedded multi-microcontroller core switch chain structure and method of work thereof.
Background technology
Many kernels refer to integrated two or more complete computing engines (kernel) in one piece of processor.The speed that the exploitation of multi-core technology only improves monokaryon chip can produce too much heat and cannot bring corresponding performance improvement, and previous processor products is exactly like this.Work with that speed in previous product, the heat that processor produces can exceed sun surface very soon.Even if do not have heat problem, its cost performance also makes us being difficult to accepting, and the slightly fast processor price of speed wants high a lot.
As shown in Figure 1, when a monokaryon improves frequency operation (raising operating rate), in time performing same task, power consumption can significantly increase but performance is not but greatly improved.If but changing frequency time double-core goes to perform same task into reduces, power consumption has no change, but performance--1,000,000 instructions (MIPS) per second but have great raising.But when manufacturing process is constantly being contracted to 40nm, 22nm, 14nm, 9nm, time even less, element leakage fails to be convened for lack of a quorum constantly to be increased, and electricity leakage power dissipation can be greater than more than 50% of total power consumption.On this basis, if when using double-core or multinuclear, energy efficiency (dynamic power/(dynamic power+electric leakage energy)) can reduce greatly.This also just means, if multi core chip is battery-powered, the effective rate of utilization of the energy content of battery will greatly reduce, and namely the electric leakage energy of the large multi-energy core sheet of battery is to consuming.
Individual comparison is done with prior art, as shown in table 1, when a monokaryon has worked two same task with frequency F time, use up time T, consume dynamic power Ed, and consume electric leakage energy be Elek, wherein suppose under Super deep submicron process, dynamic power consumption accounts for 40% of total power consumption, electricity leakage power dissipation accounts for 60% of general power, and the integration of power consumption to the time is energy, and corresponding dynamic power accounts for 40% of consumed gross energy, electric leakage energy accounts for 60% of consumed gross energy, and namely energy efficiency is Ed/ (Ed+Elek)=40%.When two core work complete same two tasks time, the frequency of operation of core is set for (1/n) F, so the time that double-core has all opened required task is nT/2, again because dynamic power consumption is proportional to cv
2f (wherein c is capacitive load, and v is chip operating voltage, and f is working frequency of chip), so double-core dynamic power consumption that work consumes is 2*cv
2(1/n) F, namely consumed dynamic power is Ed (energy is that power consumption is multiplied by the time), the same with dynamic power that monokaryon consumes, electric leakage energy ezpenditure is then n*Elek, total power consumption is that Ed adds n*Elek, energy efficiency is Ed/ (Ed+n*Elek), supposes that n equals 2, and energy efficiency is just 25%.That is, under Super deep submicron process, when double-core goes to process same thing with 1/2 of original frequency time, to consume dynamic power constant, performance (MIPS) is also constant, but electric leakage energy ezpenditure is double, causes energy efficiency almost to reduce half.
Table 1 monokaryon and double-core energy efficiency contrast form
| Frequency | Working time | Dynamic power consumes | Electric leakage energy ezpenditure | Total power consumption | Energy efficiency | |
| Monokaryon | F | T | Ed | Elek | Et | 40％ |
| Double-core | 1/2F | T | Ed | 2*Elek | 1.6*Et | 25％ |
Can draw from these group data, under sub-micro manufacturing process, along with open in the same time period more multinuclear go process multitask time, the result caused is exactly the further reduction of power consumption efficiency, in other words, along with Super deep submicron process is more toward small size development, multinuclear is opened work capacity efficiency simultaneously and also will be declined further, and this just means that energy utilization rate is more and more lower.
Summary of the invention
Instant invention overcomes the defect that multinuclear work capacity efficiency constantly declines under Super deep submicron process, propose a kind of embedded multi-microcontroller core switch chain structure and method of work thereof.
The present invention proposes a kind of embedded multi-microcontroller core switch chain structure, comprising:
At least two microcontroller cores, the data in its process multi-microcontroller core system;
Described microcontroller core is according to the large minispread of static leakage current, and the microcontroller core order that described static leakage current is less is more forward; Connected in series between described microcontroller core.
Wherein, the static leakage current size of described microcontroller core is obtained by described microcontroller core nude film test.
Wherein, described embedded multi-microcontroller core switch chain structure is applicable to Super deep submicron process node.
The invention allows for a kind of method of work of embedded multi-microcontroller core switch chain structure, comprise priority and judge operation, the operation of microprocessor core condition adjudgement, wake microprocessor core operation up, turn off microprocessor core operation.
Wherein, described priority judgement operation comprises:
Steps A 1: in multi-microcontroller core system whenever there is interrupt event, anomalous event or task, described multi-microcontroller core system judges the priority of described interrupt event, anomalous event or task;
Steps A 2: if described priority is the highest and urgently processes, wake microprocessor core operation described in described multi-microcontroller core system performs up; Otherwise described multi-microcontroller core system performs the operation of described microprocessor core condition adjudgement.
Wherein, described microprocessor core condition adjudgement operation comprises:
Step B1: when there is interrupt event, anomalous event or task, described multi-microcontroller core system judges whether to exist in the multiple described microprocessor core in described multi-microcontroller core system at least one kernel and is in and powers on and not busy duty;
Step B2: if exist, described interrupt event, anomalous event or task stored in system wait list, wait pending by described multi-microcontroller core system; If do not exist, then perform and wake microprocessor core operation up.
Wherein, wake microprocessor core operation described in up to comprise:
Step C: described multi-microcontroller core system wake up described microprocessor core put in order upper first turn off microprocessor core process described in interrupt event, anomalous event or task.
Wherein, present microprocessor core performs the operation of described shutoff microprocessor core after processing interrupt event, anomalous event or task; Described shutoff microprocessor core operation comprises:
Step D1: described multi-microcontroller core system judges whether described system wait list is empty;
Step D2: if described system wait list is empty, described multi-microcontroller core system then turns off current described microprocessor core; If not empty, then step D3 is performed;
Step D3: described multi-microcontroller core system to judge except described present microprocessor whether other microprocessors are in and powers on and not busy duty;
Step D4: if result is yes, then turn off described present microprocessor core; If the result is negative, then step D5 is performed;
Step D5: described multi-microcontroller core system judges that whether there are other microprocessor cores before described present microprocessor nuclear arrangement order is in off state;
Step D6: if exist, then described multi-microcontroller core system turns off described present microprocessor core and wakes microprocessor core operation described in execution up; If do not exist, then keep described present microprocessor core power-up state, by interrupt event, anomalous event or task in system wait list described in the process of described present microprocessor core.
The present invention propose a kind of newly under Super deep submicron process based on the embedded multi-microcontroller nuclear structure of very high energies efficiency, can under Super deep submicron process, and when having multinuclear to open work simultaneously, improve energy efficiency greatly, solve multinuclear under Super deep submicron process to open work hourglass electric flux simultaneously and consume excessive problem, thus battery equal energy source effective rate of utilization is improved greatly.
Accompanying drawing explanation
Fig. 1 is performance and the power consumption comparison diagram of monokaryon and double-core in prior art.
Fig. 2 is the present invention's embedded multi-microcontroller core switch chain structural representation.
Fig. 3 is the circuit diagram of each zone bit in the present embodiment.
Fig. 4 is the process flow diagram that priority judges operation.
Fig. 5 is the process flow diagram of microprocessor core condition adjudgement operation.
Fig. 6 is the process flow diagram turning off microprocessor core operation.
Fig. 7 is the switch chain structural integrity schematic flow sheet of the present embodiment.
Embodiment
In conjunction with following specific embodiments and the drawings, the present invention is described in further detail.Implement process of the present invention, condition, experimental technique etc., except the following content mentioned specially, be universal knowledege and the common practise of this area, the present invention is not particularly limited content.
What table 2 showed is a utilization rate based on the typical dynamic instruction of ARM kernel.In all instructions, the dynamic utilization rate of data mobile is 43%, control flow check is 23%, other some as, arithmetical operation, relatively, the instruction of logical operation and so on accounts for 34% of dynamic utilization rate, and ALU (ALU) is the parts performing various arithmetic sum logical operation in computing machine.The basic operation of arithmetical unit comprise add, subtract, multiplication and division arithmetic, with or, the logical operation such as non-, XOR, and displacement, to compare and the operation such as transmission, also known as arithmetic logical unti (ALU).Visible, in ARM kernel, the dynamic utilization rate of ALU instruction only accounts for the half of data mobile and control flow check instruction summation.Because the operation of ALU instruction can relate to the work of a large amount of logic gate, so dynamic power consumption can be far longer than the dynamic power consumption that data mobile and control flow check instruction consume, for the chip based on ARM kernel, only in the event of 34%, namely 1/3 time in, its dynamic power consumption just can reach peak value, within other 2/3 time, ARM ALU is in static state, only has the consumption of electric leakage energy.
Table 2 is based on the utilization rate of the typical dynamic instruction of ARM kernel
Embedded multi-microcontroller core switch chain structure of the present invention as shown in Figure 2, comprises at least two microprocessor cores.Multi-microprocessor core in order logic serial links together.Order is according to the large float of each core static leakage current on chain.After the microprocessor core that leakage current is large comes, otherwise before the little microprocessor core of leakage current comes.The size of leakage current is determined by industrial manufacturing process, so the chain sequence of each multi core chip is likely different, this is because the process shifts in manufacture process causes, and this phenomenon is particularly outstanding under Super deep submicron process.The leakage current of each microprocessor core can measure when chip dies is tested, thus determines multinuclear order, and order determines the order that core is opened and turned off.After multimicroprocessor core chip in multi-microcontroller core system powers on, first microprocessor core is first unlocked, other microprocessor core is in off state, when the ALU of first microprocessor core is not in running status, characterize first microprocessor core dynamic power consumption and do not reach peak value, now system has come other event or interruption or abnormal when urgently processing, and operating system (OS) can open second microprocessor core on chain to process this event; Otherwise (urgently not processing), this event can be placed in the system wait list of system, until first microprocessor core enter idle state after (processing current event), operating system can be taken out this event again and be transferred to first microprocessor core process from system wait list.Switch chain structure of the present invention ensure that CPU reduces the quantity of the microprocessor core on chain at power-up state while normally working as far as possible, maximally ensures that the ALU of the microprocessor core powered on is under the state of fully work, can reduce leakage power like this.
As shown in Figure 2 according to microprocessor core static leakage current size, N number of microprocessor core is lined up 1st kernel, 2nd kernel, 3th kernel, until N number of microprocessor core, get up by logical order link then.
Preferably, dynamic peak value state is introduced in the present embodiment, dynamic peak value state refers to CPU (central processing unit) (CPU), and namely multi-microcontroller core system microprocessor core portion is in arithmetical logic operating process, is namely by under the duty frequently called in ALU instruction.Preferably, a flag (Fu is set in the present embodiment, i.e. Fully Utilized), as shown in Figure 3, be used for characterizing present microprocessor core and whether be in ALU busy state, by this flag Fu, operating system (os) just can judge whether present microprocessor core is in the stage of the busy operation of ALU instruction intuitively.When Fu is in noble potential " 1 ", represents this microprocessor core and be in the ALU instruction busy operational phase; If when Fu is in electronegative potential " 0 ", represents this microprocessor and be in ALU idle condition.A zone bit PWR is also set in the present embodiment, is used to indicate present microprocessor core and whether powers on or power-off.When PWR is noble potential " 1 ", represents this microprocessor core and be in power-up state; If when PWR is electronegative potential " 0 ", represents this microprocessor core and be in off-position.In this fact Example, on chain, each microprocessor core can export the signal of a non_fu, this signal be Fu negate after the result of PWR on logical and, wherein! Fu refers to the value of Fu (fullyutilized) negate.Show during non_fu=1 that this microprocessor core is in power on and the state of the not busy work of ALU, namely dynamic power consumption is not in peak value.Show during non_fu=0 that this microprocessor core is in turn off or power on and the state of the busy work of ALU.Non_fu_comb is the non_fu logical OR signal together that all microprocessor cores export, as non_fu_comb=1, representing on chain has at least a microprocessor core to be in the not busy duty of ALU, as non_fu_comb=0, represent the microprocessor core on chain or be in power-off state, ALU on microprocessor core is in busy duty, and namely dynamic power consumption is in peak value.
The method of work of embedded multi-microcontroller core switch chain structure of the present invention, comprises priority and judges operation, the operation of microprocessor core condition adjudgement, wakes microprocessor core operation up, turns off microprocessor core operation.
Wherein, as shown in Figure 4, priority judgement operation comprises:
Steps A 1: in multi-microcontroller core system whenever there is interrupt event, anomalous event or task, multi-microcontroller core system judges the priority of interrupt event, anomalous event or task;
Steps A 2: if priority is the highest and urgently processes, multi-microcontroller core system performs and wakes microprocessor core operation up; Otherwise multi-microcontroller core system performs the operation of microprocessor core condition adjudgement.
Wherein, as shown in Figure 5, the operation of microprocessor core condition adjudgement comprises:
Step B1: when there is interrupt event, anomalous event or task, multi-microcontroller core system judges whether to exist in the multi-microprocessor core in multi-microcontroller core system at least one kernel and is in and powers on and not busy duty;
Step B2: if exist, interrupt event, anomalous event or task stored in system wait list, wait pending by multi-microcontroller core system; If do not exist, then perform and wake microprocessor core operation up.
Wherein, wake microprocessor core operation up to comprise:
Step C: multi-microcontroller core system wakes microprocessor core up and to put in order upper first microprocessor core process interrupt event turned off, anomalous event or task.
Wherein, as shown in Figure 6, present microprocessor core performs after processing interrupt event, anomalous event or task and turns off microprocessor core operation; Turn off microprocessor core operation to comprise:
Step D1: multi-microcontroller core system judges whether system wait list is empty;
Step D2: if system wait list is empty, multi-microcontroller core system then turns off present microprocessor core; If not empty, then step D3 is performed;
Step D3: multi-microcontroller core system to judge except present microprocessor whether other microprocessors are in and powers on and not busy duty;
Step D4: if result is yes, then turn off present microprocessor core; If the result is negative, then step D5 is performed;
Step D5: multi-microcontroller core system judges that whether there are other microprocessor cores before present microprocessor nuclear arrangement order is in off state;
Step D6: if exist, then multi-microcontroller core system turns off present microprocessor core and performs and wakes microprocessor core operation up; If do not exist, then keep present microprocessor core power-up state, wait for interrupt event, anomalous event or the task in list by present microprocessor core disposal system.
Being illustrated in figure 7 the present invention's embedded multi-microcontroller core switch chain arrangement works process flow diagram, is below complete workflow.
The first step, when come in multi-microcontroller core system an interruption, exception or task time, operating system (OS) first judges that its priority is whether the highest and urgently processes;
Second step, if this interrupts, the priority of exception or task is the highest and urgently process, no matter whether non_fu_comb signal equals 1, operating system (OS) portion will travel through whole switch chain in order, newly opens or wake up the microprocessor core of first power down on chain to process this interruption, exception or task (in order to interrupt response performance);
3rd step, if this interrupts, the priority of exception or task is not the highest and urgently do not process, operating system (OS) judges whether non_fu_comb signal waits and 1, if equal 1, have at least a microprocessor core to be in expression system and power on and the state of the not busy work of ALU, now OS is just put into this interruption, exception or task in system wait list (waiting list); If be not equal to 1, represent that the ALU circuit part of all microprocessor cores that open on chain is all fully utilized, at this moment operating system (OS) will travel through whole switch chain in order, newly open or wake up the microprocessor core of first power down on chain to process this interruption, exception or task;
4th step; after the microprocessor core opened or wake up processes interruption, exception or task; the interruption that OS goes check system to wait in list whether to have process or not again, exception or task; if do not had; OS can turn off this microprocessor core, can reduce electricity leakage power dissipation like this thus increase energy efficiency.If be not empty in system wait list, namely have the interruption of process, exception or task or not, now do the 5th step;
5th step, OS judges to remove again ought up till now microprocessor core, the situation of non_fu_comb signal, if equal 1, illustrate that except this microprocessor core, also have a microprocessor core to be at least in powers on and the not busy duty of ALU, this time, OS can turn off this microprocessor core, can reduce electricity leakage power dissipation like this thus increase energy efficiency; If be not equal to 1, illustrate that any one except this microprocessor core microprocessor core of powering on is all the state being in the busy work of ALU;
6th step, now OS judges whether the microprocessor core on chain before this microprocessor core order has the microprocessor core being in off state, if had, then turn off this microprocessor core, and the microprocessor core newly opening or wake up first power down on chain is to process that this interrupts, exception or task; If no, then do not descend this interruption of electric treatment, exception or task, the 4th step after finishing on get back to, judge whether system wait list is empty;
The present embodiment is multi-microcontroller core system when just powering on and ALU is accessed frequently, it is not the highest interrupt event that chip exterior has carried out a priority, when second microprocessor core at Processing tasks and ALU is part-load time, having carried out again a priority is not the highest anomalous event, has carried out again a task that priority is the highest after a while.
Here is the whole detailed step of this event of process:
The first step, multi-microcontroller core system powers on, and has spent a period of time, and now chip exterior has carried out an interrupt event.
Second step, judges whether this priority is the highest and urgently processes.
3rd step, result is non-post, judges whether non_fu_comb signal equals 1;
4th step, non_fu_comb signal equals 0, and representative now all microprocessor cores powered on all is in ALU by frequent utilization state, and operating system (OS) will open microprocessor core 2, processes this event.
5th step, now carrys out again an event, judges whether its priority is the highest and urgently processes.
6th step, result is non-post, judges whether non_fu_comb signal equals 1
7th step, non_fu_comb signal equals 1, and representative now has at least a microprocessor core to be in ALU to be not exclusively utilized state, and OS will be put into this event in system wait list.
8th step, now carrys out again an event, judges whether its priority is the highest and urgently processes.
9th step, if this Event Priority is the highest and urgently processes, no matter whether non_fu_comb signal equals 1, all newly will open microprocessor core 3 to process this event.
9th step, after microprocessor core 2 processes task prior to microprocessor core 3 and microprocessor core 1, OS judges whether wait for event in addition in system wait list, found that a untreated event in addition.
Tenth step, now OS judges whether non_fu_comb signal equals 1, result is that non-post (represents microprocessor core 1 and is all in frequent accessed state with the respective ALU of microprocessor core 2, dynamic power consumption reaches the highest), so microprocessor core 2 does not descend this event in electric treatment system wait list;
11 step, after microprocessor core 3 processes task, OS judges that system wait list is as empty, so turn off microprocessor core 3;
12 step, after microprocessor core 2 processes task, OS judges that system wait list is as empty, so turn off microprocessor core 2;
13 step, after microprocessor core 1 processes task, OS judges system wait list is as empty, now determines whether will turn off microprocessor core 1 by OS, makes chip be in super low-power consumption pattern, or continues to keep "on" position (standby).
Protection content of the present invention is not limited to above embodiment.Under the spirit and scope not deviating from inventive concept, those skilled in the art can to change and advantage be all included in the present invention, and be protection domain with appending claims.
Claims (3)
1. an embedded multi-microcontroller core switch chain structure, is characterized in that, comprising:
At least two microcontroller cores, the data in its process multi-microcontroller core system;
Described microcontroller core is according to the large minispread of static leakage current, and the microcontroller core order that described static leakage current is less is more forward; Connect by sequence serial logic between described microcontroller core;
Described embedded multi-microcontroller core switch chain structure is applicable to Super deep submicron process node.
2. embedded multi-microcontroller core switch chain structure as claimed in claim 1, is characterized in that, the static leakage current size of described microcontroller core is obtained by described microcontroller core nude film test.
3. a method of work for embedded multi-microcontroller core switch chain structure, is characterized in that, comprises priority and judges operation, the operation of microprocessor core condition adjudgement, wakes microprocessor core operation up, turns off microprocessor core operation;
Wherein,
Described priority judgement operation comprises:
Steps A 1: in multi-microcontroller core system whenever there is interrupt event, anomalous event or task, described multi-microcontroller core system judges the priority of described interrupt event, anomalous event or task;
Steps A 2: if described priority is the highest and urgently processes, wake microprocessor core operation described in described multi-microcontroller core system performs up; Otherwise described multi-microcontroller core system performs the operation of described microprocessor core condition adjudgement;
Described microprocessor core condition adjudgement operation comprises:
Step B1: when there is interrupt event, anomalous event or task, described multi-microcontroller core system judges whether to exist in the multiple described microprocessor core in described multi-microcontroller core system at least one kernel and is in and powers on and not busy duty;
Step B2: if exist, described interrupt event, anomalous event or task stored in system wait list, wait pending by described multi-microcontroller core system; If do not exist, then perform and wake microprocessor core operation up;
Described wake up microprocessor core operation comprise:
Step C: described multi-microcontroller core system wake up described microprocessor core put in order upper first turn off microprocessor core process described in interrupt event, anomalous event or task;
Present microprocessor core performs the operation of described shutoff microprocessor core after processing interrupt event, anomalous event or task; Described shutoff microprocessor core operation comprises:
Step D1: described multi-microcontroller core system judges whether described system wait list is empty;
Step D2: if described system wait list is empty, described multi-microcontroller core system then turns off described present microprocessor core; If not empty, then step D3 is performed;
Step D3: described multi-microcontroller core system to judge except described present microprocessor whether other microprocessors are in and powers on and not busy duty;
Step D4: if result is yes, then turn off described present microprocessor core; If the result is negative, then step D5 is performed;
Step D5: described multi-microcontroller core system judges that whether there are other microprocessor cores before described present microprocessor nuclear arrangement order is in off state;
Step D6: if exist, then described multi-microcontroller core system turns off described present microprocessor core and wakes microprocessor core operation described in execution up; If do not exist, then keep described present microprocessor core power-up state, by interrupt event, anomalous event or task in system wait list described in the process of described present microprocessor core.
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