CN102855199A - Data processing device and data processing arrangement - Google Patents
Data processing device and data processing arrangement Download PDFInfo
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- CN102855199A CN102855199A CN2012102146047A CN201210214604A CN102855199A CN 102855199 A CN102855199 A CN 102855199A CN 2012102146047 A CN2012102146047 A CN 2012102146047A CN 201210214604 A CN201210214604 A CN 201210214604A CN 102855199 A CN102855199 A CN 102855199A
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Abstract
The invention discloses a data processing device and a data processing arrangement. The data processing device is described with a memory and a first and a second data processing component. The first data processing component comprises a control memory comprising, for each memory region of a plurality of memory regions of the memory, an indication whether a data access to the memory region may be carried out by the first data processing component and a data access circuit configured to carry out a data access to a memory region of the plurality of memory regions if a data access to the memory region may be carried out by the first data processing component; and a setting circuit configured to set the indication for a memory region to indicate that a data access to the memory region may not be carried out by the first data processing component in response to the completion of a data access of the first data processing component to the memory region.
Description
Technical field
Embodiment relates generally to data processing equipment and data processing equipment.
Background technology
In data handling system, usually need to be between different parts (for example different processor) (for example between central processing unit CPU and coprocessor) swap data, perhaps also swap data between the various process that operates on the same processor.
Can be written to storer by means of data that will be to be exchanged and between different entities (it can comprise the software process of being carried out by processor or hardware component (for example coprocessor)) swap data, described storer can be by all entities access (being shared storage).
In this case, usually must be provided for guaranteeing for the synchronization of access of data and avoid the mechanism of data corruption, if for example entity another entity finish its to the access of shared storage before the access shared storage just data corruption may appear.
Therefore, provide efficient access (for example allowing to carry out fast data exchange by means of storer), to be used for control be desirable to the mechanism of the access of storer (shared storage that for example is used for exchanges data).
Summary of the invention
According to an aspect of the present invention, provide a kind of data processing equipment.Described data processing equipment comprises: the storer that comprises a plurality of memory areas; The first data processor; Control store, whether it comprises for each memory area in described a plurality of memory areas and shows and can carry out indication to the data access of this memory area by the first data processor; And second data processor; Wherein, the first data processor comprises: check circuit, and whether it is configured to can be by the data access of the first data processor execution to this memory area for this memory area inspection based on the described indication corresponding to memory area; The data access circuit, it is configured to carry out the data access to this memory area in situation about can be carried out by the first data processor the data access of a memory area in described a plurality of memory areas; And circuit is set, it is configured in response to the first data processor the finishing of data access of memory area be arranged cannot be by the data access of the first data processor execution to this memory area to show corresponding to the described indication of this memory area; And wherein, the described indication that the second data processor is configured to arrange corresponding to memory area can be carried out the data access to this memory area to show the first data processor.
A kind of data processor of data processing equipment is provided according to a further aspect in the invention.Described data processor comprises: control store, and whether it comprises for each memory area in a plurality of memory areas and shows and can carry out indication to the data access of this memory area by the first data processor; Check circuit, whether it is configured to can be by the data access of the first data processor execution to this memory area for this memory area inspection based on the described indication corresponding to memory area; The data access circuit, it is configured to carry out the data access to this memory area in situation about can be carried out by the first data processor the data access of a memory area in described a plurality of memory areas; Circuit is set, and it is configured in response to the first data processor the finishing of data access of memory area be arranged cannot be by the data access of the first data processor execution to this memory area to show corresponding to the described indication of this memory area.
According to another aspect of the invention, provide a kind of data processing equipment.Described data processing equipment comprises: the first memory that comprises a plurality of data objects; The second memory that comprises a plurality of data storage cells, wherein the number of data storage cell is less than the number of data object; Data processing circuit, it is configured to for access described a plurality of data storage cell about the status information of described a plurality of data objects; Select circuit, it is configured to select data object according to pre-defined rule from described a plurality of data objects; Memory circuit, it is configured to the status information about the selected data object is stored in the data storage cell of described a plurality of data storage cells.
Description of drawings
In the accompanying drawings, identical Reference numeral refers to identical parts usually all the time in different views.Accompanying drawing is not necessarily pro rata, but usually focuses on the explanation principle of the present invention.In the following description, with reference to following accompanying drawing various embodiment are described, wherein:
Fig. 1 illustrates the data processing equipment according to an embodiment.
Fig. 2 illustrates the data processing equipment according to an embodiment.
Fig. 3 illustrates the data processing equipment according to an embodiment.
Fig. 4 illustrates the process flow diagram according to an embodiment.
Fig. 5 illustrates the storer according to an embodiment.
Fig. 6 illustrates data processing equipment.
Fig. 7 illustrates the mapping according to the status information of an embodiment.
Embodiment
Following detailed description is with reference to accompanying drawing, and described accompanying drawing illustrates wherein by the mode that illustrates can put into practice detail of the present invention and embodiment.These embodiment are described so that those skilled in the art can put into practice the present invention with enough details.In the situation that do not deviate from scope of the present invention, can utilize other embodiment and can make structure, logic and change electricity.Various embodiment are not necessarily mutually exclusive, because some embodiment can be combined to form new embodiment with one or more other embodiment.
In data handling system, may need handle (is that data produce entity by an entity, for example hardware component or operate in process on the processor) to be supplied to another entity (be the data consumption entity for the data that generate, another hardware component or operate in process on the processor for example, described processor may be the same processor that service data generates entity).It should be noted that, described another entity (being the data consumption entity) can or also produce entity for described data for third communication partner (i.e. the 3rd entity) and also be operating as data generation entity, produces entity and data consumption entity thereby whole two entities all are operating as data.
This is illustrated in Fig. 1.
Fig. 1 illustrates the data processing equipment 100 according to an embodiment.
Can produce swap data 103 between entity 101 and the data consumption entity 102 in data by means of shared storage 104.Data produce entity 101 data 103 are written in the shared storage 104, and data consumption entity 102 is from shared storage 104 reading out datas 103.Data 103 for example can be for example to be produced by data that entity 101 produces (for example generating) continuously and the part (shown in three points on data 103 left sides among Fig. 1 and right side) of the data stream of being consumed by data consumption entity 102.
Shared storage 104 can be regarded as the path 10 8 between implementation data generation entity 101 and the data consumption entity 102.
Memory area 105,106,107 layout can be described by I/O context (context), and it can be regarded as the context of path 10 8.Produce entity 101 and consume entity 102 and can comprise respectively the interface 109,110 that joins with this context dependent.
For instance, data produce entity 101 with the data 103(part of data stream for example) be written to the first memory zone 105 of storer 104, and data consumption entity 102 reads described data from first memory zone 105.Be written to memory area 105 for fear of data consumption entity 102 fully in data, 106,107 before from memory area 105,106,107 read described data (and therefore read incomplete and therefore can destructible data), perhaps avoid data to produce entity 101 at memory area 105,106,107 are write new data before suitably reading by data consumption entity 102, can lock memory area 105,106,107, namely can lock for each memory area 105,106,107 access produces the exclusive access of entity 101 or data consumption entity 102 to allow data.
Can use a plurality of memory areas 105,106,107 to carry out simultaneously with read (another memory area from described memory area reads) that write (being written to a memory area in the described memory area) and data consumption entity 102 that allow data to produce entity 101.
Data generate entity 101 and/or data consumption entity 102 for example can be the part of computer system, and can be coupled to storer 104 by means of the system computer bus of described computer system.According to an embodiment, data produce entity 101 and/or data consumption entity 102 comprises interface circuit, it also is known as bus master interface, by means of described bus master interface come swap data 103(for example its control via the exchange of the data 103 of storer 104), and by described bus master interface, can produce between entity 101 and the data consumption entity 102 in data and exchange synchronizing information, for example be used for guaranteeing that memory area 105,106,107 was produced the information that entity 101 writes (vice versa) by data before being read by data consumption entity 102.
Describe with reference to Fig. 2 below and have the data processing equipment that can form this bus master interface and/or implement the parts of this bus master interface.
Fig. 2 illustrates the data processing equipment 200 according to an embodiment.
The first data processor 201 comprises check circuit 207, and whether it is configured to check based on the indication 206 corresponding to this memory area 204 for memory area 204 can be by the data access of the first data processor 201 execution to this memory area 204.
The first data processor 201 also comprises data access circuit 208, and it is configured to carry out the data access to this memory area 204 in situation about can be carried out by the first data processor 201 data access of a memory area in a plurality of memory areas 204.
The first data processor 201 also comprises circuit 209 is set, it is configured to finish the data access of memory area 204 in response to the first data processor 201 and indication 206 corresponding to this memory area 204 is set, and can not carry out the data access to this memory area 204 to show the first data processor 201.
Should be noted that showing also can be the indication that shows to the access of memory area 204 executing datas to the indication of memory area 204 executing datas access in one embodiment.
The data access that depends on the first data processor 201 is write-access or read access, is write-access if the first data processor 201 can produce the described data access of entity 101(corresponding to data) if or the described data access of data consumption entity 102(be read access).It should be noted that, the second data processor can have the framework that is similar to the first data processor, and can produce entity 101 corresponding to data in the situation that data access is read access, perhaps in the situation that data access be write-access can be corresponding to data consumption entity 102.
The first data processor can also comprise data processing circuit 210, and (treated) data that it for example is configured to provide with being stored in by data access in the storer 203 perhaps are configured to process the data that read from storer 203 by data access.
According to an embodiment, memory area 204 can be regarded as data buffer, and each data buffer is corresponding to data block (for example being stored in the corresponding memory area 204).According to an embodiment, read or write to memory area 204 data block that is stored in this memory area 204 from memory area 204.In other words, an embodiment can be regarded as based on following concept: data are with synchronous (for example aspect the exclusive access of the first data processor 201 or the second data processor 202) atomic unit (be respectively each memory area 204 or corresponding to each data block of each memory area 204) exchange.These atomic units are known as memory area below.For example can promote manipulation to these memory areas by controller.
According to an embodiment, in other words, check circuit checks whether the first data processor has the access right for memory area, and after finishing data access, circuit is set discharges access right by the indication that correspondingly arranges corresponding to described memory area.
Can be by means of signal/message (for example interrupt) with signal to check circuit 207 notices for example by circuit 209 being set or by the content changing of the control store 205 of the second data handling component 202 execution, thereby check circuit 207 does not need initiatively to check the change of control store 205, does not for example carry out the active poll to control store 205.Described signal for example transmits and is carried out by signal transfer circuit 213, and it can be disposed in the first data handling component 201 or the second data handling component 202 with control store 205.
According to an embodiment, can transmit additional parameter with the data of each memory area 204 that is associated with corresponding memory area 204 (perhaps accordingly the data in being stored in memory area 204).
According to an embodiment, but the hierarchy memory area concept makes it possible to efficient still implements for the necessary basis facility of handling each memory area 204 neatly.
In one embodiment, " circuit " can be understood to the logic enforcement entity of any kind, and it can be the processor that special circuit or execution are stored in the software in storer, firmware or its any combination.Therefore, in one embodiment, " circuit " can be hard-wired logic or Programmable Logic Device, and programmable processor for example is such as microprocessor (such as complex instruction set computer (CISC) (CISC) processor or Reduced Instruction Set Computer (RISC) processor)." circuit " can also be the processor of executive software, and described software for example is the computer program of any kind, such as the computer program of the virtual machine code of example such as Java and so on.According to an alternative embodiment, the enforcement of any other kind of the corresponding function that will be described in greater detail below also can be understood to " circuit ".
According to an embodiment, the second data processor is configured to arrange the indication corresponding to memory area, showing that the first data processor can carry out the data access to this memory area, carry out data access to this memory area to be used for for example indicating the first data processor.
The first data processor can also comprise for carrying out the memory interface of exchanges data with storer.Described memory interface for example can be the part of interface 211.For instance, it can be the part of data access circuit 208.
The first data processor for example is configured to according to the data access of predefined procedure execution to memory area.
In one embodiment, the first data processor comprises the input end that is configured to receive indication.
For instance, the second data processor is the processor of operating software process, and wherein by the setting of described software process initiation corresponding to the indication of memory area, can carry out the data access to this memory area to show the first data processor.
In one embodiment, described interface is configured to the data retransmission that reads from storer in the process of data access perhaps to provide and will be written to the data of storer in the process of data access to data processing circuit 210.
Memory area for example is the impact damper that distributes in shared storage.
Memory area for example has equal size.
Described data processing equipment for example is computing machine.
In one embodiment, show that can carry out indication to the data access of memory area by the first data processor is to show that the data block size of the data block that is stored in the described memory area is greater than zero standard.
Show that the indication that can not be carried out the data access of memory area by the first data processor for example is to show that the data block size of the data block that is stored in the described memory area is zero standard.
In one embodiment, for at least one memory area, control store is also stored at least one parameter value except described indication, according to described at least one parameter value, will or process the data that are stored in the described memory area by the access of the first data processor executing data.
Each feature that should be noted that the second data processor 202 can comprise each feature of aforesaid the first data processor 201, and vice versa.In other words, described data processing equipment can comprise two the data processing element with above-mentioned feature that communicate with one another.
Below with reference to the data processing equipment of Fig. 3 description according to an embodiment.
Fig. 3 illustrates the data processing equipment 300 according to an embodiment.
The storer 308 of data processing equipment 300 is connected to system bus 307.
Accelerator will speed up device kernel 304 from interface 306 and is connected to local general purpose controller 303.
In one embodiment, described data processing equipment also comprises central synchronization hardware 310.
The accelerator main interface is used to 302 couples of storer 308(of accelerator nuclear, and it can comprise one or more shared storage equipment) read and write-access (being that all read and write-access in one embodiment), and be used for sending message by system bus 307 to the software part of data processing equipment 300.It can also support with the data of other hardware componenies of data processing equipment 300 or software part synchronous.
Accelerator main interface 305 can be regarded as configurable general grand, and its a plurality of (even owning) hardware accelerator that can be used as computer system is examined the bus master interface in 302.Can regulate individually general parameter for each accelerator main interface example, and can be fixing after synthetic.Every other parameter can be by software definition when moving.
Accelerator main interface 305 comprises multithreading bus master controller 311, also is useful on alternatively the special register set in the synchronous additional logic of memory area (comprising automatic message circuit 312 and direct synchronizing circuit 313) and a plurality of register 309.Automatic message circuit 312 for example is connected to the automatic message arbiter circuit 314 of data processing equipment 300.
Accelerator main interface 305 has several ports, and it will speed up device main interface 305 and is connected to accelerator kernel 304, automatic message arbiter circuit 314(it is connected to the message queue of local general purpose controller 303), the central synchronization hardware 310 of system bus 307 and data processing equipment 300.
Req: be used for asking access to system bus 307 by bus master controller 311.
Req_spec: be used for stipulating type to the access of system bus 307 by bus master controller 311.This signal is stated therein in cycle of req and is carried block address, bunch address and read/write designator.Within the cycle of following after request, it carries burst-length.
Reqd: enable the request for each individual data stage of burst transaction.This is vital when the burst that should stop having begun.
Grant: it is licensed to the access of system bus 307 to bus master controller 311 notice to be used for signal.
Grantd: to the dominant force (master) (being bus master controller 311 in this example) of the request of sending license readout data bus circuit (lane) rdata or data writing bus line wdata, and define described data and appear at cycle on the bus.
Maddr: the storage address that is used for predetermined memory 308.
Wdata: be used for being written to data transmission in the storer 308 to system bus 307 by bus master controller 311.
Byteen a: part that is used for activating storer 308 by bus master controller 311.
Rdata: the data communication device that is used for having read from storer 308 is crossed system bus 307 and is transferred to bus master controller 311.
Wresp: signal and write finishing of transmission.
Io_trigger_command: be used for initiating input and output (I/O) operation (for example data access, such as write-access or the read access to storer 308) of bus master controller 311 by accelerator kernel 304.
Io_trigger_valid: be used for signaling by accelerator kernel 304, the initiation signal that operates for I/O is effective.
Data_chunk_size: be used for showing the data volume that inputs or outputs in the process of the I/O operation of initiating, the i.e. size of data burst by accelerator kernel 304.
Address_offset: be used for skew in the predetermined memory zone 315 by accelerator kernel 304, in this skew place, the data that will input or output begin in described memory area.In one embodiment, in the situation that system bus message, this signal can be used to message data.
Last_command: show that current I/O order is last the I/O order for the current storage zone.
Io_trigger_ack: be used for confirming the initiation (namely triggering) of I/O operation by bus master controller 311.
Read_data: be used for the data transmission that reads from storer 308 to accelerator kernel 304 by bus master controller 311.
Read_data_valid: be used for showing by bus master controller 311, the data of transmitting via read_data are effective.
Write_data_req: be used for the I/O operation, to be written to the data of storer 308 from 304 requests of accelerator kernel by bus master controller 311.
Write_data: be used for being written to the data transmission of storer 308 to bus master controller 311 by accelerator kernel 304.
Buffer_complete: be used for showing that by bus master controller 311 final I/O operation about memory area 315 (for example write data into memory area 315 or from memory area 315 reading out datas) finishes.
Bc_ctx: current buffer_complete signal for the contextual index of I/O.
Bc_bufx_phys: current buffer_complete signal for control store in the index of parameter register set.
Auto_msg_full: be used for showing that by automatic message circuit 312 its impact damper that is used for automatic message to be sent is full.
Auto_msg_din: be used for the content of the automatic message that signal will send by automatic message circuit 312 to automatic message circuit 312 notice.
(perhaps being any number in other embodiments) configurable I/O context can be arranged up to eight kinds, to be used in the same instance of accelerator main interface 305, using different I/O patterns (for example stream send pattern or random access mode), different I/O direction and multiple other different parameters, wherein be useful on the special I/O context of transmitting system bus message.Should be noted that in the situation that a plurality of accelerator main interfaces 305 are arranged in the data handling system 301, can be for this I/O context of each example definition of the accelerator main interface 305 in the data handling system 301.
Every kind of I/O context is by the set representative of the parameter of describing the contextual attribute of this I/O.Although some in these parameters can be fixed when the design of accelerator main interface 305, other parameters can configuration when operation.Configurable I/O context parameters and memory region parameter are mapped to the set of the register field of register 309 when operation, its can by software (namely by the local general purpose controller 303 of accelerator 301 by accelerator nuclear 302 from interface 306) write, perhaps can be write by hardware (namely by accelerator kernel 304 or by accelerator main interface 305).For instance, register 309 comprises corresponding to the contextual set of registers 316 of every kind of I/O for accelerator 302 definition.Set of registers 316 for example comprises I/O context register (it comprises the register field of storage I/O context parameters) and is used for storage corresponding to the register of the contextual memory region parameter of this I/O.
Should be noted that as for register 309 mention, in Method at Register Transfer Level (RTL) was implemented, the I/O context register can be that accelerator is from the part of interface model.
Various I/O contexts can be used simultaneously, thereby also can handle simultaneously a plurality of input and output data transmission according to staggered mode even have the single accelerator nuclear 302 of the only single instance of accelerator main interface 305.This is illustrated in Fig. 4.
Fig. 4 illustrates the process flow diagram 400 according to an embodiment.
In this example, bus master controller 311 is carried out and is numbered three threads of 0,1 and 2, and wherein each thread uses the I/O context of himself, and it is to be defined by the I/O context register corresponding to the contextual set of registers 316 of this I/O.
Figure 40 0 illustrates the data stream (for example comprising connection wdata, rdata of going to system bus 307 etc.) on the FPDP of data stream (for example comprise and connect io_trigger_command etc.) on the I/O command port of bus master controller 311 and bus master controller 311.
Via the I/O command port, five orders 401,402,403,404 and 405 are given bus master controller 311.
According to the first order 401, will read from storer 308/write the first data 406 to storer 308.According to the second order 402, will read from storer 308/write the second data 407 to storer 308.According to the 3rd order 403, will read from storer 308/write the 3rd data 408 to storer 308.
In this example, the first order the 401 and the 4th order 404 is processed by bus main thread 0, and the second order the 402 and the 5th order 405 is processed by bus main thread 1, and the 3rd order 403 is processed by bus main thread 2.
As shown, transmit serially data 406,407,408 via FPDP.By for example being allowed by different threads processing command 401-405 even transmitted the first data 406 by FPDP before, just receiving the second order 402 by bus master controller 305.Signal below for example utilizing and connecting is carried out communicating by letter between each register 309 and the bus master controller 311.
Io_context_reset: be used for replacement I/O context.
Buffer_base_pointer: the start address corresponding to the contextual first memory of this I/O zone 315 that is used for predetermined memory 308.
Buffer_size: the size that is used for predetermined memory zone 315.
N_buffers_virt: the number that is used for predetermined memory zone 315.
Start_buffer_virt: be used for regulation and will begin for it the memory area 315(that processes for example in the sequential processes of each memory area 315).
For example for every kind of I/O context exist these signals with connection
According to an embodiment, as mentioned above, based on each the memory area 315 usage data synchronization concept in the shared storage 308.In general, according to an embodiment, the data 103 that are based on synchronously that data produce entities (for example process) 101 and data consumption entity (for example process) 102 are divided into data block, and described data block is stored in each memory area in the shared storage.
Explain in more detail for data below with reference to Fig. 5 and to use synchronously memory area 315.
Fig. 5 illustrates the storer 500 according to an embodiment.
Therefore each data block 502 is stored in the independent shared memory area 501, and wherein data block size 504 is less than or equal to memory region size 503 in all cases.
Always memory area 501 is each only addressable for parts of data processing equipment 300, no matter described access is reading of read access, write-access or mixing and write-access.Currently give the parts of the access of memory area 501 also are known as the owner of memory area 501 to it.It can be hardware component or the software part of data processing equipment 300.
In order to control the entitlement of particular area of memory 501, use common data synchronization concept according to an embodiment.This data synchronization concept is based on the parameter that is represented as block_size, and it is stored for each memory area 501 by parts.Use this parameter according to following rule:
● block_size〉0: only have described parts to carry out the read/write access to this memory area and all parameters thereof.
● block_size=0: only have another parts to carry out the read/write access to this memory area and all parameters thereof.
This means if corresponding to the block_size parameter of this memory area greater than zero, described parts just can read or write this memory area.Do not allow at that time another parts to conduct interviews.Described parts one block_size parameter zero setting (be about to it and be set to zero), another parts just can be accessed described memory area again.
In the situation that data processing equipment 300, for example for each memory area 315 with the block_size Parameter storage in corresponding to the block_size parameter register in the register 309 of this memory area 315.For instance, the block_size parameter can be stored in corresponding to using therein the i.e. reference-to storage zone 315 therein of memory area 315(, for example write data into therein in the memory area 315 or therein from memory area 315 reading out datas) the contextual set of registers 316 of I/O the block_size parameter register in.
The block_size parameter for example can directly or indirectly be write by local general purpose controller 303.For instance, controller 303 can directly write to the block_size parameter corresponding in the block_size parameter register in the register 309 of memory area 315.For situation indirectly, controller 303 can always be written to the same register (for example aspect register address) in the register 309, and it automatically is mapped to the block_size parameter register of (for example passing through special circuit) memory area 315.
Can be by the value of local general purpose controller 303 direct or indirect poll block_size parameters.For instance, the direct block_size parameter register of poll (for example reading) memory area 315 of controller 303.
For situation indirectly, controller 303 is the same register of poll always, and it automatically is mapped to the block_size parameter register of (for example passing through special circuit) memory area 315.
According to an embodiment, can be with the additional memory region Parameter storage in each register 309 corresponding to each memory area 315.
For instance, reside in immediately following corresponding in the additional memory region parameter register in the register 309 of the nuclear of the accelerator after the block_size parameter register of memory area 315 302 corresponding to the additional memory region parameter of a memory area 315.In one embodiment, the additional memory region parameter can be optional, and the block_size parameter can be enforceable.The number of additional memory region parameter and purposes can define (if data processing equipment comprise more than an accelerator 301, then every kind of I/O context for each accelerator 301 defines individually) for every kind of I/O context individually in when design.The memory region parameter register can also be used to (optionally) memory area rreturn value, and it also can be defined when design.
The additional memory region parameter for example can stipulate how to process the data that are stored in the memory area 315 (for example can stipulate the function that will carry out data etc.).The additional memory region parameter for example can also be stipulated will be in another time read memory zone 315.For instance, each memory area 315 has ordering in one embodiment, and subsequently according to this ordering accessed (read or write).The additional memory region parameter for example can be the Data duplication bit, and can stipulate by described Data duplication bit will double reference-to storage zone 315.
For example can examine 302 by accelerator corresponding to the memory area rreturn value of memory area 315 arranges after having processed the data block that is stored in the memory area 315.For instance, the memory area rreturn value can be stipulated, for the CRC(cyclic redundancy check (CRC) of data) success.
Be similar to the memory areas domain browsing, can be by the accessibility of parts of block_size parameter control for the additional memory region parameter:
● block_size〉0: the parts that only have the additional memory region parameter register can carry out the read/write access to this memory area and all parameters thereof.
● block_size=0: only have another parts to carry out the read/write access to this memory area and all parameters thereof.
According to an embodiment, adopt the hierarchy memory area concept.This is illustrated in Fig. 6.
Fig. 6 illustrates data processing equipment 600.
According to an embodiment, data processing equipment 600 comprises and is configured to select the selection circuit 606 of data object 603 and be configured to the status information about selected data object 603 is stored in memory circuit 607 in the data storage cell 604 according to pre-defined rule.
Described selection circuit can be configured to select data object according to the ordering of data object.
Should be noted that data processing circuit 605, select circuit 606 and memory circuit 607 not necessarily must and circuit 209 be set corresponding to data access circuit 208, the check circuit 207 of data processing equipment 200.Yet data processing circuit 605, selection circuit 606 and memory circuit 607 for example can be the parts of the first data processor 201, for example are the parts of interface 211.
Described status information for example is the access right to the data object, and described data object for example is the memory area of storer.
In other words, the data storage cell 604 of (for example register 309 of the accelerator nuclear 305) second memory 602 that in one embodiment, only has the subset subset of the block_size parameter value of all memory areas 315 (for example corresponding to) of full state information to be mapped to.
For instance, in the situation that data processing equipment 300, use two-layer memory areas Domain Index, this allows for the contextual high total memory of single I/O zone counting, wherein one deck memory areas Domain Index identifies each memory area, and another layer memory areas Domain Index identify register 309 memory region parameter set (for example corresponding to each memory region parameter set of memory area, it comprise the block_size memory region parameter and corresponding to the additional parameter of this memory area).
The full set of status information can be regarded as the virtual parameter set, and data storage cell 604 is corresponding to (physics) parameter sets that resides in the control store.Index in the ground floor (memory area layer 0) for example carries out addressing to the parameter sets in the control store, and the index in the second layer (memory area layer 1) carries out addressing to virtual parameter set.This is illustrated in Fig. 7.
Fig. 7 illustrates the mapping according to the status information of an embodiment.
In the explanation of Fig. 7, in control store 701, there are 4 memory region parameter set of numbering from 0 to 3 and 8 memory areas of numbering from 0 to 7.
In other words, at register 309(register file for example) in physics can with the I/O context in only have four memory region parameter set.Therefore for four memory areas 702 wherein only, the memory region parameter set of himself is only (for example comprising block_size parameter and additional memory region parameter) part of register 309.
The number of memory area 702 is counted corresponding to memory area total in the I/O context, and needs not be the integral multiple of the parameter sets number in the control store 701.The number of memory area 702 for example can be by software programming.It also can be different for different I/O contexts.
First memory area level (memory area layer 0) can represent the moving window that covers 4 memory areas.In other words, the set of memory region parameter in the control store 701 comprises the wherein parameter of four memory areas 702 according to moving window, and for example the glide direction that has of described moving window is by arrow 703 indications on the direction of increasing progressively of memory area 702 numberings.Therefore, the parameter sets in the control store 701 comprises that wherein these four memory areas 702 change according to described " moving window " corresponding to the parameter of four memory areas 702 wherein.
For memory area layer 1, accelerator main interface 305 is only followed the tracks of and will be carried out to it current storage region index of the memory area 315 of next data access, and the start address of (namely will access) next memory area that will use in the computing store 308.In one embodiment, do not need the hardware effort of adding for memory area layer 1.All memory region parameter corresponding to the current memory area that is not covered by moving window (according to current mapping, for example the position of moving window) can or can be stored by means of software variable by impliedly definition (for example can have default value).
According to an embodiment, automatic message can be used to by the specific messages port with signal to local general purpose controller 303 notices finishing the data access of memory area.These automatic messages (also being known as automatic message (Auto-Message) here) for example are local messages, and for example are not the message by system bus 307 transmissions of data processing equipment 300.If the effective words of described automatic message feature then can be switched on for each I/O context or disconnect by software (for example by the control bit in the register 309 that uses accelerator nuclear 302).
In the time will sending automatic message, the automatic message circuit 312 of accelerator main interface 305 generates the automatic message data word, and it for example comprises:
● accelerator nuclear index (in the situation that having a plurality of accelerator nuclears to be used for sign accelerator nuclear 302 in the hardware accelerator 301)
● accelerator main interface index (in the situation that having a plurality of accelerator main interfaces to be used for sign accelerator main interface 305 in the accelerator nuclear 302)
● I/O context index (being used for sign I/O context)
● the memory areas Domain Index
● the index of the memory region parameter set in the control store
The automatic message that generates is sent to the automatic message moderator accelerator main interface of correspondence (for example via).Automatic message moderator 314 can be disposed in accelerator nuclear 302(or a plurality of accelerator nuclear 302) with local general purpose controller 303 between with for the automatic message of software is sent.For instance, when two or more main interfaces 305 were wanted to send automatic message simultaneously, the automatic message moderator was followed circulating scheme.
Auto_msg_dout: be used for transmitting the automatic message that will send by automatic message circuit 312.
Auto_msg_valid: be used for showing by automatic message circuit 312, the automatic message that is sent to automatic message moderator 314 is effective.
Auto_msg_ack: be used for confirming to receive automatic message from automatic message circuit 312 by automatic message moderator 314.
In addition, in the situation that automatic message transmits can and be connected and bus master controller 311 communicate with following signal:
Acc_core_index: be used in the situation that automatic message transmits accelerator nuclear 302 being carried out addressing.
Master_if_index: be used in the situation that automatic message transmits main interface 305 being carried out addressing.
According to an embodiment, accelerator main interface 305 has the port be used to the central synchronization hardware 310 that is connected to data processing equipment 300, and it is formed by direct synchronizing circuit 313 and synchronous bus arbiter circuit 317 in example shown in Figure 3.Directly synchronizing circuit 313 can be used to the autonomous memory zone synchronously, and it is known as directly synchronously (Direct Sync) below.
Directly can be included in synchronously in the mutual situation of any every memory area of not having local general purpose controller 303 pre-configured block_size parameter value is written to register 309.Accelerator kernel 304 possibly can't be distinguished the block_size parameter value by hardware (namely by direct synchronizing function) or be write by software (perhaps by controller 303).
The pre-configured value of block_size parameter for example can always be written in the control store will the block_size register for next memory region parameter set of corresponding I/O context configuration in.The index of this parameter sets in control store for example can utilize counter to generate.
If direct effective words of synchronous characteristic then can be switched on for each I/O context or disconnect by software (control bit from register that for example utilizes accelerator to examine).
Directly synchronizing circuit 313 is connected with the synchronous bus arbiter circuit and for example can be utilized following signal to be connected with connection.
The synchronous promoter of synci_valid(is effective): when being activated, this signal shows the effective input on promoter's passage.
Synci_valid_oms(is from promoter's useful signal of other dominant forces of described layer): when being activated, initiate the output of word from this signal disables of the higher dominant force of priority.Utilize direct each synchronous other accelerator main interface example that a bit is arranged, local controller has a bit.
Synci_mid: the ID that initiates dominant force.Described mapping will be by defining with general parameter.
Synci_type(initiates the word type):
0: the 1st cycle that access is initiated: addressing, read/write indication
1: the 2nd cycle that writes initiation: data writing.
Synci_type_oms(is from the initiation word type of other dominant forces of described layer): show the data writing stage from 1 of dominant force, it should not separate with address phase.Even when priority is higher, this also forbids the output of initiating word.Utilize direct each synchronous other accelerator main interface example that a bit is arranged, local controller has a bit.
The synci_data(originator data): initiate word, multiplexing address (14 bits comprise for 3 bits that agent functionality is encoded), read/write designator (1 bit), and data writing (8 bit).Two stages that write affairs always transmit continuously.
The syncr_valid(sync response is effective): the signal that has activated shows the effective input on the response channel.
The dominant force ID of syncr_mid(response receiver): this dominant force is only accepted by the suitably response of addressing.Described mapping will be by defining with general parameter.
The syncr_data(reading out data): its content is indifferent to for write-access.In the accelerator main interface, do not connect in inside.Only stipulate for compatibility reason.
Although illustrate especially and described the present invention with reference to specific embodiment, but those skilled in the art are to be understood that, in the situation that does not deviate from the spirit and scope of the present invention that appended claims limits, various changes can made therein aspect form and the details.Therefore, scope of the present invention is indicated by appended claims, and so intention comprises the implication of the equivalent that is in claims and the institute in the scope changes.
Claims (19)
1. data processing equipment comprises:
The storer that comprises a plurality of memory areas;
The first data processor;
Control store, whether it comprises for each memory area in described a plurality of memory areas and shows and can carry out indication to the data access of this memory area by the first data processor; And
The second data processor;
Wherein, the first data processor comprises:
Check circuit, whether it is configured to can be by the data access of the first data processor execution to this memory area for this memory area inspection based on the described indication corresponding to memory area;
The data access circuit, it is configured to carry out the data access to this memory area in situation about can be carried out by the first data processor the data access of a memory area in described a plurality of memory areas; And
Circuit is set, and it is configured in response to the first data processor the finishing of data access of memory area be arranged cannot be by the data access of the first data processor execution to this memory area to show corresponding to the described indication of this memory area;
And wherein, the described indication that the second data processor is configured to arrange corresponding to memory area can be carried out the data access to this memory area to show the first data processor.
2. data processing equipment according to claim 1, wherein, the described indication that the second data processor is configured to arrange corresponding to memory area can be carried out the data access to this memory area to show the first data processor.
3. data processing equipment according to claim 1, wherein, the first data processor also comprises for carrying out the memory interface of exchanges data with described storer.
4. data processing equipment according to claim 1, wherein, the first data processor is configured to carry out data access to memory area according to predefined procedure.
5. data processing equipment according to claim 1, wherein, the first data processor comprises the input end that is configured to receive described indication.
6. data processing equipment according to claim 1, wherein, the second data processor is the processor of operating software process, and wherein can carry out data access to this memory area corresponding to the setting of the described indication of memory area to show the first data processor by described software process initiation.
7. data processing equipment according to claim 1, wherein, the first data processor also comprises data processing circuit and interface, described interface is configured in the process of data access the data retransmission that reads from described storer perhaps to provide the data that will be written to described storer to described data processing circuit in the process of data access.
8. data processing equipment according to claim 1, wherein, described memory area is the impact damper that distributes in shared storage.
9. data processing equipment according to claim 1, wherein, described memory area has equal size.
10. data processing equipment according to claim 1, it is computing machine.
11. data processing equipment according to claim 1, wherein, show that can carry out described indication to the data access of memory area by the first data processor is to show that the data block size of the data block that is stored in this memory area is greater than zero standard.
12. data processing equipment according to claim 1, wherein, show that the described indication that cannot be carried out the data access of memory area by the first data processor is to show that the data block size of the data block that is stored in this memory area is zero standard.
13. data processing equipment according to claim 1, wherein, for at least one memory area, except described indication, described control store is also stored at least one parameter value, according to described at least one parameter value, will or process the data that are stored in this memory area by the access of the first data processor executing data.
14. data processing equipment according to claim 13, wherein, described control store is configured to receive described at least one parameter value from the second data processor.
15. the data processor of a data processing equipment, described data processor comprises:
Control store, whether it comprises for each memory area in a plurality of memory areas and shows and can carry out indication to the data access of this memory area by the first data processor;
Check circuit, whether it is configured to can be by the data access of the first data processor execution to this memory area for this memory area inspection based on the described indication corresponding to memory area;
The data access circuit, it is configured to carry out the data access to this memory area in situation about can be carried out by the first data processor the data access of a memory area in described a plurality of memory areas;
Circuit is set, and it is configured in response to the first data processor the finishing of data access of memory area be arranged cannot be by the data access of the first data processor execution to this memory area to show corresponding to the described indication of this memory area.
16. a data processing equipment comprises:
The first memory that comprises a plurality of data objects;
The second memory that comprises a plurality of data storage cells, wherein the number of data storage cell is less than the number of data object;
Data processing circuit, it is configured to for access described a plurality of data storage cell about the status information of described a plurality of data objects;
Select circuit, it is configured to select data object according to pre-defined rule from described a plurality of data objects;
Memory circuit, it is configured to the status information about the selected data object is stored in the data storage cell of described a plurality of data storage cells.
17. data processing equipment according to claim 16, wherein, described selection circuit is configured to select data object according to the ordering of data object.
18. data processing equipment according to claim 16, wherein, described status information is the access right to the data object.
19. data processing equipment according to claim 16, wherein, described data object is the memory area of storer.
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| US13/169128 | 2011-06-27 | ||
| US13/169,128 US8880811B2 (en) | 2011-06-27 | 2011-06-27 | Data processing device and data processing arrangement for accelerating buffer synchronization |
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| CN102855199A true CN102855199A (en) | 2013-01-02 |
| CN102855199B CN102855199B (en) | 2016-05-11 |
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| US (1) | US8880811B2 (en) |
| CN (1) | CN102855199B (en) |
| DE (1) | DE102012105622A1 (en) |
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| CN108090008A (en) * | 2016-11-22 | 2018-05-29 | 谷歌有限责任公司 | For the system and method for parallel power monitoring |
| CN112789604A (en) * | 2018-09-28 | 2021-05-11 | 罗克韦尔柯林斯德国公司 | Data processing apparatus with multiple processors and multiple interfaces |
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| GB2511794B (en) * | 2013-03-13 | 2020-12-02 | Advanced Risc Mach Ltd | A Protection Unit and Method for Controlling Access by Plural Processes to a Storage Unit |
| US10007586B2 (en) * | 2016-01-08 | 2018-06-26 | Microsoft Technology Licensing, Llc | Deferred server recovery in computing systems |
| US10387666B2 (en) * | 2016-01-15 | 2019-08-20 | Acronis International Gmbh | System and method for synchronization of large amounts of data while maintaining control over access rights to such data |
| US10296338B2 (en) * | 2016-12-09 | 2019-05-21 | Intel Corporation | System, apparatus and method for low overhead control transfer to alternate address space in a processor |
| JP2019008860A (en) * | 2017-06-28 | 2019-01-17 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
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Also Published As
| Publication number | Publication date |
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| US20120331240A1 (en) | 2012-12-27 |
| DE102012105622A1 (en) | 2012-12-27 |
| CN102855199B (en) | 2016-05-11 |
| US8880811B2 (en) | 2014-11-04 |
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