CN102854373B - PWM (Pulse-Width Modulation) three-level digital controller of zero-flux Hall large-current sensor - Google Patents
PWM (Pulse-Width Modulation) three-level digital controller of zero-flux Hall large-current sensor Download PDFInfo
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- CN102854373B CN102854373B CN201210125181.1A CN201210125181A CN102854373B CN 102854373 B CN102854373 B CN 102854373B CN 201210125181 A CN201210125181 A CN 201210125181A CN 102854373 B CN102854373 B CN 102854373B
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Abstract
The invention discloses a PWM (Pulse-Width Modulation) three-level digital controller of a zero-flux Hall large-current sensor. The PWM three-level digital controller comprises a PWM carrier wave triangle generation and regulation circuit, a Hall chip signal collection and negative feedback PID (Proportion Integration and differentiation) control parameter circuit, a three-level circuit and a square wave signal generation circuit; the PWM carrier wave triangle generation and regulation circuit is utilized to generate a positive carrier wave signal and a negative carrier wave signal, the Hall chip signal collection and negative feedback PID control parameter circuit collects a Hall voltage signal by utilizing a difference amplification circuit, and outputs proper feedback voltage by regulating the negative feedback PID control parameters, the feedback voltage and the carrier wave signals are intersected, different square wave signals are generated through control at intersection moment, the square wave signals control the on and off of four transistors in the three-level circuit and outputs the voltage, a compensation coil generates current, and the value of the current is measured out. The PWM three-level digital controller can measure large current, is high in current signal measurement frequency and low in cost, and solves the problems of influences on the large-power consumption radiation and voltage grade improvement of the transistors under large-current conditions.
Description
Technical field
The present invention relates generally to the design of a Novel digital type controller of zero magnetic flux Hall great current sensor.
Background technology
It is the large current bi-pole sensor of 45KA that the PF power-supply system of the DC test platform of ITER power supply and following ITER power supply needs range, and on domestic and international market, lacks this type of current sensor at present.Novel optical fiber formula current sensor can be measured large electric current, but its frequency response of measuring current signal is not high, and expensive, and the price of the sensor of 45KA range is also in 450,000 Renminbi left and right, ITER supply unit needs a lot of current sensors, and this cost is quite high.
Hall zero magnetic flux Hall bidirectional current sensor on market, its controller is based on Analog Circuit Design, and sensor is in the time measuring electric current, and the transistor of its main output is to be operated in magnifying state, has output resistance, and during by electric current, transistor can produce heat.Current sensor, has fixing turn ratio number, measures in the situation of little electric current, and the output current value of paying limit is generally less, needn't consider transistorized power consumption.Exceeding under the large current conditions of 20KA, the electric current of paying limit compensating coil will be very large, reaches order of amps, and at this moment transistorized power consumption is very large, and tens watts to hectowatt all likely.So large pipe consumption in design heat radiation, only depend on air-cooled will be very difficult.Under large current conditions, must improve in addition the electric pressure of controller in order to pursue larger offset current, and the raising of electric pressure can affect complementary type and recommend the type selecting of the transistor unit of power circuit, so the problem of transistorized high power waste radiation and electric pressure has directly limited the application of analog quantity controller under large current applications.
Summary of the invention
The object of the invention is exactly the defect in order to make up prior art, and a kind of PWM tri-level digital controllers of zero magnetic flux Hall great current sensor are provided.
The present invention is achieved by the following technical solutions:
PWM tri-level digital controllers for zero magnetic flux Hall great current sensor, include the collection of the leg-of-mutton generation of PWM carrier wave and Circuit tuning thereof, Hall plate signal and the generation circuit of negative feedback pid control parameter circuit, tri-level circuit and square-wave signal, the described leg-of-mutton generation of PWM carrier wave and Circuit tuning thereof comprise a chip AP2001 and amplifier one, amplifier two, amplifier three, on the CT pin of described chip AP2001, be connected in series a capacitor, on RT pin, be connected in series a slide rheostat, the equal ground connection of the other end of described capacitor and slide rheostat, the carrier signal producing at CT pin enters respectively the in-phase input end of described amplifier one through a capacitor, the in-phase input end of one resistance one termination amplifier one, one end ground connection, the reverse inter-input-ing ending grounding of amplifier one, at inverting input and an output terminal slide rheostat in parallel, the power supply of amplifier one just, negative pole is respectively through a capacitor grounding, the in-phase input end of amplifier two described in the output termination of amplifier one, the inverting input of amplifier two is connected with a slide rheostat, the two ends of slide rheostat connect respectively power positive cathode, a capacitor in parallel between power cathode and slide rheostat, the inverting input of amplifier three described in the output termination of amplifier two, the in-phase input end ground connection of amplifier three, negative sense carrier signal is in the output terminal output of amplifier two, forward carrier signal is in the output terminal output of amplifier three, form the two-way carrier signal of opposite sign but equal magnitude, the collection of described Hall plate signal and negative feedback pid control parameter circuit comprise a differential amplifier circuit and negative feedback pid control parameter circuit, the output terminal of described differential amplifier circuit is connected with the inverting input of the amplifier four in negative feedback pid control parameter circuit, the in-phase input end ground connection of amplifier four, an impedor in parallel between inverting input and output terminal, described tri-level circuit comprises four HCPL3120 chips, four voltage stabilizing diodes, four transistors, four diodes, two capacitors and two have polar capacitor, the drain electrode of transistor one connects positive source, the source electrode of transistor one connects the drain electrode of transistor two, the source electrode of transistor two connects the drain electrode of transistor three, the source electrode of transistor three connects the drain electrode of transistor four, the drain electrode of transistor four connects power cathode, voltage stabilizing diode one, two, three, four negative pole connects respectively transistor one, two, three, four grid, the positive pole of voltage stabilizing diode one is connected between the source electrode of transistor one and the drain electrode of transistor two, the positive pole of voltage stabilizing diode two is connected between the source electrode of transistor two and the drain electrode of transistor three, the positive pole of voltage stabilizing diode three is connected between the source electrode of transistor three and the drain electrode of transistor four, the positive pole of voltage stabilizing diode four is connected on power cathode, the VO pin 7 of four described HCPL3120 chips is all connected on NC pin 6, NC pin 1, K pin 3 and the equal ground connection of NC pin 4, HCPL3120 chip one, two, three, four NC pin 6 respectively with described transistor one, two, three, four grid is connected, four described diodes form bridge circuit, two input ends one and two of bridge circuit are connected on respectively between the source electrode of transistor one and the drain electrode of transistor two, between the drain electrode of the source electrode of transistor three and transistor four, the output terminal one of bridge circuit is connected with a sample resistance, sample resistance is connected with a compensating coil, the other end of compensating coil is connected between the source electrode of transistor two and the drain electrode of transistor three, between positive source and another output terminal two of bridge circuit, be parallel with respectively capacitor one and one dc capacitor one, the positive pole of this dc capacitor one connects positive source, negative pole connects the output terminal two of bridge circuit, between the output terminal two of bridge circuit and power cathode, be parallel with respectively a capacitor two and dc capacitor two, the positive pole of this dc capacitor two connects the output terminal two of bridge circuit, negative pole connects power cathode, capacitor one is connected through the output terminal two of bridge circuit with two, the positive pole of the negative pole of dc capacitor one and dc capacitor two is connected through the output terminal two of bridge circuit, required voltage is exported from the output terminal two of bridge circuit, described square-wave signal produces circuit and comprises two comparers and four not circuits, the output terminal of described amplifier four connects respectively the in-phase input end of comparer, the forward carrier signal of described output and negative sense carrier signal connect respectively the inverting input of comparer one and two, there is one end of a capacitor three to be connected with the in-phase input end of comparer one, other end ground connection, there is one end of a capacitor four to be connected with the inverting input of comparer one, other end ground connection, there is one end of a capacitor five to be connected with the inverting input of comparer two, other end ground connection, the output terminal of comparer one is connected by the input end of resistance one NAND gate circuit one, there is an end of a resistance two to be connected between the output terminal and resistance one of comparer one, another termination positive source of resistance two, there are the positive pole on diode May Day and the negative pole of a diode five or two are connected and are jointly connected between resistance one NAND gate circuit one input end, connect+5V of the negative pole power supply on diode May Day, the plus earth of diode five or two, the output terminal of not circuit one is connected with the input end of not circuit two with a resistance three respectively, a two ends diode six in parallel of resistance three, the negative pole of diode six is connected between the output terminal of resistance three NAND gate circuit one, resistance three has square-wave signal three outputs with the anodal one end being connected of diode six, one end of one capacitor six is connected with the intersection point of resistance three with the positive pole of diode six, the other end ground connection of capacitor six, the output terminal of described not circuit two is connected with resistance four, resistance four and one diode seven is in parallel, the negative pole of diode seven is connected between the output terminal and resistance four of not circuit two, there is square-wave signal one output one end that resistance four is connected with the positive pole of diode seven, there are one end of a capacitor seven and the positive pole of diode seven to be connected with the intersection point of resistance four, the other end ground connection of capacitor seven, the output terminal of described comparer two is connected by the input end of resistance five NAND gate circuit three, there is an end of a resistance six to be connected between the output terminal and resistance five of comparer two, another termination positive source of resistance six, there are the positive pole of a diode Aug. 1st and the negative pole of a diode eight or two to be connected and are jointly connected between resistance five NAND gate circuit three input ends, connect+5V of the negative pole of diode Aug. 1st power supply, the plus earth of diode eight or two, the output terminal of not circuit three is connected with the input end of not circuit four with a resistance seven respectively, a two ends diode nine in parallel of resistance seven, the negative pole of diode nine is connected between the output terminal of resistance seven NAND gate circuit three, resistance seven has square-wave signal four outputs with the anodal one end being connected of diode nine, one end of one capacitor eight is connected with the intersection point of resistance seven with the positive pole of diode nine, the other end ground connection of capacitor eight, the output terminal of described not circuit four is connected with resistance eight, resistance eight and one diode ten is in parallel, the negative pole of diode ten is connected between the output terminal and resistance eight of not circuit four, there are square-wave signal two outputs one end that resistance eight is connected with the positive pole of diode ten, there are one end of a capacitor nine and the positive pole of diode ten to be connected with the intersection point of resistance eight, the other end ground connection of capacitor nine, described square-wave signal one, two, three, four enters respectively in the A pin 2 of described HCPL3120 chip one, two, three, four.
Feature of the present invention is also that four described transistors are insulated gate bipolar transistor; Described forward carrier signal and the waveform of negative sense carrier signal are isosceles triangle.
Principle of work of the present invention:
1, the leg-of-mutton generation of carrier wave and adjustment: utilize signal generating circuit to generate the carrier wave of PWM, it is generally isosceles triangle waveform, consider that current sensor needs certain frequency response requirement, need the speed of response that controller needs are higher, the carrier frequency of controller of the present invention is 100KHz.Current sensor of the present invention is to measure bidirectional current, and the control carrier wave of PWM also will be designed to two-way carrier current channel so.
2, the design of the collection of Hall plate signal and negative feedback pid control parameter: in the time that sensor primary side has current signal, Hall original paper just can induce voltage, utilize differential amplifier circuit to gather Hall voltage signal, and by the adjustment of negative feedback pid control parameter, export suitable feedback voltage.Feedback voltage is crossing with carrier wave triangular wave, and the moment of joining just can be controlled corresponding transistorized break-make, thereby can give corresponding compensating coil power supply, realizes zero magnetic flux effect of sensor inner magnetic core.
3, the circuit structure of tri-level circuit: major loop structure formula of the present invention designs based on tri-level circuit, in the time of primary side forward current, by the computing of foregoing circuit, transistor one, two, three corresponding conductings, output forward voltage, compensating coil produces forward current, and zero magnetic flux is realized in the magnetic field that compensation primary side produces.Transistor four, three, two corresponding conductings in the time of primary side negative current, output negative voltage, compensating coil produces negative current, and zero magnetic flux is realized in the magnetic field that compensation primary side produces.
4, output sampling: the measuring method of offset current, seal in sample resistance at equalizing network, gather sampling voltage and obtain current value accurately.
Advantage of the present invention is: the present invention has designed two-way carrier current channel, has formed bipolar current sensor; The present invention can measure large electric current and measure the frequency of current signal high, and cost is low, has solved the problem of the impact that under large current conditions, transistorized high power waste radiation and electric pressure improve.
Accompanying drawing explanation
Fig. 1 is the leg-of-mutton generation of PWM carrier wave and Circuit tuning.
Fig. 2 is collection and the negative feedback pid control parameter circuit of Hall plate signal.
Fig. 3 is tri-level circuit.
Fig. 4 is the generation circuit of square-wave signal.
Fig. 5 is sensor measurement forward current signal output waveform of the present invention.
Fig. 6 is sensor measurement negative current signal output waveform of the present invention.
Fig. 7 is that sensor measurement of the present invention exchanges 50Hz electric current oscillogram.
Embodiment
PWM tri-level digital controllers for zero magnetic flux Hall great current sensor, include the collection of the leg-of-mutton generation of PWM carrier wave and Circuit tuning thereof, Hall plate signal and the generation circuit of negative feedback pid control parameter circuit, tri-level circuit and square-wave signal, the described leg-of-mutton generation of PWM carrier wave and Circuit tuning thereof are as shown in Figure 1, comprise a chip AP2001U1 and amplifier one U2A, amplifier two U2B, amplifier three U2C, on the CT pin of described chip AP2001U1, be connected in series a capacitor C1, on RT pin, be connected in series a slide rheostat WR1, the equal ground connection of the other end of described capacitor C1 and slide rheostat WR1, the carrier signal TR1WAVE producing at CT pin enters respectively the in-phase input end of described amplifier one U2A through a capacitor C4, the in-phase input end of one resistance R 4s mono-termination amplifier one U2A, one end ground connection, the reverse inter-input-ing ending grounding of amplifier one U2A, at inverting input and an output terminal slide rheostat RP3 in parallel, the power supply of amplifier one U2A just, negative pole is respectively through a capacitor C5 ground connection, the in-phase input end of amplifier two U2B described in the output termination of amplifier one U2A, the inverting input of amplifier two U2B is connected with a slide rheostat RP2, the two ends of slide rheostat RP2 connect respectively power positive cathode, a capacitor C7 in parallel between power cathode and slide rheostat RP2, the inverting input of amplifier three U2C described in the output termination of amplifier two U2B, the in-phase input end ground connection of amplifier three U2C, negative sense carrier signal TRI-is in the output terminal output of amplifier two U2B, forward carrier signal TRI+ is in the output terminal output of amplifier three U2C, form the two-way carrier signal of opposite sign but equal magnitude, the collection of described Hall plate signal and negative feedback pid control parameter circuit are as shown in Figure 2, comprise a differential amplifier circuit and negative feedback pid control parameter circuit, the output terminal of described differential amplifier circuit is connected with the inverting input of amplifier four U4B in negative feedback pid control parameter circuit, the in-phase input end ground connection of amplifier four U4B, an impedor Zf in parallel between inverting input and output terminal, at the output terminal output feedback voltage V ERR of amplifier four U4B, described tri-level circuit as shown in Figure 3, comprises four HCPL3120 chip U6, U7, U8, U9, four voltage stabilizing diode Z1, Z2, Z3, Z4, four transistor Q1, Q2, Q3, Q4, four diode D1, D2, D3, D4, two capacitor C14, C15 and two have polar capacitor E12, E13, the drain electrode of transistor one Q1 connects positive source, and the source electrode of transistor one Q1 connects the drain electrode of transistor two Q2, the source electrode of transistor two Q2 connects the drain electrode of transistor three Q3, the source electrode of transistor three Q3 connects the drain electrode of transistor four Q4, and the drain electrode of transistor four Q4 connects power cathode, voltage stabilizing diode one Z1, two Z2, three Z3, the negative pole of four Z4 meets respectively transistor one Q1, two Q2, three Q3, the grid of four Q4, the positive pole of voltage stabilizing diode one Z1 is connected between the source electrode of transistor one Q1 and the drain electrode of transistor two Q2, the positive pole of voltage stabilizing diode two Z2 is connected between the source electrode of transistor two Q2 and the drain electrode of transistor three Q3, the positive pole of voltage stabilizing diode three Z3 is connected between the source electrode of transistor three Q3 and the drain electrode of transistor four Q4, the positive pole of voltage stabilizing diode four Z4 is connected on power cathode, the VO pin 7 of four described HCPL3120 chips is all connected on NC pin 6, NC pin 1, K pin 3 and the equal ground connection of NC pin 4, HCPL3120 chip one U6, two U7, three U8, the NC pin 6 of four U9 respectively with described transistor one Q1, two Q2, three Q3, the grid of four Q4 is connected, four described diode D1, D2, D3, D4 forms bridge circuit, and two input ends one 1 and 22 of bridge circuit are connected on respectively between the source electrode of transistor one Q1 and the drain electrode of transistor two Q2, between the drain electrode of the source electrode of transistor three Q3 and transistor four Q4, the output terminal 1 of bridge circuit is connected with a sample resistance J5, sample resistance J5 connects with a compensating coil J4, the other end of compensating coil J4 is connected between the source electrode of transistor two Q2 and the drain electrode of transistor three Q3, between positive source and another output terminal 24 of bridge circuit, be parallel with respectively capacitor one C14 and dc capacitor one E12, the positive pole of this dc capacitor one E12 connects positive source, negative pole connects the output terminal 24 of bridge circuit, between the output terminal 24 of bridge circuit and power cathode, be parallel with respectively capacitor two C15 and dc capacitor two E13, the positive pole of this dc capacitor two E13 connects the output terminal 24 of bridge circuit, negative pole connects power cathode, capacitor one C14 is connected through the output terminal 24 of bridge circuit with two C15, the positive pole of the negative pole of dc capacitor one E12 and dc capacitor two E13 is connected through the output terminal 24 of bridge circuit, required voltage is from output terminal 24 outputs of bridge circuit, described square-wave signal produces shown in circuit diagram Fig. 4, comprise two comparer U5A, U5B and four not circuit U10A, U10B, U10C, U10D, the output terminal of described amplifier four U4B meets respectively comparer U5A, the in-phase input end of U5B, the forward carrier signal TRI+ of described output and negative sense carrier signal TRI-connect respectively the inverting input of comparer one U5A and two U5B, there is one end of capacitor three C24 to be connected with the in-phase input end of comparer one U5A, other end ground connection, there is one end of capacitor four C25 to be connected with the inverting input of comparer one U5A, other end ground connection, there is one end of capacitor five C26 to be connected with the inverting input of comparer two U5B, other end ground connection, the output terminal of comparer one U5A is connected by the input end of resistance one R19 NAND gate circuit one U10A, there is an end of resistance two R17 to be connected between the output terminal and resistance one R19 of comparer one U10A, another termination positive source of resistance two R17, there are the positive pole of a diode D51 on May Day and the negative pole of diode five or two D52 to be connected and are jointly connected between resistance one R19 NAND gate circuit one U10A input end, connect+5V of the negative pole power supply of diode D51 on May Day, the plus earth of diode five or two D52, the output terminal of not circuit one U10A is connected with the input end of not circuit two U10C with resistance three R2s respectively, two ends diode six D6 in parallel of resistance three R2s, the negative pole of diode six D6 is connected between the output terminal of resistance three R2s NAND gate circuit one U10A, resistance three R2s have square-wave signal three PWM3 outputs with the anodal one end being connected of diode six D6, one end of one capacitor six C16 is connected with the intersection point of resistance three R2s with the positive pole of diode six D6, the other end ground connection of capacitor six C16, the output terminal of described not circuit two U10C is connected with resistance four R29, resistance four R29 and diode seven D12 are in parallel, the negative pole of diode seven D12 is connected between the output terminal and resistance four R29 of not circuit two U10C, there is square-wave signal one PWM1 output one end that resistance four R29 are connected with the positive pole of diode seven D12, there are one end of capacitor seven C17 and the positive pole of diode seven D12 to be connected with the intersection point of resistance four R29, the other end ground connection of capacitor seven C17, the output terminal of described comparer two U5B is connected by the input end of resistance five R20 NAND gate circuit three U10B, there is an end of resistance six R18 to be connected between the output terminal and resistance five of comparer two U5B, another termination positive source of resistance six R18, there are the positive pole of a diode Aug. 1st D81 and the negative pole of diode eight or two D82 to be connected and are jointly connected between resistance five R20 NAND gate circuit three U10B input ends, connect+5V of the negative pole power supply of diode Aug. 1st D81, the plus earth of diode eight or two D82, the output terminal of not circuit three U10B is connected with the input end of not circuit four U10D with resistance seven R30 respectively, two ends diode nine D7 in parallel of resistance seven R30, the negative pole of diode nine D7 is connected between the output terminal of resistance seven R30 NAND gate circuit three U10B, resistance seven R30 have square-wave signal four PWM4 outputs with the anodal one end being connected of diode nine D7, one end of one capacitor eight C18 is connected with the intersection point of resistance seven R30 with the positive pole of diode nine D7, the other end ground connection of capacitor eight C18, the output terminal of described not circuit four U10D is connected with resistance eight R31, resistance eight R31 and diode ten D9 are in parallel, the negative pole of diode ten D9 is connected between the output terminal and resistance eight R31 of not circuit four U10D, there are square-wave signal two PWM2 outputs one end that resistance eight R31 are connected with the positive pole of diode ten D9, there are one end of capacitor nine C19 and the positive pole of diode ten D9 to be connected with the intersection point of resistance eight R31, the other end ground connection of capacitor nine C19, described square-wave signal one PWM1, two PWM2, three PWM3, four PWM4 enter respectively in the A pin 2 of described HCPL3120 chip one U6, two U7, three U8, four U9.Four wherein said transistors are insulated gate bipolar transistor; The waveform of described forward carrier signal TRI+ and negative sense carrier signal TRI-is isosceles triangle.
Utilize the leg-of-mutton generative circuit of PWM carrier wave to generate the carrier signal of PWM, carrier signal TR1WAVE is transmitted into Circuit tuning, through amplifier one U2A, carrier signal amplitude is amplified, the carrier wave after amplifying is carried out skew upwards by amplifier two U2B, under two amplifier actings in conjunction, the carrier signal that adjusts a negative sense amplitude is negative sense carrier signal TRI-, from the output terminal output of amplifier two U2B, the negater circuit forming through amplifier three U2C, negative sense carrier signal TRI-is become to forward carrier signal TRI+, from the output terminal output of amplifier three U2C, forward carrier signal TRI+ and negative sense carrier signal TRI-form the two-way carrier signal of opposite sign but equal magnitude, when working sensor, primary side has electric current I 1, in the magnetic core of sensor, have magnetic flux, Hall element will induce corresponding magnitude of voltage, utilize differential amplifier circuit to gather Hall voltage signal VHALL+ and VHALL-, and by the adjustment of negative feedback pid control parameter, export suitable feedback voltage V ERR, the carrier signal of generation and feedback voltage V ERR are passed in the generation circuit of square-wave signal, carrier signal is crossing with feedback voltage V ERR, the generation circuit of joining control square-wave signal produces four kinds of different square-wave signals, four kinds of square-wave signals are passed into respectively to tri-level circuit and control four transistorized break-makes, while supposing that feedback voltage V ERR is forward, TRI+ is forward carrier wave, through comparer one U5A relatively after, output be exactly positive and negative amplitude be the square-wave signal of 15V, through not circuit U10A and the Shape correction of U10C to square wave, just can export the square-wave signal PWM1 of 0-5V, PWM3, Here it is so-called pwm control signal, pwm signal can be controlled conducting and the cut-off of the transistor Q1～Q4 of three level major loops, high level 5V conducting, low level 0V cut-off.Corresponding comparer two U5B also can produce square-wave signal PWM2, PWM4 simultaneously.Pwm signal control transistor Q1, the corresponding conducting of Q2, Q3 in the time measuring forward current, to compensating coil J4 output forward voltage, compensating coil J4 produces forward current and produces the magnetic field contrary with primary side to offset former magnetic field, realizes zero magnetic flux.Electric current flows through sample resistance J5 simultaneously, by gathering voltage drop, obtains secondary current value I2.Zero magnetic flux effect of sensor inner magnetic core, by magnetic potential equation, the known N1=1 of the number of turn on former pair of limit, N2=6000, as long as measure so the size of the I2 offset current of paying limit, just can know the size of primary side current.The simple principle of work of Here it is zero magnetic flux Hall great current sensor.When primary side negative current, transistor Q4, Q3, the corresponding conducting of Q2, output negative voltage, compensating coil produces negative current and offsets former magnetic field, the principle of work of bipolar current sensor that Here it is.
As shown in Figure 5, sensor measurement forward current signal output waveform, concrete numerical value is as following table:
| | Vernier | 1 | Vernier 2 | Difference |
| Ch 35(V) | -12.93m | ?4.431 | -4.444 | |
| X-axis | 01:18.592 | 01:18.836 | ?244.3ms |
Known N2=6000, I2=4.444A, so measured current I 1=4.444*6000/1=26664A.
As shown in Figure 6, sensor measurement negative current signal output waveform of the present invention, concrete numerical value is as following table:
| | Vernier | 1 | Vernier 2 | Difference |
| Ch 35(V) | ?5.303m | -5.171 | ?5.176 | |
| X-axis | ?2.632 s | ?2.860 s | ?228.1ms |
Known N2=6000, while measuring negative current, I2=-5.176A, so measured current I 1=-5.176*6000/1=31056A.
As shown in Figure 7, sensor measurement exchanges 50Hz electric current oscillogram, CH1 is current peak I1=10A (Imtech's current probe of former limit output, 100mV->1A), the former limit number of turn is 857 circles, pay the output peak I 2=1.46V/1 Ω=1.46A on limit, paying the limit number of turn is 6000 circles.Primary magnetomotive force I1N1=857*10=8570, pays limit magnetic potential I2N2=1.46*6000=8760, and former pair of limit magnetic potential is substantially equal.This is the method for testing of the large electric current alternating current source of equivalence, has certain error on magnetic circuit, and result also has error.
Claims (3)
1. PWM tri-level digital controllers for zero magnetic flux Hall great current sensor, is characterized in that: include the collection of the leg-of-mutton generation of PWM carrier wave and Circuit tuning thereof, Hall plate signal and the generation circuit of negative feedback pid control parameter circuit, tri-level circuit and square-wave signal; The described leg-of-mutton generation of PWM carrier wave and Circuit tuning thereof comprise a chip AP2001 and amplifier one, amplifier two, amplifier three, on the CT pin of described chip AP2001, are connected in series a capacitor
c1, on RT pin, be connected in series a slide rheostat, described capacitor
c1and slide rheostat
wR1the equal ground connection of the other end, CT pin produce carrier signal respectively through a capacitor
c4enter the in-phase input end of described amplifier one, the in-phase input end of a resistance one termination amplifier one, one end ground connection, the reverse inter-input-ing ending grounding of amplifier one, at inverting input and an output terminal slide rheostat in parallel
rP3, the power supply positive and negative electrode of amplifier one is respectively through a capacitor
c5ground connection, in-phase input end, the inverting input of amplifier two and a slide rheostat of amplifier two described in the output termination of amplifier one
rP2series connection, slide rheostat
rP2two ends connect respectively power positive cathode, power cathode and slide rheostat
rP2between a capacitor in parallel
c7the inverting input of amplifier three described in the output termination of amplifier two, the in-phase input end ground connection of amplifier three, negative sense carrier signal is in the output terminal output of amplifier two, forward carrier signal, in the output terminal output of amplifier three, forms the two-way carrier signal of opposite sign but equal magnitude; The collection of described Hall plate signal and negative feedback pid control parameter circuit comprise a differential amplifier circuit and negative feedback pid control parameter circuit, the output terminal of described differential amplifier circuit is connected with the inverting input of the amplifier four in negative feedback pid control parameter circuit, the in-phase input end ground connection of amplifier four, an impedor in parallel between inverting input and output terminal;
Described tri-level circuit comprises four HCPL3120 chips, four voltage stabilizing diodes, four transistors, four diodes, two capacitors and two have polar capacitor, the drain electrode of transistor one connects positive source, the source electrode of transistor one connects the drain electrode of transistor two, the source electrode of transistor two connects the drain electrode of transistor three, the source electrode of transistor three connects the drain electrode of transistor four, the drain electrode of transistor four connects power cathode, voltage stabilizing diode one, two, three, four negative pole connects respectively transistor one, two, three, four grid, the positive pole of voltage stabilizing diode one is connected between the source electrode of transistor one and the drain electrode of transistor two, the positive pole of voltage stabilizing diode two is connected between the source electrode of transistor two and the drain electrode of transistor three, the positive pole of voltage stabilizing diode three is connected between the source electrode of transistor three and the drain electrode of transistor four, the positive pole of voltage stabilizing diode four is connected on power cathode, the VO pin 7 of four described HCPL3120 chips is all connected on NC pin 6, NC pin 1, K pin 3 and the equal ground connection of NC pin 4, HCPL3120 chip one, two, three, four NC pin 6 respectively with described transistor one, two, three, four grid is connected, four described diodes form bridge circuit, two input ends one and two of bridge circuit are connected on respectively between the source electrode of transistor one and the drain electrode of transistor two, between the drain electrode of the source electrode of transistor three and transistor four, the output terminal one of bridge circuit is connected with a sample resistance, sample resistance is connected with a compensating coil, the other end of compensating coil is connected between the source electrode of transistor two and the drain electrode of transistor three, between positive source and another output terminal two of bridge circuit, be parallel with respectively capacitor one and one dc capacitor one, the positive pole of this dc capacitor one connects positive source, negative pole connects the output terminal two of bridge circuit, between the output terminal two of bridge circuit and power cathode, be parallel with respectively a capacitor two and dc capacitor two, the positive pole of this dc capacitor two connects the output terminal two of bridge circuit, negative pole connects power cathode, capacitor one is connected through the output terminal two of bridge circuit with two, the positive pole of the negative pole of dc capacitor one and dc capacitor two is connected through the output terminal two of bridge circuit, required voltage is exported from the output terminal two of bridge circuit, described square-wave signal produces circuit and comprises two comparers and four not circuits, the output terminal of described amplifier four connects respectively the in-phase input end of comparer, the forward carrier signal of described output and negative sense carrier signal connect respectively the inverting input of comparer one and two, there is one end of a capacitor three to be connected with the in-phase input end of comparer one, other end ground connection, there is one end of a capacitor four to be connected with the inverting input of comparer one, other end ground connection, there is one end of a capacitor five to be connected with the inverting input of comparer two, other end ground connection, the output terminal of comparer one is connected by the input end of resistance one NAND gate circuit one, there is an end of a resistance two to be connected between the output terminal and resistance one of comparer one, another termination positive source of resistance two, there are the positive pole on diode May Day and the negative pole of a diode five or two are connected and are jointly connected between resistance one NAND gate circuit one input end, connect+5V of the negative pole power supply on diode May Day, the plus earth of diode five or two, the output terminal of not circuit one is connected with the input end of not circuit two with a resistance three respectively, a two ends diode six in parallel of resistance three, the negative pole of diode six is connected between the output terminal of resistance three NAND gate circuit one, resistance three has square-wave signal three outputs with the anodal one end being connected of diode six, one end of one capacitor six is connected with the intersection point of resistance three with the positive pole of diode six, the other end ground connection of capacitor six, the output terminal of described not circuit two is connected with resistance four, resistance four and one diode seven is in parallel, the negative pole of diode seven is connected between the output terminal and resistance four of not circuit two, there is square-wave signal one output one end that resistance four is connected with the positive pole of diode seven, there are one end of a capacitor seven and the positive pole of diode seven to be connected with the intersection point of resistance four, the other end ground connection of capacitor seven, the output terminal of described comparer two is connected by the input end of resistance five NAND gate circuit three, there is an end of a resistance six to be connected between the output terminal and resistance five of comparer two, another termination positive source of resistance six, there are the positive pole of a diode Aug. 1st and the negative pole of a diode eight or two to be connected and are jointly connected between resistance five NAND gate circuit three input ends, connect+5V of the negative pole of diode Aug. 1st power supply, the plus earth of diode eight or two, the output terminal of not circuit three is connected with the input end of not circuit four with a resistance seven respectively, a two ends diode nine in parallel of resistance seven, the negative pole of diode nine is connected between the output terminal of resistance seven NAND gate circuit three, resistance seven has square-wave signal four outputs with the anodal one end being connected of diode nine, one end of one capacitor eight is connected with the intersection point of resistance seven with the positive pole of diode nine, the other end ground connection of capacitor eight, the output terminal of described not circuit four is connected with resistance eight, resistance eight and one diode ten is in parallel, the negative pole of diode ten is connected between the output terminal and resistance eight of not circuit four, there are square-wave signal two outputs one end that resistance eight is connected with the positive pole of diode ten, there are one end of a capacitor nine and the positive pole of diode ten to be connected with the intersection point of resistance eight, the other end ground connection of capacitor nine, described square-wave signal one, two, three, four enters respectively in the A pin 2 of described HCPL3120 chip one, two, three, four.
2. the PWM tri-level digital controllers of zero magnetic flux Hall great current sensor according to claim 1, is characterized in that: four described transistors are insulated gate bipolar transistor.
3. the PWM tri-level digital controllers of zero magnetic flux Hall great current sensor according to claim 1, is characterized in that: described forward carrier signal and the waveform of negative sense carrier signal are isosceles triangle.
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| CN105572456A (en) * | 2016-03-10 | 2016-05-11 | 河北工业大学 | AC/DC fluxgate current sensor |
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| CN109143122A (en) * | 2018-09-20 | 2019-01-04 | 上海岱梭动力科技有限公司 | Hall sensor |
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| CN112730948B (en) * | 2020-12-14 | 2022-10-25 | 天津航空机电有限公司 | double-Hall sensor conditioning circuit capable of detecting bidirectional current |
| CN112858752B (en) * | 2021-01-06 | 2023-02-21 | 四川众航电子科技有限公司 | Hall sensor device with power isolation |
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Address after: 230001 no.181 Gucheng Road, shiyangang Township, Hefei City, Anhui Province Patentee after: INSTITUTE OF PLASMA PHYSICS, CHINESE ACADEMY OF SCIENCES Address before: 230031 Shushan Lake Road, Shushan District, Anhui, China, No. 350, No. Patentee before: INSTITUTE OF PLASMA PHYSICS, CHINESE ACADEMY OF SCIENCES |