CN102843128B - The digital phase-locked loop operated based on mark input and output phase place - Google Patents
The digital phase-locked loop operated based on mark input and output phase place Download PDFInfo
- Publication number
- CN102843128B CN102843128B CN201210266806.6A CN201210266806A CN102843128B CN 102843128 B CN102843128 B CN 102843128B CN 201210266806 A CN201210266806 A CN 201210266806A CN 102843128 B CN102843128 B CN 102843128B
- Authority
- CN
- China
- Prior art keywords
- phase place
- accumulator
- oscillator
- phase
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The present invention relates to the digital phase-locked loop operated based on mark input and output phase place.In an aspect, digital PLL (DPLL) based on input and output phase place fractional part and operate.Described DPLL adds up at least one input signal to obtain input phase.Described DPLL (such as) service time/digital quantizer (TDC) determines to export the fractional part of phase place based on the phase difference come between the oscillator signal of self-oscillator and reference signal.Described DPLL determines phase error based on the described fractional part of described input phase and the described fractional part of described output phase place.The control signal that described DPLL then produces for described oscillator based on described phase error.In another aspect, DPLL comprises synthesis accumulator, and described synthesis accumulator is determined to export phase place roughly by the number following the trail of oscillator signal period based on described reference signal.
Description
the relevant information of divisional application
This case is divisional application.The application for a patent for invention case that female case of this division is the applying date is on January 12nd, 2009, application number is 200880118247.6, denomination of invention is " digital phase-locked loop operated based on mark input and output phase place ".
Technical field
The present invention relates generally to electronic component, and more particularly, relates to digital phase-locked loop.
Background technology
The integral part that phase-locked loop (PLL) is many electronic circuits and being even more important in telecommunication circuit.For example, digital circuit uses clock signal to carry out trigger synchronous circuits (such as, trigger).Local oscillator (LO) signal is respectively used to frequency up-converted and frequency down-converts by reflector and receiver.Clock signal is used for digital circuit and LO signal is used for reflector and receiver by wireless device (such as, cellular phone) for wireless communication system usually.Come clocking and LO signal with oscillator, and usually control the frequency of clock signal and LO signal with PLL.
PLL generally includes the frequency of oscillator signal and/or the various circuit blocks of phase place that carry out self-oscillator in order to adjustment.These circuit blocks may consume relatively a large amount of power, this for such as cellular phone mancarried device may be unacceptable.Therefore, the technology of the power consumption reducing PLL when not sacrificing performance is needed in technique.
Summary of the invention
The digital PLL (DPLL) with superperformance and lower power consumption is described herein.DPLL is the PLL having the circuit block implemented in a digital manner but not have analog circuit.Numeral is implemented can provide some advantages, such as lower cost, less circuit area etc.
In an aspect, DPLL can operate based on the fractional part of input and output phase place.DPLL can add up can comprise modulation signal at least one input signal to obtain input phase.DPLL can (such as) service time/digital quantizer (TDC) determines to export the fractional part of phase place based on the phase difference come between the oscillator signal of self-oscillator and reference signal.DPLL then can determine phase error based on the fractional part of the fractional part of described input phase and described output phase place.Fractional part can have the scope of the one-period of described oscillator signal.In one design, DPLL can determine the phase difference between the fractional part of described output phase place and the fractional part of described input phase.DPLL then can by predetermined value (such as, a cycle oscillator) add described phase difference to or deduct described predetermined value (if needs) from described phase difference, to make gained phase error (1/2nd such as, negative cycle oscillators are to positive 1/2nd cycle oscillators) in preset range.The control signal that DPLL can produce for described oscillator based on described phase error.
In another aspect, DPLL can comprise synthesis accumulator (synthesizedaccumulator) and TDC.Described synthesis accumulator is determined to export phase place roughly by the number in the cycle of following the trail of oscillator signal.Described synthesis accumulator can be upgraded based on the reference signal with the frequency lower than the frequency of described oscillator signal.Described TDC can determine meticulous output phase place based on the phase difference between described oscillator signal and described reference signal.DPLL can produce control signal for oscillator based on described rough output phase place, described meticulous output phase place and described input phase.
Below various aspects of the present invention and feature are described in more detail.
Accompanying drawing explanation
Fig. 1 shows the block diagram of DPLL.
Fig. 2 shows the chart of the output of TDC to input.
Fig. 3 shows the block diagram of the DPLL operated based on mark input and output phase place.
Fig. 4 shows the operation of synthesis accumulator.
Fig. 5 shows the block diagram of the DPLL with synthesis accumulator.
Fig. 6 shows the block diagram of the phase detectors with synthesis accumulator.
Fig. 7 shows the schematic diagram of TDC.
Fig. 8 shows the block diagram of another DPLL with synthesis accumulator.
Fig. 9 shows the block diagram of communicator.
Figure 10 shows the process for controlling oscillator.
Figure 11 shows another process for controlling oscillator.
Embodiment
Fig. 1 shows the block diagram of the design of DPLL100.In DPLL100, summer 110 receive modulation signal M (t) and to its summation, described modulation signal M (t) for the channel for communicating centre frequency there is quiescent value.Input accumulator 112 add up summer 110 output and input phase P (t) is provided.Frequency inverted is become phase place by described adding up in essence.Trigger input accumulator 112 by reference to signal, described reference signal can have fixed frequency f
ref.Also upgrade various circuit block in DPLL100 and signal by described reference signal, and t is the index of described reference signal.
Radio frequency (RF) accumulator 122 increases progressively one for each cycle oscillator, and cycle oscillator is the one-period of the oscillator signal from controlled oscillator 118.Latch 124 latches the output of RF accumulator 122 and provides rough/integer to export phase place A (t) when being triggered by described reference signal.TDC130 receives described oscillator signal and described reference signal, the phase place of described oscillator signal is determined when being triggered by described reference signal, and provide TDC export F (t), TDC export F (t) indicate between described oscillator signal and described reference signal meticulous/fractional phase is poor.TDC130 implements the fractional phase transducer being used for DPLL100.Summer 126 receives the rough phase place A of output (t) and TDC exports F (t) and sues for peace to it, and provides feedback phase Z (t), and feedback phase Z (t) is the estimation to exporting phase place B (t).
Summer 114 receives feedback phase Z (t) and deducts feedback phase Z (t) from input phase P (t), and provides phase error E (t).Ring wave filter 116 is to described phase error filtering and be provided for the control signal S (t) of oscillator 118.Ring wave filter 116 sets the gyration state of DPLL100.The frequency of described control signal adjustment oscillator 118, to make the phase place of oscillator signal in accordance with the phase place of modulation.Control signal can have the resolution of any suitable number position, such as, and the resolution of 8,12,16,20,24 or more positions.
Oscillator 118 can be digital controlled oscillator (DCO), voltage-controlled oscillator (VCO), current controlled oscillator (ICO), or the oscillator of other type a certain that frequency can be adjusted by control signal.Oscillator 118 can at nominal frequency f
osclower operation, nominal frequency f
osccan by use DPLL100 should be used for determine.For example, DPLL100 can be used for radio communication device, and f
osccan be hundreds of megahertz (MHz) or a few gigahertz (GHz).Described reference signal can be produced based on the oscillator of crystal oscillator (XO), Voltage Controlled Crystal oscillator (VCXO), Temp .-compensation type crystal oscillator (TCXO) or other type a certain with precise frequencies.The frequency of described reference signal can far below the frequency of described oscillator signal.For example, f
refcan be tens MHz, and f
osccan be some GHz.
Can cycle oscillator be that unit is to provide input phase P (t), to export phase place B (t) and feedback phase Z (t).In design in FIG, the feedback path of DPLL100 comprises: (i) RF accumulator 122, and it is in order to measure the rough output phase place provided with the integer number of cycle oscillator; And (ii) TDC130, it is in order to measure the meticulous output phase place provided by the part of a cycle oscillator.RF accumulator 122 always exports phase place B (t) with the measurement in a closed series of TDC130, total export phase place B (t) comprise from RF accumulator 122 rough/integer part and from TDC130 meticulous/fractional part.In description in this article, term " meticulous " and " mark " exchange and use, and term " roughly " and " integer " also exchange use.Feedback phase Z (t) (it is the estimation to exporting phase place) is deducted to obtain the phase error for ring wave filter 116 from described input phase.
The all square frames except RF accumulator 122 in DPLL100 can be operated based on described reference signal.RF accumulator 122 operates based on oscillator signal, much higher times of the comparable described reference signal of frequency of oscillator signal.Therefore, RF accumulator 122 can account for the major part (such as, about 50%) of the total power consumption of DPLL100.Therefore, can need to operate DPLL100 to save the power of battery when RF accumulator 122 cuts out.
In a reference cycle (it is the one-period of reference signal), always can will export phase theta
totalbe given:
θ
total=2 π f
osc/ f
refradian.Equation (1)
Can cycle oscillator be that unit provides total output phase place and can be divided into integer part θ
intwith fractional part θ
frac.The integer number of cycle oscillator or the integral multiple of 2 π radians can provide integer part θ
int.Fractional part θ can be provided by the part of a cycle oscillator or in the scope of 0 to 2 π radians
frac.Integer part θ can be provided as follows
intwith fractional part θ
frac:
and equation (2)
θ
frac=θ
total-θ
int, equation (3)
Wherein
represent lower rounding operation symbol (flooroperator).
RF accumulator 122 is by determining that the number of the cycle oscillator within a reference cycle determines to export the integer part of phase place.TDC130 is by comparing the fractional part determining to export phase place by the phase place of oscillator signal and the phase place of reference signal.
Fig. 2 shows the chart of the output of TDC130 to input.Trunnion axis shows output phase place B (t), and it is the input to TDC130.Vertical axis shows that TDC exports F (t).For trunnion axis and vertical axis, a cycle oscillator equals 2 π.As shown in Figure 2, TDC130 has discontinuous output to input.TDC exports F (t) and equals to export phase place B (t) at 0 to 2 π, then 0 is rapped around to when B (t)=2 π, then increase linearly with B (t) to 4 π at 2 π, then rap around to 0 when B (t)=4 π, by that analogy.
For making DPLL suitably operate, the discontinuity that TDC exports should be solved.The mode solving these discontinuities uses RF accumulator 122 to follow the trail of to export the number of times of phase place B (t) more than 2 π.Then the output of RF accumulator 122 (being the integral multiple of 2 π) can be added to TDC to export, opereating specification is limited to 0 to 2 π, thus avoid discontinuity.But RF accumulator 122 can consume a lot of electric current because of its high frequency of operation.
As shown in Figure 2, TDC exports and jumps every 2 π, but is continuous print within the scope of 2 π between phase step in succession.If the rate of change exporting phase place is limited, then the phase step that TDC exports can be identified when it occurs and be taken into account.For example, can not modulate DPLL100, to make M (t)=0, and P (t) does not have fractional part for all t.Initial condition can be F (0)=0 and A (0)=P (0), to make E (0)=0.Because DPLL is through locking, so control signal S (t) can have steady state value.If input phase has increased slightly (such as, adding 0.1 radian), then TDC130 is by this phase place of measurement and the signal that affords redress (such as, E (t)=-0.1 radian).But slightly reduce (such as, reducing-0.1 radian) if export phase place B (t), then TDC130 will export large value (such as, 2 π-0.1 radians).So phase error will be made to have differed from a cycle period, this adversely may affect the performance of DPLL.
But, if the rate of change exporting phase place is limited, then can by any large change of TDC output within a reference cycle owing to phase step.Then a cycle oscillator can be added to TDC export or deduct a cycle oscillator to obtain correct phase value from TDC output.In the above example, can by TDC export be the large value of 2 π-0.1 radians owing to phase step, from then on can be worth and deduct 2 π, and-0.1 radian can be provided as correct TDC output valve.
In one aspect, when not using RF accumulator, the fractional part exporting phase place and input phase based on the mark from TDC operates DPLL.In each reference cycle, described TDC can be deducted from the fractional part of input phase and export, as follows:
D (t)=P
f(t)-F (t), equation (4)
Wherein P
ft fractional part that () is input phase and in the scope of 0 to 2 π, and
Difference between the fractional part that D (t) is input phase and TDC export, TDC exports the fractional part for exporting phase place.
The rate of change of input phase can be supposed and to export the rate of change of phase place limited, and phase error can be supposed within each reference cycle in the scope of-π to π.So phase error can be determined as follows:
equation (5)
Equation (5) shows the design compared with threshold value+π and-π by D (t).Also D (t) can be compared with other threshold value.
As institute in equation (5) shows, if phase difference is greater than π or is less than-π, then supposition phase step occurs.In the case, 2 π can be added to described phase difference or deduct 2 π from described phase difference, to make gained phase error comparatively close to zero.
Fig. 3 shows the block diagram of the design of the DPLL300 only operated based on input phase and the fractional part exporting phase place.In DPLL300, summer 310 and input accumulator 312 as above for the summer 110 of Fig. 1 and input accumulator 112 described as operate, and provide input phase P (t).Unit 313 receives described input phase and provides fractional part P
f(t).TDC330 receives from the oscillator signal of controlled oscillator 318 and reference signal, and provides TDC to export F (t), TDC export F (t) indicate between described oscillator signal and described reference signal meticulous/fractional phase is poor.Summer 314 is from mark input phase P
ft () deducts TDC and exports F (t), and provide phase difference D (t).Unit 315 receives described phase difference, and determines phase error E (t) (such as, as shown in equation (5)).Ring wave filter 316 to described phase error filtering, and is provided for the control signal S (t) of oscillator 318.
In one design, can use RF accumulator that oscillator 318 is locked onto modulation signal at first.Lock detector (not showing in Fig. 3) can (such as) by observing the value of described phase error determine, whether DPLL300 locked.After DPLL300 is locked, RF accumulator of can stopping using, and can only use the fractional part of input phase and output phase place to operate described DPLL.
In another aspect, synthesis accumulator can be used to determine roughly/integer output phase place.Therefore synthesis accumulator based on described reference signal but not described oscillator signal and operating, and can consume the power of much less than RF accumulator.
Fig. 4 illustrates the operation of the DPLL with synthesis accumulator.In example in the diagram, the frequency of oscillator signal is 3.25 times of the frequency of reference signal, and the frequency control word (FCW) of 3.25 can be provided as the channel frequency in Fig. 1.For the sake of simplicity, assuming that the rising edge based on oscillator signal and reference signal locks and triggers described DPLL.
Oscillator signal is showed in the first row at Fig. 4 top place, and reference signal is showed in second row.The output of RF accumulator is showed in the 3rd row.RF accumulator increases progressively one at each rising edge place of oscillator signal, and therefore follows the trail of cycle oscillator when cycle oscillator occurs.Latch the output of RF accumulator at each rising edge place of reference signal, and each latched value is showed in the circle of the 3rd row.By the number round down of cycle oscillator is obtained each latched value to immediate integer value.For example, in the diagram, there are 3.25 cycle oscillators between the first rising edge of reference signal and the second rising edge, and the output of RF accumulator is 3, it equals through round down 3.25.In the example shown in fig. 4, there are 3.25 cycle oscillators in per reference cycle, and latched value is 0,3,6,9,13 etc.
The output of desirable TDC is showed in the 4th row.The fractional part of the output phase place that described TDC measurement is ignored by round down function.Described fractional part equals the rising edge of reference signal and the difference between immediate rising edge above of oscillator signal.For each rising edge of reference signal, described TDC is provided in the fractional value between 0 and 1.0.As shown in Figure 4, the output of TDC is periodic.By by from TDC meticulous/fractional part with from RF accumulator rough/integer part phase Calais obtains feedback phase.
Being showed in the 5th row through the number that rounds off (it is also called integer increments N (t)) of the cycle oscillator in per reference cycle.For each rising edge of reference signal, N (t) equals current latched value and the difference previously between latched value.In example in the diagram, N (t) is the sequence of 3,3,3,4,3,3,3,4,3 etc.N (t) has mean value 3.25 and exports with TDC is periodic in the same manner.In addition, after DPLL is locked, N (t) only has two possible integer values, is 3 and 4 in its example shown in the diagram.Even if during the DPLL applied when narrow band frequency is modulated, this switching is between two integer values still what set up.For switching between three integer values, needs are greater than reference frequency f by frequency modulation(FM)
ref, can be engaged in the reference cycle to make an extra full cycle oscillator.Usually, peak modulation frequency is the part of reference frequency.For example, peak modulation frequency can be a few MHz, and reference frequency can be tens MHz.In the case, N (t) only has two possible integer values.
If N (t) only can adopt two possible integer values, then likely can not be used in oscillator frequency f
oscn (t) is determined when the RF accumulator of lower operation.Even if by utilize DPLL through modulation time phase error per reference cycle still only have the fact of a small amount of change, can be realized this.For example, crest frequency modulation is for can be about 3MHz the low strap EDGE with 4GHz oscillator and be four points in DPLL output, described reference frequency can be about 57MHz, and per the maximum change of reference cycle input phase can be about 0.3 radian or is about 5% of the reference cycle.Therefore, 2 π phase steps are not covered in described modulation, and the operation of DPLL does not change in essence.
N (t) can be determined as follows when not using RF accumulator.For each reference cycle or update time interval t, two hypothesis by assessment N (t) determine the right value of N (t).First hypothesis a is the situation of the smaller in two values for N (t), and described smaller is expressed as N
land 3 are equaled for the example shown in Fig. 4.Second hypothesis b is the situation of the greater in two values for N (t), and described the greater is expressed as N
hand 4 are equaled for the example shown in Fig. 4.The hypothesis that less phase error value is provided can be selected, and the N for correctly supposing
lor N
hcan be used to upgrade the register storing and count the operation of the number of cycle oscillator.This register provides rough output phase place C (t) provided with the integer number of cycle oscillator.
Described two hypothesis a and b can be assessed as follows.After DPLL is locked, (such as) register described in initialization can be carried out based on the integer part of input phase P (t).In example in the diagram, by initialization of register to zero.At second rising edge place of reference signal, suppose that a has the output phase place Z of hypothesis
a(1)=3+0+0.25=3.25, wherein 3 is the N for supposing a
lvalue, 0 is the rough output phase place C (1) from described register, and 0.25 is TDC output valve.Suppose that b has the output phase place Z of hypothesis
b(1)=4+0+0.25=4.25, wherein 4 is the N for supposing b
hvalue.The output phase place Z of the described hypothesis of described two hypothesis will be used for
aand Z (1)
b(1) compare with input phase P (1)=3.25.Due to Z
a(1) Z is compared
b(1) closer to P (1), so hypothesis a is correct hypothesis.Then (it is the N for correct hypothesis a by 3
lvalue) upgrade register, and described register is stored as the rough output phase place of 3.
At the 3rd rising edge place of reference signal, suppose that a has the output phase place Z of hypothesis
a(2)=3+3+0.5=6.5, wherein first 3 is the N for supposing a
lvalue, second 3 is the rough output phase place C (2) from described register, and 0.5 is TDC output valve.Suppose that b has the output phase place Z of hypothesis
b(2)=4+3+0.5=7.5, wherein 4 is the N for supposing b
hvalue.The output phase place Z of the described hypothesis of described two hypothesis will be used for
aand Z (2)
b(2) compare with input phase P (2)=6.5.Due to Z
a(2) Z is compared
b(2) closer to P (2), so hypothesis a is correct hypothesis.Then (it is the N for correct hypothesis a by 3
lvalue) upgrade described register, and described register is stored as the rough output phase place of 6.Identical process can be repeated for each subsequent reference cycle.
In general, can determine as follows two of N (t) possible integer value:
with
equation (6)
Wherein N
lfor the smaller in two of N (t) possible integer values,
N
hfor the greater in two of N (t) possible integer values, and
rounding operation symbol in expression.
The output phase place of the hypothesis supposing a and b can be determined as follows:
Z
a(t)=N
l+ C (t)+F (t), and equation (7)
Z
b(t)=N
h+ C (t)+F (t), equation (8)
Wherein C (t) is the rough output phase place in reference cycle t,
Z
at () is the output phase place of the hypothesis for supposing a in reference cycle t, and
Z
bt () is the output phase place of the hypothesis for supposing b in reference cycle t.
The phase error of the hypothesis supposing a and b can be determined as follows:
E
a(t)=P (t)-Z
a(t), and equation (9)
E
b(t)=P (t)-Z
b(t), equation (10)
Wherein E
at () is the phase error of the hypothesis for supposing a in reference cycle t, and
E
bt () is the phase error of the hypothesis for supposing b in reference cycle t.
Can upgrade as follows and export phase place roughly:
equation (11)
The phase error E (t) in reference cycle t can be determined as follows:
equation (12)
Phase error from equation (12) can be provided to the ring wave filter in DPLL.
If equation (6) is to as shown in (12), for selecting between two of the N (t) in the given reference cycle possible integer values, described two hypothesis a and b can be assessed.Can select to have closer to the hypothesis of input phase output phase place or there is the hypothesis of less phase error value equivalently.
Fig. 5 shows the block diagram of the design of the DPLL500 with synthesis accumulator.In DPLL500, summer 510 and input accumulator 512 as above for the summer 110 of Fig. 1 and input accumulator 112 described as operate, and provide input phase P (t).
TDC530 receives from the oscillator signal of controlled oscillator 518 and reference signal, and provides TDC to export F (t), and TDC exports F (t) and indicates phase difference between described oscillator signal and described reference signal.Phase detectors 520 receive described oscillator signal, described TDC output and described input phase and produce first phase error E
1(t).Phase detectors 520 comprise RF accumulator 522, latch 524 and summer 526, and it operates as described for the RF accumulator 122 in Fig. 1, latch 124 and summer 114 and 126 above.Enable or inactive phase detectors 520 by mode signal.Phase detectors 540 receive channel frequency, described reference signal, described TDC export and described input phase, and produce second phase error E
2(t).Phase detectors 540 comprise synthesis accumulator and can as mentioned below as implement.Enable or inactive phase detectors 540 by mode signal.Can enable phase detectors 520 or 540 at any given time, and another phase detectors of can stopping using are to save the power of battery.
Multiplexer (Mux) 514 receives respectively from two phase error E of phase detectors 520 and 540
1(t) and E
2(t) and mode signal, and phase error E (t) is provided.Multiplexer 514 provides first phase error E when enabling phase detectors 520
1t () as phase error E (t), and provides second phase error E when enabling phase detectors 540
2t () is as phase error E (t).Ring wave filter 516 pairs of phase error E (t) filtering and be provided for the control signal S (t) of oscillator 518.
In one design, phase detectors 520 can be enabled at first and be used for oscillator 518 to lock onto modulation signal.After DPLL500 is locked, phase detectors 520 of can stopping using, and phase detectors 540 can be enabled.Lock detector 550 receives the first phase error E from phase detectors 520
1(t) and determine that whether DPLL500 is locked.By observation first phase error E
1t the value of () realizes this and determines, first phase error E
1the value of (t) DPLL500 without can be at first during locking large and DPLL500 through locking time can be little.Lock detector 550 provides lock indicator, lock indicator DPLL through locking time can be set to a logical value (such as, ' 1') or at DPLL without being set to another logical value (such as, ' 0') during locking.Mode selector 552 receives described lock indicator and may receive other input do not shown in Fig. 5, and the signal that supplies a pattern.For example, mode selector 552 can at DPLL once locking, or in time after a while, just enables phase detectors 540 and phase detectors 520 of stopping using.Phase detectors 520 and 540 can be enabled in regular period before cutting off RF accumulator 522 simultaneously.Whenever locking loss (such as, the severe jamming owing to DPLL500) being detected, or because of other reason any, mode selector 552 just also can reactivate phase detectors 520.Lock detector 550 and mode selector 552 also can be used for DPLL300 in Fig. 3 to produce phase error without during locking with the output of RF accumulator (not showing in Fig. 3) at DPLL.
The block diagram of the design of the phase detectors 540 in Fig. 6 exploded view 5.In this design, phase detectors 540 comprise synthesis accumulator 610, hypothesis evaluation unit 620 and the unit 630 that rounds off.Rounding off unit 630 can receive channel frequency and determine two of N (t) possible integer values, and it is N
land N
h.Or unit 630 can receive rough output phase place A (t) from the latch 524 in Fig. 5.When phase detectors 520 through enable and DPLL500 through locking time, rough export phase place A (t) should at N
lwith N
hbetween switch.Therefore, after DPLL500 is locked, unit 630 can determine N based on the rough value exporting phase place A (t)
land N
h.
The number of cycle oscillator followed the trail of by synthesis accumulator 610, but based on reference signal but not oscillator signal operate, this can greatly reduce the power consumption of DPLL500.Synthesis accumulator 610 comprises register 612, summer 614 and multiplexer 616.Register 612 stores current coarse with the integer number of cycle oscillator and exports phase place C (t).Multiplexer 616 receives N
land N
hand the selection signal of the hypothesis which indicates be assumed to be correctly/win.In each reference cycle, multiplexer 616 provides N at hypothesis a for during correct hypothesis
land provide N at hypothesis b for during correct hypothesis
h.Summer 614 exports phase place C (t) to the current coarse from register 612 and sues for peace with the output of multiplexer 616 and provide the rough output phase place C (t+1) through upgrading, and the rough phase place C (t+1) that exports is stored in register 612.Equation (11) implemented by register 612, summer 614 and multiplexer 616.
Unit 620 is assessed two hypothesis a and b and is provided phase error E in each reference cycle
2(t) and indicate the selection signal of correct hypothesis.In unit 620, summer 622a receives and exports F (t) and N from rough output phase place C (t) of register 612, TDC
land to its summation, and be provided for the output phase place Z of the hypothesis supposing a
a(t) (as shown in equation (7)).Summer 624a deducts the output phase place Z of hypothesis from input phase P (t)
at () is also provided for the phase error E of hypothesis supposing a
a(t) (as shown in equation (9)).Similarly, summer 622b receives rough output phase place C (t), TDC output F (t) and N
hand to its summation, and be provided for the output phase place Z of the hypothesis supposing b
b(t) (as shown in equation (8)).Summer 624b deducts the output phase place Z of hypothesis from input phase P (t)
bt () is also provided for the phase error E of hypothesis supposing b
b(t) (as shown in equation (10)).
Selector 626 receives the phase error E of the hypothesis being used for described two hypothesis
a(t) and E
b(t) and determine described two hypothesis phase errors in less value.Selector 626 provides the phase error of the hypothesis with less value as the phase error E from phase detectors 540
2(t) (as shown in equation (12)).Selector 626 also provides selection signal, the correct hypothesis of the phase error value of hypothesis less described in described selection signal designation produces.
Fig. 4 and Fig. 6 shows design RF accumulator being exported round down (such as, from 3.25 round downs to 3, from 6.5 round downs to 6 etc.).In the case, for each hypothesis, TDC is exported F (t) and add rough output phase place C (t) to.In another design, RF accumulator is exported round-up (such as, from 3.25 round-ups to 4, from 6.5 round-ups to 7 etc.).In the case, for each hypothesis, deduct TDC from the rough phase place C of output (t) and export F (t) (not showing Fig. 4 or Fig. 6).In general, mode that can be consistent with the mode upgrading described synthesis accumulator assesses described hypothesis.
Fig. 6 shows for there being two integer value N during the normal running of DPLL500
land N
hsituation, synthesis accumulator 610 and the example design of hypothesis evaluation unit 620.N (t) can have plural possible integer value, such as, for wide-band modulation or when DPLL500 first time powers up.Compensate owing to the larger difference on the frequency of wide-band modulation by rough output phase place correction factor is applied to from described synthesis accumulator.In general, a hypothesis can be assessed for the integer value that each of N (t) is possible.The hypothesis with minimum phase error can be selected, and described synthesis accumulator can be upgraded based on N (t) value of selected hypothesis.
In one design, the RF accumulator that DPLL operates under being included in oscillator frequency and the synthesis accumulator (such as, as shown in Figure 5) operated under reference frequency.As above for described by Fig. 5, RF accumulator can be used when operating and starting, and after DPLL is locked, synthesis accumulator can be used between error-free running period.
In another design, the synthesis accumulator that DPLL operates under being only included in reference frequency.Operate start time, can more for the more possible values assessment of N (t) (such as, three, four or may be more) suppose.After DPLL is locked, can suppose for less possible N (t) value assessment less (such as, two).Or, when operating beginning with the hypothesis (such as, supposing for two) can assessing identical number in the normal operation period.Endless belt can be selected wide, to realize desired acquisition performance by a limited number of possible N (t) value.
DPLL500 in Fig. 5 can operate with the mode of the DPLL300 equivalence in Fig. 3.When DPLL500 is through locking, the integer part (it is rough output phase place C (t) from synthesis accumulator 610) of described hypothesis phase place should mate the integer part of input phase.These two integer parts of cancellation will be carried out by summer 624a and 624b in Fig. 6, and at phase error E
2in (t), will only provide the difference between fractional part.
The schematic diagram of the design of the TDC530 in Fig. 7 exploded view 5.The phase place of oscillator signal and the phase place of reference signal compare by TDC530, and provide the phase difference detected of the resolution with multiple (B) position.
TDC530 comprises 2
bindividual delay element 710a to 710z, 2
bindividual d type flip flop 712a to 712z, and thermometer/binary translator (thermometer-to-binaryconverter) 714.Delay element 710a to 710z through series coupled, wherein delay element 710a reception oscillator signal.The logic element of useful inverter and/or other type implements each delay element 710, to obtain desired delay resolution.Delay element 710a to 710z provides the total delay of an about cycle oscillator.For example, if oscillator frequency f
oscfor 4GHz, then a cycle oscillator is 250 psecs (ps), and each delay element 710 provides about 250/2
bthe delay of ps.
D type flip flop 712a to 712z makes its D input the output of being coupled to delay element 710a to 710z respectively, and the input of its clock receives reference signal.Each d type flip flop 712 to from the delay element 710 be associated output signal sampling and sampled output is provided to transducer 714.The number being in the high d type flip flop of logic is to the phase difference be between the number instruction oscillator signal of d type flip flop of logic low and reference signal.This phase difference has 1/2
bthe resolution of cycle oscillator.Transducer 714 receives from d type flip flop 712a to 712z 2
bindividual output, by these 2
bindividual output converts B position binary value to, and provides described B position binary value to export phase place as meticulous/mark.
In general, TDC530 can be designed by the resolution of any number position.For example, depending on desired delay resolution, minimum delay etc. available in integrated circuit (IC) technique, B can be 8 or larger.Desired delay resolution is determined by using the application of DPLL500.
DPLL can be used for various application.For example, DPLL can be used for frequency synthesizer with produce want under frequency oscillator signal.In the case, modulation signal M (t) can be omitted or set it to zero.DPLL also can be used for polarity modulator (polarmodulator), quadrature modulator (quadraturemodulator), phase-modulator, frequency modulator, demodulator etc.For modulator, the bandwidth of modulation signal can be greater than the closed-loop bandwidth of DPLL.DPLL can be designed to adapt to the wide bandwidth of modulation signal.
Fig. 8 shows the block diagram of the design of the DPLL302 supporting wide-band modulation.DPLL302 comprises all square frames in the DPLL300 in Fig. 3.DPLL302 comprises unit for scaling (scalingunit) 320 and summer 317 further.
DPLL302 implements at 2 or type of dual-port modulation is modulated to realize high bandwidth.Modulation signal M (t) can be provided to low-pass modulation path and high-pass modulation path.In low-pass modulation path, summer 310 and input accumulator 312 pairs of modulation signals M (t) operate and provide input phase P (t).That is undertaken by input accumulator 312 cumulative becomes phase place by frequency inverted in essence.In high-pass modulation path, unit for scaling 320 receives modulation signal M (t) and carries out convergent-divergent with gain g (t) to it and provide the second modulation signal X (t).Summer 317 is coupled between the output of ring wave filter 316 and the input of oscillator 318.Summer 317 is sued for peace to the phase error signal through filtering from ring wave filter 316 and the second modulation signal X (t) from unit for scaling 320 and is provided for the control signal S (t) of oscillator 318.
The bandwidth of modulation signal can by use DPLL302 should be used for determining and the closed-loop bandwidth of comparable DPLL is wide.The bandwidth in the low-pass modulation path in DPLL302 be determined by ring wave filter 316 and can relative narrower (such as, being less than 100KHz) to realize desired noise filtering and gyration state.By carrying out application of modulation signal M (t) via independent high pass and low-pass modulation path, DPLL302 the signal bandwidth wider than the closed-loop bandwidth of DPLL can carry out modulating oscillator 318.
For the sake of simplicity, Fig. 3, Fig. 5 and Fig. 8 show respectively DPLL300,500 and 502 function square frame.For clarity sake, specific detail is eliminated.For example, the appropriate position be inserted in DPLL300,302 and 500 can be postponed, to make the various signals suitably time alignment in these DPLL.
Fig. 3, Fig. 5 and Fig. 8 show some example design of modulation DPLL.Also can implement to modulate DPLL with other design, some in described design be described in issue on June 21st, 2005 be entitled as " phase-locked loop (PHASELOCKEDLOOPHAVINGAFORWARDGAINADAPTATIONMODULE) with forward gain adaptation module " the 6th, in 909, No. 331 United States Patent (USP)s.Described in the the 6th, 909, No. 331 United States Patent (USP), gain g (t) in high-pass modulation path can be determined.
For DPLL300 corresponding in Fig. 3, Fig. 5 and Fig. 8,500 and 302, the continuity exporting phase place may be upset to the interference of oscillator.This interference can be derived from the wink property the sent out fluctuation in power supply, the puppet coupling etc. from other ring.In general, if the value of the peak value output phase shift in per reference cycle is less than 1/2nd reference cycles, then disturb and do not bother, it will be normal conditions.Therefore, these DPLL can provide sane performance.
Fig. 9 shows the block diagram of the design of the communicator 900 adopting DPLL described herein.Device 900 can be used in radio communication device, cellular phone, personal digital assistant (PDA), handheld apparatus, radio modem, cordless telephone, radio station, bluetooth (Bluetooth) device etc.Device 900 also can be used in the various wireless communication systems such as such as code division multiple access (CDMA) system, time division multiple access (TDMA) system, frequency division multiple access (FDMA) system, orthogonal FDMA (OFDMA) system, WLAN (WLAN).Device 900 can support the such as cdma wireless power technology such as cdma2000, wideband CDMA (W-CDMA).Device 900 also can support the TDMA radiotechnics of such as global system for mobile communications (GSM).These various systems and radiotechnics are known in technique.
In device 900, data that data processor 910 can process (such as, coding and modulation) are to obtain symbol.Processor 910 also can come according to the radiotechnics for communicating other process (such as, spread spectrum, scramble etc.) of described semiology analysis to obtain stowed value sample.Processor 910 can providing package containing the real part of each stowed value sample in-phase data signal I (t) and comprise orthogonal data signals Q (t) of imaginary part of each stowed value sample.Orthogonal/polarity switch (quadrature-to-polarconverter) 920 can receive I (t) and Q (t) data-signal, by each stowed value sample from Descartes (Cartesian) Coordinate Conversion to polar coordinates, and provide envelope signal Y (t) and phase signal θ (t).
In envelope depth, envelope signal can be multiplied with gain G by multiplier 922, to obtain desired output power levels.Delay cell 924 can provide programmable retardation to make described envelope signal and described phase signal time alignment.The filter response that filter 926 can be suitable for comes delayed envelope signal filtering.Envelope signal through filtering can be transformed into simulation and provide output envelope signal by D/A converter (DAC) 928.The gain of power amplifier (PA) 954 is changed to realize Modulation and Amplitude Modulation by described output envelope signal.
In phase path, differentiator 930 can carry out differential to phase signal θ (t) and provide modulation signal M (t), and modulation signal M (t) can containing the frequency component of I (t) with Q (t) data-signal.DPLL940 can receive modulation signal M (t) and produce the control signal S (t) being used for DCO950.DPLL302 in DPLL500 or Fig. 8 in DPLL300, Fig. 5 in useful Fig. 3 implements DPLL940.DCO950 can produce the signal through phase-modulation modulated by described modulation signal.Amplifier (Amp) 952 can amplify the described signal through phase-modulation.The output of amplifier 952 can be amplified based on the envelope signal exported and provide through phase-modulation and output signal through amplitude-modulated RF by PA954 further.
Data processor 910 in controller/processor 960 controllable device 900 and the operation of other square frame.Memory 962 can store data for controller/processor 960 and/or other square frame and program code.
The various square frames in device for carrying out said 900 can be carried out in a digital manner.For example, available one or more digital signal processors (DSP), Reduced Instruction Set Computer (RISC) processor, CPU (CPU) etc. implement processor 910 to filter 926, differentiator 930, DPLL940 and controller/processor 960.Described digital square frame may be implemented on one or more application-specific integrated circuit (ASIC)s (ASIC) and/or other integrated circuit (IC).Available analog circuit carrys out the residue square frame in device for carrying out said 900.The part of DCO950, amplifier 952 and/or PA954 may be implemented in one or more RFIC (RFIC), analog IC, mixed-signal IC etc.
Figure 10 shows the design of the process 1000 for controlling oscillator (such as, DCO, VCO etc.).Can add up can comprise modulation signal at least one input signal to obtain input phase (square frame 1012).Can determine that phase difference (such as, with TDC) between oscillator signal and reference signal is to obtain the fractional part (square frame 1014) of the output phase place for described oscillator signal.
Only can determine phase error (square frame 1016) based on the fractional part of input phase and the described fractional part of described output phase place.Described fractional part can have the scope of the one-period of described oscillator signal.For square frame 1016, the phase difference between the fractional part of described output phase place and the fractional part of described input phase can be determined.If described phase difference is less than the first value (such as, 1/2nd negative cycle oscillators), then predetermined value (such as, a cycle oscillator) can be added to described phase difference.If described phase difference is greater than the second value (such as, 1/2nd positive cycle oscillators), then can deduct predetermined value from described phase difference.May be provided in and add or deduct phase difference (if any) after described predetermined value using as phase error.The control signal (square frame 1018) that can produce for oscillator based on described phase error.
Number (such as, using RF accumulator) by the cycle of following the trail of oscillator signal determines the integer part of described output phase place.When without locking, based on the integer of input phase and fractional part and the integer of phase place can be exported and fractional part determines described phase error.When through locking, only can determine described phase error based on the fractional part of input phase and the fractional part of output phase place.
Figure 11 shows the design of the process 1100 for controlling oscillator (such as, DCO, VCO etc.).Can determine to export roughly phase place C (t) (such as based on the number of reference signal by the cycle of following the trail of the oscillator signal of self-oscillator, with synthesis accumulator), described reference signal has the frequency (square frame 1112) lower than the frequency of described oscillator signal.Can determine based on the phase difference between described oscillator signal and described reference signal meticulous output phase place F (t) (such as, with TDC) (square frame 1114).Phase error E (t) (square frame 1116) can be determined based on described rough output phase place, described meticulous output phase place and input phase P (t).The control signal S (t) (square frame 1118) that can produce for oscillator based on described phase error.
For square frame 1112, can by the first integer value N in each interval update time (such as, each reference cycle)
lor the second integer value N
hupgrade and export phase place roughly.Described first integer value and described second integer value can be the continuous integral number value determining (such as, as shown in equation (6)) based on the frequency of oscillator signal and the frequency of reference signal.Can in each interval update time based on described first integer value and described second integer value, export phase place, meticulous output phase place and input phase roughly and assess two hypothesis for described first integer value and described second integer value.Phase place can be exported roughly based on being upgraded by described first integer value or described second integer value the result of assessments of described two hypothesis.For example, the output phase place Z of the first hypothesis can be determined based on described first integer value, rough output phase place and meticulous output phase place
a(t).The output phase place Z of the second hypothesis can be determined based on described second integer value, rough output phase place and meticulous output phase place
b(t).(i) described rough output phase place can be upgraded by described first integer value or (ii) by described second integer value closer to when input phase than the output phase place of described second hypothesis in the output phase place of described first hypothesis.
In the first duration, (such as, when operating beginning) is determined to export phase place A (t) roughly based on the number of oscillator signal by the cycle of following the trail of oscillator signal.In the second duration, (such as, after realizing locking) is determined to export phase place C (t) roughly based on the number of reference signal by the cycle of following the trail of oscillator signal.
DPLL described herein is implemented by various means.For example, described DPLL may be implemented in hardware, firmware, software or its combination.For hardware embodiments, one or more DSP available, digital signal processing device (DSPD), programmable logic device (PLD), field programmable gate array (FPGA), processor, controller, microcontroller, microprocessor, electronic installation, through design with other electronic unit or digital circuit, the computer that perform function described herein, or it combines the square frame implemented in described DPLL.
Described DPLL also may be implemented on IC, analog IC, digital IC, RFIC, mixed-signal IC, ASIC, printed circuit board (PCB) (PCB), electronic installation etc.Also can manufacture described DPLL by various IC technology, such as complementary metal oxide semiconductors (CMOS) (CMOS), N-channel MOS (N-MOS), P channel MOS (P-MOS), bipolar junction transistor (BJT), bipolar CMOS (BiCMOS), SiGe (SiGe), GaAs (GaAs) etc.
For firmware and/or Software implementations, the square frame in DPLL implemented by the code (such as, program, function, module, instruction etc.) of the function that available execution is described herein.In general, any computer/processor-readable media visibly comprising firmware and/or software code can be used for implementing technology described herein.For example, firmware and/or software code can be stored in memory (memory 962 such as, in Fig. 9) and to be performed by processor (such as, processor 960).Memory may be implemented in processor or processor outside.Firmware and/or software code also can be stored in computer/processor-readable media, such as random access memory (RAM), read-only memory (ROM), nonvolatile RAM (NVRAM), programmable read only memory (PROM), electric erasable PROM (EEPROM), flash memory, floppy disk, compact disk (CD), digital versatile disc (DVD), magnetic or optical data storage device etc.Described code can be performed by one or more computer/processor and described computer/processor can be caused to perform functional particular aspects described herein.
The equipment implementing DPLL described herein can be self-contained unit or can be the part compared with bigger device.Device can be: (i) independent IC; (ii) set of one or more IC, it can comprise the memory IC for storing data and/or instruction; (iii) the such as RFIC such as RF receiver (RFR) or RF emitter/receiver (RTR); (iv) ASIC such as such as mobile station modem (MSM); V () can be embedded in the module in other device; (vi) receiver, cellular phone, wireless device, hand-held set or mobile unit; (vii) etc.
There is provided previous description of the present invention can make to make those skilled in the art or use the present invention.Those skilled in the art will easily understand various amendment of the present invention, and without departing from the scope of the invention, the General Principle defined herein can be applicable to other change.Therefore, do not wish that the present invention is limited to example described herein and design, and by its widest scope consistent with principle disclosed herein and novel feature of imparting.
Claims (10)
1. an electronic equipment, it comprises:
Oscillator, it is configured to produce oscillator signal; And
Digital phase-locked loop DPLL, it is configured to receive from the described oscillator signal of described oscillator and reference signal and the control signal produced for described oscillator, the number that described DPLL comprises the cycle be configured to by recording described oscillator signal determines the synthesis accumulator comprising register exporting roughly phase place, described synthesis accumulator is updated based on the described reference signal with the frequency lower than the frequency of described oscillator signal
Wherein said DPLL is configured to determine input phase by cumulative modulation signal further,
Wherein said DPLL comprise further time/digital quantizer TDC, described TDC be configured to determine meticulous output phase place based on the phase difference between described oscillator signal and described reference signal,
Wherein, the described control signal for described oscillator is determined based on described rough output phase place, described meticulous output phase place and described input phase.
2. equipment according to claim 1, wherein said synthesis accumulator was upgraded by the first integer value or the second integer value in interval in each update time, and described first and second integer values are the continuous integral number values determined by the described frequency of described oscillator signal and the described frequency of described reference signal.
3. equipment according to claim 2, wherein said DPLL comprises assessment unit further, described assessment unit is configured to assess described first integer-valued hypothesis and described second integer-valued hypothesis in interval in each update time, and based on the instruction provided the result of described assessments of described two hypothesis being upgraded described synthesis accumulator in each interval by the described first or second integer value update time.
4. equipment according to claim 3, wherein said assessment unit is configured to assess described two hypothesis based on described first and second integer values, described rough output phase place, described meticulous output phase place and input phase.
5. equipment according to claim 4, wherein said assessment unit is configured to based on described first integer value, described rough output phase place and described meticulous output phase place determine the output phase place of the first hypothesis, based on described second integer value, described rough output phase place and described meticulous output phase place determine the output phase place of the second hypothesis, and provide to when the output phase place of described first hypothesis than the output phase place of described second hypothesis closer to upgrading described synthesis accumulator by described first integer value when described input phase or otherwise being upgraded the instruction of described synthesis accumulator by described second integer value.
6. equipment according to claim 4, wherein said assessment unit is configured to based on described first integer value, described rough output phase place, described meticulous output phase place and described input phase determine the phase error of the first hypothesis, based on described second integer value, described rough output phase place, described meticulous output phase place and described input phase determine the phase error of the second hypothesis, and provide upgrading described synthesis accumulator when the value of phase error of described first hypothesis is less than the value of the phase error of described second hypothesis by described first integer value or otherwise being upgraded the instruction of described synthesis accumulator by described second integer value.
7. equipment according to claim 1, wherein said DPLL comprises further:
Radio frequency (RF) accumulator, the number in its cycle be configured to by recording described oscillator signal determines described rough output phase place, and described RF accumulator operates based on described oscillator signal.
8. equipment according to claim 7, wherein said RF accumulator is activated within the first duration, and is deactivated within the second duration, and wherein said synthesis accumulator is activated within described second duration.
9. equipment according to claim 7, wherein said DPLL comprises lock detector further, described lock detector is configured to determine that whether described DPLL is through locking, and wherein enable described RF accumulator at described DPLL without during locking, and after described DPLL locks, enable described synthesis accumulator.
10., for controlling a method for oscillator, it comprises:
Based on reference signal, the number being carried out the cycle of the oscillator signal of self-oscillator by record is determined to export phase place roughly, described reference signal has the frequency lower than the frequency of described oscillator signal, wherein, described rough output phase place is determined by synthesis accumulator, and wherein said synthesis accumulator upgrades based on described reference signal;
Phase error is determined based on described rough output phase place and input phase; And
The control signal produced for described oscillator based on described phase error,
Wherein said synthesis accumulator was upgraded by the first integer value or the second integer value in interval in each update time, and described first integer value and the second integer value are the continuous integral number values determined by the described frequency of described oscillator signal and the described frequency of described reference signal.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200880118247.6A CN101878594B (en) | 2007-11-29 | 2009-01-12 | The digital phase-locked loop operating based on mark input and output phase place |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200880118247.6A Division CN101878594B (en) | 2007-11-29 | 2009-01-12 | The digital phase-locked loop operating based on mark input and output phase place |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102843128A CN102843128A (en) | 2012-12-26 |
| CN102843128B true CN102843128B (en) | 2015-11-18 |
Family
ID=47370231
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210266806.6A Expired - Fee Related CN102843128B (en) | 2009-01-12 | 2009-01-12 | The digital phase-locked loop operated based on mark input and output phase place |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102843128B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102013114367B4 (en) * | 2013-12-18 | 2017-02-02 | Intel IP Corporation | A circuit, method and synthesizer for generating a synthesized signal at a selectable frequency |
| US9391625B1 (en) * | 2015-03-24 | 2016-07-12 | Innophase Inc. | Wideband direct modulation with two-point injection in digital phase locked loops |
| CN110673822A (en) * | 2019-09-29 | 2020-01-10 | 杭州万高科技股份有限公司 | Electric energy metering microprocessor, inner core thereof, energy accumulation circuit and method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1960164A (en) * | 2006-10-27 | 2007-05-09 | 清华大学 | CMOS of chip digital controlled complementary type LC oscillator in low noise |
| US7279988B1 (en) * | 2005-03-17 | 2007-10-09 | Rf Micro Devices, Inc. | Digital frequency locked loop and phase locked loop frequency synthesizer |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7532679B2 (en) * | 2004-08-12 | 2009-05-12 | Texas Instruments Incorporated | Hybrid polar/cartesian digital modulator |
-
2009
- 2009-01-12 CN CN201210266806.6A patent/CN102843128B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7279988B1 (en) * | 2005-03-17 | 2007-10-09 | Rf Micro Devices, Inc. | Digital frequency locked loop and phase locked loop frequency synthesizer |
| CN1960164A (en) * | 2006-10-27 | 2007-05-09 | 清华大学 | CMOS of chip digital controlled complementary type LC oscillator in low noise |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102843128A (en) | 2012-12-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101878594B (en) | The digital phase-locked loop operating based on mark input and output phase place | |
| US8019301B2 (en) | Calibration techniques for frequency synthesizers | |
| JP5256535B2 (en) | Phase-locked loop circuit | |
| US8830001B2 (en) | Low power all digital PLL architecture | |
| US10771072B2 (en) | Frequency generator and associated method | |
| CN105827238B (en) | System and method for calibrating dual-port phase-locked loop | |
| US7915935B1 (en) | Communication systems w/counter-based frequency centering for mm-wave frequency bands | |
| US20100073095A1 (en) | Frequency Synthesizer and Radio Transmitting Apparatus | |
| CN102843128B (en) | The digital phase-locked loop operated based on mark input and output phase place | |
| US7642861B2 (en) | Locked loop system | |
| EP1297619B1 (en) | Linear dead-band-free digital phase detection | |
| WO2009083501A2 (en) | A phase locked loop | |
| US10270487B2 (en) | Frequency generator and associated method | |
| JP2012147080A (en) | Delta-sigma modulation-type fraction division pll frequency synthesizer, and wireless communication device having the same | |
| Akamine et al. | A polar loop transmitter with digital interface including a loop-bandwidth calibration system | |
| WO2006019734A2 (en) | Direct modulator for shift keying modulation | |
| CN110995259A (en) | Frequency synthesizer for hand-held type ultrashort wave frequency hopping radio station | |
| US20230082930A1 (en) | Monitoring circuit of phase locked loop and operating method thereof | |
| JP4641325B2 (en) | PLL frequency synthesizer | |
| US20080258942A1 (en) | Sigma-delta multiplier, phase-locked loop with extended tuning range and methods for generating rf signals | |
| Alaimo | Fractional-N synthesizer simplifies UHF sensor radio | |
| Unterassinger et al. | Investigation of two-point modulation to increase the GFSK data rate of PLL-based wireless transceivers of wireless sensor nodes |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20151118 Termination date: 20220112 |