CN102842654B - A kind of amorphous silicon thin-film solar cell low-power chip analysis processing method - Google Patents
A kind of amorphous silicon thin-film solar cell low-power chip analysis processing method Download PDFInfo
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- CN102842654B CN102842654B CN201210303317.3A CN201210303317A CN102842654B CN 102842654 B CN102842654 B CN 102842654B CN 201210303317 A CN201210303317 A CN 201210303317A CN 102842654 B CN102842654 B CN 102842654B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a kind of amorphous silicon thin-film solar cell low-power chip analysis processing method, comprise the following steps: (1) sticks on a label to each low-power chip, the corresponding ID of each label, this label at least comprises following information: the time of a, critical process, b, cvd furnace batch, the said shank of c, electrode position; (2) ID is corresponding one by one with electric performance test result and be stored on test computer, by corresponding with electric performance test result for the ID of all low-power chips and be pooled to unique database; (3) during certain low-power chip of Water demand, by analyzing the ID of this low-power chip, extracting all electric performance test results on its label, presenting with data list or graph mode.Can be obtained effectively by the present invention, targetedly, accurately, complete visual information, significantly improve efficiency and the accuracy of analyzing and processing amorphous silicon thin-film solar cell low-power chip.
Description
Technical field
The present invention relates to a kind of amorphous silicon thin-film solar cell low-power chip analysis processing method, particularly relate to a kind of amorphous silicon thin-film solar cell low-power chip analysis processing method that can obtain visual information targetedly.
Background technology
For amorphous silicon thin-film solar cell, the successive sedimentation of general employing multicell or single chamber batch deposition, for both of these case, common ground is that the performance of each battery is relevant to its batch, therefore when analyzing certain bad chip, the performance information of its related chip to analytic process and processing method extremely important.
There is following defect in current amorphous silicon thin-film solar cell low-power chip analysis processing method:
1, low-power chip information does not have specific aim: can not provide the customizing messages for low-power chip from existing MES system or record of production table, and needs personnel's manual screening from mass data, obtains information accurately after comparison;
2, low-power chip information is imperfect: the information pointer that existing MES system or record of production table intuitively present is to conventional products, the relevant information needed for analysis of rejects does not comprise complete, twin of such as same electrode, the Related product of same heat does not comprise in the information of different phase;
3, low-power chip information is directly perceived or cannot directly use: show by a large amount of digital form the electrical property of low-power chip, but not the intuitively display such as chart, and numeral may not directly shift, as copied, printing etc., be unfavorable for carrying out smoothly of the analyzing and processing process of low-power chip;
4, analyzing and processing process efficiency is low, accuracy is low: the information obtained due to existing means does not have specific aim, imperfect, directly perceived, causes technical staff to need at substantial energy to go finishing collecting data, and the process that may make the mistake.
Summary of the invention
Object of the present invention is just to provide a kind of amorphous silicon thin-film solar cell low-power chip analysis processing method that can obtain visual information targetedly to solve the problem.
In order to achieve the above object, present invention employs following technical scheme:
Amorphous silicon thin-film solar cell low-power chip analysis processing method of the present invention, comprise the following steps: (1) sticks on a label to each low-power chip, the corresponding ID of each label, this label at least comprises following information: the time of a, critical process, b, cvd furnace batch, the said shank of c, electrode position; (2) ID is corresponding one by one with electric performance test result and be stored on test computer, by corresponding with electric performance test result for the ID of all low-power chips and be pooled to unique database; (3) during certain low-power chip of Water demand, by analyzing the ID of this low-power chip, extracting all electric performance test results on its label, presenting with data list or graph mode.
Particularly, in described step (1), described critical process is: using plasma strengthens chemical vapour deposition technique (being called for short PECVD) deposited silicon film as sunlight absorbed layer.
In described step (3), when described electric performance test result is the unit for electrical property parameters of the twin of same electrode position of this chip, present with data list or graph mode; When described electric performance test result is the electric performance test result of same batch of this chip, present with data list or graph mode; When described electric performance test result is the abnormality processing historical information of this chip, present in data list mode.
Beneficial effect of the present invention is:
Can be obtained effectively by the present invention, targetedly, accurately, complete visual information, significantly improve efficiency and the accuracy of analyzing and processing amorphous silicon thin-film solar cell low-power chip, and improve product yield, production efficiency, save production cost.
Accompanying drawing explanation
Fig. 1 is the software interface figure of the embodiment of the present invention 1;
Fig. 2 is the software interface figure of the embodiment of the present invention 2;
Fig. 3 is the software interface figure of the embodiment of the present invention 3.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment, the present invention is further described in detail:
Amorphous silicon thin-film solar cell low-power chip analysis processing method of the present invention is as follows: first, a label is sticked on to each low-power chip, the corresponding ID of each label, this label at least comprises following information: the time of a, critical process, b, cvd furnace batch, the said shank of c, electrode position; Then, ID is corresponding one by one with electric performance test result and be stored on test computer, by corresponding with electric performance test result for the ID of all low-power chips and be pooled to unique database; Finally, when needed analyzing and processing is carried out to amorphous silicon thin-film solar cell low-power chip.Above-mentioned critical process is: using plasma strengthens chemical vapour deposition technique (being called for short PECVD) deposited silicon film as sunlight absorbed layer.
Above-mentioned database purchase is in software systems, and the process that the later stage carries out analyzing and processing to low-power chip is also based on the interface of these software systems.
Below in conjunction with the embodiment of carrying out analyzing and processing for different low-power chips, the present invention is further described in detail:
Embodiment 1:
Analyzing and processing PECVD abnormal chips: as shown in Figure 1, after the low-power chip of input numbering HA212032801141105T, software demonstrates this chip through process, and be judged as " regeneration ", its twin chip testing electrical property is close to (the left list), be all low-power, all do not form assembly (right side list is for empty), the chip major part with batch (72) forms qualified component (lower diagrams).Therefore can reach a conclusion: chip low-power reason is " RF electrode is abnormal ", and processing mode is " regeneration ".
Embodiment 2:
Analyzing and processing micro-short circuit chip: as shown in Figure 2, after the low-power chip of input numbering HA212041401136253T, software demonstrates this chip through process, and be judged as " micro-short circuit ", its test record shows that power is about surveyed higher (the left list), its twin chip testing electrical property be difference large (the left list) with it, all normal, and form assembly (right side list), chip major part with batch (72) forms qualified component (lower diagrams), comprises 4 twin (black).Therefore can reach a conclusion: chip low-power reason is " micro-short circuit ", processing mode is " secondary back-pressure ", and result is for making qualified product.
Embodiment 3:
The bad chip of analyzing and processing groove: as shown in Figure 3, after the low-power chip of input numbering HA212041715539103T, software demonstrates this chip through process, and be judged as " micro-short circuit ", its test record shows power P m and the proportional reduction of open circuit voltage Voc, short circuit current Isc normal (the left list), its twin chip testing electrical property be difference large (the left list) with it, all normal, and form assembly (right side list), chip major part with batch (72) forms qualified component (lower diagrams), comprise 4 twin (black).Therefore can reach a conclusion: chip low-power reason is " P3 is not carved off ", then after observing chip itself, provide processing mode for " P3 heavily carves ", result is for making qualified product.
Claims (1)
1. an amorphous silicon thin-film solar cell low-power chip analysis processing method, it is characterized in that: comprise the following steps: (1) sticks on a label to each low-power chip, the corresponding ID of each label, this label at least comprises following information: the time of a, critical process, b, cvd furnace batch, the said shank of c, electrode position; (2) ID is corresponding one by one with electric performance test result and be stored on test computer, by corresponding with electric performance test result for the ID of all low-power chips and be pooled to unique database; (3) during certain low-power chip of Water demand, by analyzing the ID of this low-power chip, extracting all electric performance test results on its label, presenting with data list or graph mode; In described step (1), described critical process is: using plasma strengthens chemical vapor deposition silicon fiml as sunlight absorbed layer; In described step (3), when described electric performance test result is the unit for electrical property parameters of the twin of same electrode position of this chip, present with data list or graph mode; When described electric performance test result is the electric performance test result of same batch of this chip, present with data list or graph mode; When described electric performance test result is the abnormality processing historical information of this chip, present in data list mode.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6314379B1 (en) * | 1997-05-26 | 2001-11-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated defect yield management and query system |
| CN1510729A (en) * | 2002-12-23 | 2004-07-07 | 力晶半导体股份有限公司 | Water testing parameter analytical method |
| CN102135597A (en) * | 2010-11-08 | 2011-07-27 | 上海集成电路研发中心有限公司 | Data processing method for testing parameters of chips |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6314379B1 (en) * | 1997-05-26 | 2001-11-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated defect yield management and query system |
| CN1510729A (en) * | 2002-12-23 | 2004-07-07 | 力晶半导体股份有限公司 | Water testing parameter analytical method |
| CN102135597A (en) * | 2010-11-08 | 2011-07-27 | 上海集成电路研发中心有限公司 | Data processing method for testing parameters of chips |
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