CN102842517B - Chip bonding method and device - Google Patents
Chip bonding method and device Download PDFInfo
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- CN102842517B CN102842517B CN201210312484.4A CN201210312484A CN102842517B CN 102842517 B CN102842517 B CN 102842517B CN 201210312484 A CN201210312484 A CN 201210312484A CN 102842517 B CN102842517 B CN 102842517B
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- packaging
- base plate
- semiconductor chip
- tool
- bracing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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Abstract
The invention provides a kind of chip bonding method and device.The method comprises: put one first semiconductor chip on a base plate for packaging, the wherein first surface of this base plate for packaging of bump contact of this first semiconductor chip; Fix this base plate for packaging; And heat this base plate for packaging and this first semiconductor chip, wherein in heating process, the distortion of this base plate for packaging is restricted, and this first semiconductor chip can freely be out of shape.
Description
Technical field
The present invention about semiconductor packages, in detail, about chip bonding method and the device of three-dimensional (3D) semiconductor packages.
Background technology
Known chip bonding method is as follows.First, a base plate for packaging and semiconductor chip are provided.This base plate for packaging has a first surface and a second surface, and this semiconductor chip has an active surface and several projection, and these projections are positioned at this active surface.Then, this semiconductor chip is placed on this base plate for packaging, and the first surface of these these base plate for packaging of bump contact of this semiconductor chip.Then, utilize a thermal head to push down simultaneously and heat this base plate for packaging and this semiconductor chip, to make these bump bond to this base plate for packaging.
The shortcoming of this known chip bonding method is, the manufacturing cost of this thermal head is quite high, and hot pressing time must be quite of a specified duration.
Summary of the invention
The one side of this exposure is about a kind of chip bonding method, comprise the following steps: (a) provides a base plate for packaging and one first semiconductor chip, this base plate for packaging has a first surface and a second surface, this first semiconductor chip has an active surface and several projection, and these projections are positioned at this active surface; B this first semiconductor chip is placed on this base plate for packaging by (), wherein the first surface of these these base plate for packaging of bump contact of this first semiconductor chip; C this base plate for packaging and this first semiconductor chip, after this step (b), are placed on a bracing or strutting arrangement (Holder) by (), wherein this bracing or strutting arrangement holds the second surface of this base plate for packaging via pull of vacuum; And (d) heats this base plate for packaging and this first semiconductor chip, wherein in heating process, this bracing or strutting arrangement continues to hold this base plate for packaging.
The another aspect of this exposure is about a kind of chip bonding device, and it comprises a tool and several heater.This tool holds a base plate for packaging via pull of vacuum, and wherein one first semiconductor chip is positioned on this base plate for packaging.These heaters are in order to heat this base plate for packaging, this first semiconductor chip and this tool, and wherein the position of these heaters is fixed, and in heating process, this tool continues to hold this base plate for packaging.
The another aspect of this exposure is about a kind of chip bonding device, and it comprises a tool, a heating furnace (HeatingOven) and a pressure source.This tool holds a base plate for packaging via pull of vacuum, and wherein one first semiconductor chip is positioned on this base plate for packaging.This heating furnace is in order to accommodating and heat this base plate for packaging, this first semiconductor chip and this tool, and wherein in heating process, this tool continues to hold this base plate for packaging.This pressure-source communication to this heating furnace, in order to provide a normal pressure to this heating furnace to stress on a back side of this semiconductor chip in heating process.
Accompanying drawing explanation
Fig. 1 to Figure 10 display is according to the schematic diagram of an embodiment of chip bonding method of the present invention;
Figure 11 to Figure 14 display stacks the schematic diagram of an embodiment of encapsulating structure manufacture method according to the present invention;
Figure 15 display is according to the schematic diagram of another embodiment of chip bonding method of the present invention;
Figure 16 display is according to the schematic diagram of another embodiment of chip bonding method of the present invention;
Figure 17 display is according to the schematic diagram of another embodiment of chip bonding method of the present invention;
Figure 18 display is according to the schematic diagram of another embodiment of chip bonding method of the present invention;
Figure 19 display application is in the schematic perspective view of another embodiment of the tool of chip bonding method of the present invention;
Figure 20 display application is in the schematic perspective view of another embodiment of the tool of chip bonding method of the present invention;
Figure 21 shows the using state schematic diagram of the network of Figure 20, and wherein this base plate for packaging is not also held by this tool;
Figure 22 shows the using state schematic diagram of the network of Figure 20, and wherein this base plate for packaging is held by this tool;
Figure 23 display application is in the schematic perspective view of another embodiment of the tool of chip bonding method of the present invention;
Figure 24 display application is in the schematic perspective view of another embodiment of the tool of chip bonding method of the present invention;
Figure 25 display application is in the schematic perspective view of another embodiment of the tool of chip bonding method of the present invention; And
Figure 26 display application is in the cross-sectional schematic of the heating furnace of another embodiment of chip bonding method of the present invention.
Embodiment
Referring to figs. 1 to Figure 10, show the schematic diagram of the embodiment according to chip bonding method of the present invention.With reference to figure 1, provide base plate for packaging 1 and one first semiconductor chip 2.This base plate for packaging 1 has first surface 11 and a second surface 12.This first semiconductor chip 2 has an active surface 211 and several projection 28, and these projections 28 are positioned at this active surface 211.In the present embodiment, this first semiconductor chip 2 comprises chip body 21, redistribution layer (Redistribution) 22, passivation layer (Passivation Layer) 23, several conductive through hole (ConductiveVia) 24, several lining (Liner) 25, surface-treated layer 26, several weld pad 27 and several projection 28.
In the present embodiment, this first semiconductor chip 2 is an active chip, and this chip body 21 has this active surface 211 and a back side 212.But in other embodiments, this first semiconductor chip 2 can be an intermediate plate (Interposer).These conductive through holes 24 run through this chip body 21, and protrude from this back side 212.These linings 25 surround these conductive through holes 24.This passivation layer 23 is positioned at this back side 212, and its material is high molecular polymer, such as: benzocyclobutene (Benzocyclobutene, BCB) or pi (Polyimide, PI); Or inorganic passivation layer, such as: silicon dioxide.This redistribution layer 22 is positioned at this active surface 211.These weld pads 27 are positioned in this redistribution layer 22, and these projections 28 are positioned on these weld pads 27.This surface-treated layer 26 is positioned at the jag of these conductive poles 24.
This base plate for packaging 1 is placed on a platform 31, and this first semiconductor chip 2 is selected by a suction nozzle 32.In the present embodiment, a scaling powder shower nozzle 34 is utilized to apply the first surface 11 of a scaling powder 33 to this base plate for packaging 1.Then, this first semiconductor chip 2 is placed on this base plate for packaging 1, and wherein these projections 28 of this first semiconductor chip 2 are positioned at this scaling powder 33 to contact the first surface 11 of this base plate for packaging 1.
With reference to figure 2, this base plate for packaging 1 and this first semiconductor chip 2 are placed on a bracing or strutting arrangement (Holder), and wherein this bracing or strutting arrangement holds the second surface 12 of this base plate for packaging 1 via pull of vacuum.In the present embodiment, this bracing or strutting arrangement is a tool (Jig) 4.
With reference to figure 3, display application is in the schematic perspective view of an embodiment of the tool of chip bonding method of the present invention.This tool 4 has first surface 41, second surface 42, several groove 43, passage (not shown), several vacuum hole 44, several alignment pin 45 and several magnetic area 47.These grooves 43 are positioned at the first surface 41 of this tool 4 and the position of this base plate for packaging 1 corresponding.In the present embodiment, the pattern of these grooves 43 is made up of several patterns unit, and each pattern unit has two grooves 43, and these grooves 43 are by the crisscross overlooking sight.This passage is positioned at the inside of this tool 4, and has these vacuum holes 44 on the first surface 41 and these grooves 43 of this tool 4.That is this channel connection is to the first surface 41 of this tool 4 and these grooves 43.Moreover this passage utilizes a connecting pipe 46 to be communicated with a vacuum source (not shown), to produce this pull of vacuum.
With reference to figure 4, display application is in the schematic perspective view of an embodiment of the overlay of chip bonding method of the present invention.This overlay 35 in order to stress on this base plate for packaging 1 after this tool 4 holds this base plate for packaging 1.In the present embodiment, the material of this tool 4 is metal (such as stainless steel) or porous ceramics.The material of this overlay 35 is metal, and this overlay 35 attract by these magnetic area 47 of this tool 4, to increase the engaging force between this tool 4 and this base plate for packaging 1.It should be noted that this overlay 35 has several location hole 351 and several flank 352, wherein these location holes 351 these alignment pins 45 corresponding, and the region that surrounds of these flanks 352 is to being positioned at the region of this base plate for packaging 1 by the first semiconductor chip 2.That is these flanks 352 can't touch this first semiconductor chip 2.
With reference to figure 5, carry out first time reflow (Reflow) technique.This, reflow process comprised one first heating process and one first cooling procedure first time.In this first heating process, this base plate for packaging 1, this first semiconductor chip 2 and this tool 4, through a heating furnace (Heating Oven) 5 (Fig. 6), make them together by heat energy 51 (Fig. 6) heating in this heating furnace 5 (Fig. 6).It should be noted that in this first heating process, this tool 4 continues to hold this base plate for packaging 1.In the present embodiment, this heat energy 51 is from the top of this tool 4 and below; In other embodiments, this heat energy 51 can only from above or below this tool 4.
With reference to figure 6, display application is in the cross-sectional schematic of an embodiment of the heating furnace of chip bonding method of the present invention.This heating furnace 5 comprises several heater (Heater) 52 and a conveying device 53.These heaters 52 are in order to produce heat energy 51 (Fig. 5) to heat this base plate for packaging 1, this first semiconductor chip 2 and this tool 4.In the present embodiment, the position of these heaters 52 is fixed, and this conveying device 53 is a conveyer belt (Conveyer Belt).The second surface 42 of this tool 4 support by this conveyer belt, this tool 4 level is put, and in this first heating process, this tool 4 is carried by this conveying device 53 and through these heaters 52.In the present embodiment, these heaters 52 are positioned at above this first semiconductor chip 2 and below this tool 4, and the temperature of these heaters 52 is differing from each other.
After this first heating process, carry out this first cooling procedure.In this first cooling procedure, this tool 4 still continues to hold this base plate for packaging 1.In the present embodiment, because this tool 4 continues to hold this base plate for packaging 1 in reflow process, the distortion of this base plate for packaging 1 in reflow process is restricted, and this first semiconductor chip 2 can freely be out of shape.
With reference to figure 7, after this for the first time reflow process, discharge this base plate for packaging 1 from this tool 4, and this base plate for packaging 1 is placed on a platform 31a.This platform 31a and this platform 31 identical or different.Then, a scaling powder scavenge unit 36 is utilized to remove this scaling powder 33.
With reference to figure 8, a primer spray equipment 38 is utilized to apply one first primer 37 to the gap between the active surface 211 of this first semiconductor chip 2 and the first surface 11 of this base plate for packaging 1, to protect the connection between this first semiconductor chip 2 and this base plate for packaging 1.
With reference to figure 9, solidify this first primer 37.In the present embodiment, one second heating process is carried out.This base plate for packaging 1 and this first semiconductor chip 2 are placed on this tool 4 again.As mentioned above, this tool 4 holds the second surface 12 of this base plate for packaging 1 via pull of vacuum.Then, heat this base plate for packaging 1 and this first semiconductor chip 2 simultaneously, and solidify this first primer 37.It should be noted that in this second heating process, this tool 4 continues to hold this base plate for packaging 1.But in other embodiments, primer spraying coating process can carry out after this base plate for packaging 1 and this first semiconductor chip 2 are placed in this tool 4.Then this second heating process is just carried out.In the present embodiment, after this second heating process, carry out one second cooling procedure, to reduce the temperature of the first primer 37 after this base plate for packaging 1, this first semiconductor chip 2 and this solidification.
With reference to Figure 10, discharge this base plate for packaging 1 from this tool 4, to complete this chip bonding technique.
With reference to figures 11 to Figure 14, show the schematic diagram of the embodiment stacking encapsulating structure manufacture method according to the present invention.With reference to Figure 11, provide one first semiconductor chip 2, base plate for packaging 1 and one second semiconductor chip 2a.This first semiconductor chip 2 is engaged to this base plate for packaging 1.In the present embodiment, this first semiconductor chip 2 utilizes the method shown in Fig. 1 to Figure 10 to be engaged to this base plate for packaging 1.In the present embodiment, this base plate for packaging 1 is placed on a platform 31 together with this first semiconductor chip 2, and this second semiconductor chip 2a is selected by a suction nozzle 32.In the present embodiment, a scaling powder shower nozzle 34 is utilized to apply the back side 212 of a scaling powder 33 to this first semiconductor chip 2.Then, this second semiconductor chip 2a is placed on this first semiconductor chip 2 to be electrically connected this first semiconductor chip 2.It should be noted that this second semiconductor chip 2a can be identical or not identical with this first semiconductor chip 2.This first semiconductor chip 2 has an active surface 211 and several projection 28, and these projections 28 are positioned at this active surface 211.In the present embodiment, this second semiconductor chip 2a is an active chip, and has an active surface 211a, several weld pad 27a and several projection 28a, and these projections 28a is positioned at this active surface 211a.
With reference to Figure 12, this base plate for packaging 1, this first semiconductor chip 2 and this second semiconductor chip 2a are placed on a bracing or strutting arrangement (Holder), and wherein this bracing or strutting arrangement holds the second surface 12 of this base plate for packaging 1 via pull of vacuum.Preferably, this bracing or strutting arrangement is a tool (Jig) 4.Then, carry out second time reflow (Reflow) technique, this base plate for packaging 1, this first semiconductor chip 2, this second semiconductor chip 2a and this tool 4, through a heating furnace (Heating Oven) 5 (Fig. 6), make them together by heat energy 51 (Fig. 6) heating in this heating furnace 5 (Fig. 6).It should be noted that in this second time reflow process, this tool 4 continues to hold this base plate for packaging 1.
With reference to Figure 13, discharge this base plate for packaging 1 from this tool 4, and this base plate for packaging 1 is placed on a platform 31a.This platform 31a and this platform 31 identical or different.Then, a scaling powder scavenge unit 36 is utilized to remove this scaling powder 33.
With reference to Figure 14, utilize the gap that a primer spray equipment 38 applies between one second primer 37a to this second semiconductor chip 2a and this first semiconductor chip 2, to protect the connection between this second semiconductor chip 2a and this first semiconductor chip 2.Then, this second primer 37a is solidified.In this primer solidification process, this second semiconductor chip 2a, this first semiconductor chip 2 and this base plate for packaging 1 are placed on this tool 4 again.As mentioned above, this tool 4 holds the second surface 12 of this base plate for packaging 1 via pull of vacuum.After this primer solidification process, discharge this base plate for packaging 1 from this tool 4, stack encapsulating structure with obtained one.
With reference to Figure 15, show the schematic diagram of another embodiment according to chip bonding method of the present invention.The method of the present embodiment is roughly the same with the method shown in Fig. 1 to Figure 10.The method of the present embodiment and the different of the method shown in above-mentioned Fig. 1 to Figure 10 are in structure in this heating furnace 5a and the mode of movement of this tool 4 in this heating furnace 5a.
With reference to Figure 15, display application is in the cross-sectional schematic of the heating furnace 5a of another embodiment of chip bonding method of the present invention.This heating furnace 5a comprises several heater (Heater) 52 and a conveying device (not shown).This conveying device is a pipeline (Conveyer Line).The position of these heaters 52 is fixed and around this pipeline, and these heater 52 temperature are differing from each other.This tool 4 is placed on this pipeline, in course of conveying, this first semiconductor chip 2 by sequentially through different temperature blocks to complete reflow process.
With reference to Figure 16, show the schematic diagram of another embodiment according to chip bonding method of the present invention.The method of the present embodiment is roughly the same with the method shown in Fig. 1 to Figure 10.The method of the present embodiment and the different of the method shown in above-mentioned Fig. 1 to Figure 10 are in the structure of structure in this heating furnace 5b and this bracing or strutting arrangement.
With reference to Figure 16, display application is in the cross-sectional schematic of the heating furnace of another embodiment of chip bonding method of the present invention.This heating furnace 5b comprises several bracing or strutting arrangement.In the present embodiment, this bracing or strutting arrangement is a heating station (Heating Stage) 4a.This heating station 4a has several vacuum hole 48, is communicated to a vacuum source.Therefore, this heating station 4a can hold the second surface 12 of this base plate for packaging 1 via pull of vacuum.In addition, this heating station 4a itself can set different temperatures to heat this base plate for packaging 1 and this first semiconductor chip 2, and has the high rate of heat addition and high cooldown rate.In reflow process, this heating station 4a arranged perpendicular.After reflow process, this base plate for packaging 1 and this first semiconductor chip 2 are selected from this heating station 4a.In the present embodiment, the heater 52 of Fig. 6 and conveying device 53 can be omitted.
With reference to Figure 17, show the schematic diagram of another embodiment according to chip bonding method of the present invention.The method of the present embodiment is roughly the same with the method shown in Fig. 1 to Figure 10.The method of the present embodiment and the different of the method shown in above-mentioned Fig. 1 to Figure 10 are in the structure of structure in this heating furnace 5c and this bracing or strutting arrangement.
With reference to Figure 17, display application is in the cross-sectional schematic of the heating furnace of another embodiment of chip bonding method of the present invention.This heating furnace 5c comprises several bracing or strutting arrangement.In the present embodiment, this bracing or strutting arrangement is a heating station 4b.This heating station 4b has several vacuum hole 48, is communicated to a vacuum source.Therefore, this heating station 4b can hold the second surface 12 of this base plate for packaging 1 via pull of vacuum.The position of these heating stations 4b is fixing, and each heating station 4b sets a fixed temperature.That is the temperature of these heating stations 4b is differing from each other.In reflow process, these base plate for packaging 1 are placed in heating one scheduled time on these this heating stations 4b.Then, these base plate for packaging 1 all move to next heating station 4b and heat a scheduled time again.Therefore, the temperature of this base plate for packaging 1 can improve gradually or decline gradually.In the present embodiment, the heater 52 of Fig. 6 and conveying device 53 can be omitted.
With reference to Figure 18, show the schematic diagram of another embodiment according to chip bonding method of the present invention.The method of the present embodiment is roughly the same with the method shown in Fig. 1 to Figure 10.The method of the present embodiment and the different of the method shown in above-mentioned Fig. 1 to Figure 10 are in the structure of structure in this heating furnace 5d and this bracing or strutting arrangement.
With reference to Figure 18, display application is in the cross-sectional schematic of the heating furnace of another embodiment of chip bonding method of the present invention.This heating furnace 5d comprises infrared heater 54, cooling system 55 and a bracing or strutting arrangement.In the present embodiment, this bracing or strutting arrangement is a brace table 4c.This brace table 4c has several vacuum hole 48, is communicated to a vacuum source.Therefore, this brace table 4c can hold the second surface 12 of this base plate for packaging 1 via pull of vacuum.This infrared heater 54 is positioned at above this brace table 4c, in order to produce heat energy 51.This cooling system 55 is connected to this brace table 4c, in order to cool this brace table 4c.In reflow process, this base plate for packaging 1 is placed on this brace table 4c, and is heated by this infrared heater 54.Then, after reflow process, this base plate for packaging 1 is cooled by this cooling system 55.In the present embodiment, the heater 52 of Fig. 6 and conveying device 53 can be omitted.
With reference to Figure 19, display application is in the schematic perspective view of another embodiment of the tool of chip bonding method of the present invention.In the present embodiment, this tool 4d is porous material, such as: pottery.In addition, this tool 4d has an encapsulant 56 and several setting element 45a.Sealing material 56 is arranged in five surfaces of (sealing) this tool 4d except this first surface 41.These setting elements 45a is positioned at four corners of this tool 4d, to locate this base plate for packaging 1.
With reference to Figure 20, display application is in the schematic perspective view of another embodiment of the tool of chip bonding method of the present invention.In the present embodiment, this tool 4 has a network 6, and it is positioned at the first surface 41 of this tool 4.Preferably, this network 6 can be pi (PI) adhesive tape, but is not limited to this, and directly attaches to this first surface 41.It should be noted that this network 6 does not cover these vacuum holes 44 and groove 43.
With reference to Figure 21, the using state schematic diagram of the network of display Figure 20, wherein this base plate for packaging 1 is not also held by this tool 4.As shown in the figure, this base plate for packaging 1 has convex warpage (Convex Warpage).
With reference to Figure 22, the using state schematic diagram of the network of display Figure 20, wherein this base plate for packaging 1 is held by this tool 4.As shown in the figure, after this base plate for packaging 1 is held by this tool 4, its warpage becomes concavity warpage (Concave Warpage).
With reference to Figure 23, display application is in the schematic perspective view of another embodiment of the tool of chip bonding method of the present invention.The tool 4 shown in tool 4e and Fig. 3 of the present embodiment is roughly the same.The different patterns be in these grooves 43 of the tool 4 shown in tool 4e and Fig. 3 of the present embodiment.In the present embodiment, the pattern of these grooves 43 is made up of several patterns unit, and each pattern unit has four grooves 43, and these grooves 43 intersect at a bit.
With reference to Figure 24, display application is in the schematic perspective view of another embodiment of the tool of chip bonding method of the present invention.The tool 4e shown in tool 4f and Figure 23 of the present embodiment is roughly the same.The different patterns be in these grooves 43 of the tool 4e shown in tool 4f and Figure 23 of the present embodiment.In the present embodiment, these grooves 43 more comprise several connection groove 431, and each connects groove 431 and connects adjacent trenches 43 corresponding in adjacent patterns unit.
With reference to Figure 25, display application is in the schematic perspective view of another embodiment of the tool of chip bonding method of the present invention.The tool 4 shown in tool 4g and Fig. 3 of the present embodiment is roughly the same.Not existing together of the tool 4 shown in tool 4g and Fig. 3 of the present embodiment is as described below.In the present embodiment, this tool 4g does not have these grooves 43, and only has these vacuum holes 44.The pattern of these vacuum holes 44 is made up of several pattern unit be spaced, and each pattern unit has the vacuum hole 44 of several arrayed.
With reference to Figure 26, show the schematic diagram of another embodiment according to chip bonding method of the present invention.The method of the present embodiment is roughly the same with the method shown in Fig. 1 to Figure 10.The method of the present embodiment and the different structures be in this heating furnace 5e of the method shown in above-mentioned Fig. 1 to Figure 10.
With reference to Figure 26, display application is in the cross-sectional schematic of the heating furnace of another embodiment of chip bonding method of the present invention.This heating furnace 5e comprises a support 60, at least one bracing or strutting arrangement, vacuum source 62 and a pressure source 63.This support 60 is positioned at this heating furnace 5e.In the present embodiment, this bracing or strutting arrangement is a tool 4 (Fig. 3), and is positioned at this support 60.This tool 4 be communicated with this vacuum source 62 communicating pipe 46.This pressure source 63 is communicated to this heating furnace 5e, in order to provide a normal pressure 64 to this heating furnace 5e.In reflow process, this tool 4 can hold the second surface 12 of this base plate for packaging 1 via the pull of vacuum from this vacuum source 62, and from the normal pressure 64 of this pressure source 63 in order to stress on the back side 212 of the chip body 21 of this semiconductor chip 2.Therefore, the warpage of this base plate for packaging 1 can be reduced.After reflow process, this base plate for packaging 1 and this first semiconductor chip 2 are selected from this tool 4.In the present embodiment, the heater 52 of Fig. 6 and conveying device 53 can be omitted.
Only above-described embodiment is only and principle of the present invention and effect thereof is described, and is not used to limit the present invention.Therefore, the personage practised in this technology modifies to above-described embodiment and changes still de-spirit of the present invention.Interest field of the present invention should listed by claims.
Claims (11)
1. a chip bonding method, comprises the following steps:
A () provides a base plate for packaging and one first semiconductor chip, this base plate for packaging has a first surface and a second surface, and this first semiconductor chip has an active surface and several projection, and described projection is positioned on this active surface;
B this first semiconductor chip is placed on this base plate for packaging by (), wherein the first surface of described this base plate for packaging of bump contact of this first semiconductor chip;
C this base plate for packaging and this first semiconductor chip are placed on a bracing or strutting arrangement by (), wherein this bracing or strutting arrangement holds the second surface of this base plate for packaging via pull of vacuum; And
D this base plate for packaging of () reflow, this first semiconductor chip and this bracing or strutting arrangement, wherein in reflow process, this bracing or strutting arrangement continues to hold this base plate for packaging.
2. chip bonding method as claimed in claim 1, wherein more comprises after this step (d):
E () applies one first primer to the gap between the active surface of this first semiconductor chip and the first surface of this base plate for packaging;
F this base plate for packaging and this first semiconductor chip are placed on this bracing or strutting arrangement by (), wherein this bracing or strutting arrangement holds the second surface of this base plate for packaging via pull of vacuum;
G () heats this base plate for packaging and this first semiconductor chip to solidify this first primer simultaneously, wherein in heating process, this bracing or strutting arrangement continues to hold this base plate for packaging; And
H () discharges this base plate for packaging from this bracing or strutting arrangement.
3. chip bonding method as claimed in claim 1, wherein this bracing or strutting arrangement is a tool, and in this step (d), this base plate for packaging, this first semiconductor chip and this tool are heated by several heater simultaneously.
4. chip bonding method as claimed in claim 1, wherein this bracing or strutting arrangement is a heating station, and in this step (d), this base plate for packaging and this first semiconductor chip are heated by this heating station.
5. chip bonding method as claimed in claim 1, wherein more comprises after this step (d):
There is provided one second semiconductor chip, this second semiconductor chip has an active surface and several projection, and described projection is positioned on this active surface;
This second semiconductor chip is placed on this first semiconductor chip; And
This base plate for packaging of reflow, this first semiconductor chip, this second semiconductor chip and this bracing or strutting arrangement, wherein in reflow process, this bracing or strutting arrangement continues to hold this base plate for packaging.
6. a chip bonding device, comprising:
One tool, it holds a base plate for packaging via pull of vacuum, and wherein one first semiconductor chip is positioned on this base plate for packaging; And
Several heater and cooler, in order to heat and to cool this base plate for packaging, this first semiconductor chip and this tool simultaneously, the position of wherein said heater and cooler is fixed, and in reflow process, this tool continues to hold this base plate for packaging.
7. chip bonding device as claimed in claim 6, wherein this tool has a first surface, a second surface, several groove and a passage, described groove is positioned at the first surface of this tool, and this passage is positioned at this tool inside and is communicated with described groove and a vacuum source, to produce this pull of vacuum.
8. chip bonding device as claimed in claim 6, more comprises an overlay, in order to stress on this base plate for packaging after this tool holds this base plate for packaging.
9. a chip bonding device, comprising:
One tool, it holds a base plate for packaging via pull of vacuum, and wherein one first semiconductor chip is positioned on this base plate for packaging;
One heating furnace, in order to accommodating and heat this base plate for packaging, this first semiconductor chip and this tool simultaneously, wherein in heating process, this tool continues to hold this base plate for packaging;
One cooling system, in order to cool this base plate for packaging, this first semiconductor chip and this tool simultaneously, wherein in cooling procedure, this tool continues to hold this base plate for packaging; And
One pressure source, is communicated to this heating furnace, in order to provide a normal pressure to this heating furnace to stress on a back side of this semiconductor chip in heating process.
10. chip bonding device as claimed in claim 9, wherein this tool is porous material, and an encapsulant is formed on five surfaces of this tool.
11. chip bonding devices as claimed in claim 9, wherein this tool has a network, be positioned at a first surface of this tool, and this base plate for packaging is positioned in this network.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201161531790P | 2011-09-07 | 2011-09-07 | |
| US61/531,790 | 2011-09-07 |
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| CN102842517A CN102842517A (en) | 2012-12-26 |
| CN102842517B true CN102842517B (en) | 2015-10-28 |
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| CN201210312484.4A Active CN102842517B (en) | 2011-09-07 | 2012-08-29 | Chip bonding method and device |
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| JP6518461B2 (en) * | 2015-03-03 | 2019-05-22 | 東レエンジニアリング株式会社 | Mounting device and mounting method |
| CN111653494B (en) * | 2020-06-16 | 2021-10-15 | 中国电子科技集团公司第二十四研究所 | Non-contact heating flip-chip welding process method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6189208B1 (en) * | 1998-09-11 | 2001-02-20 | Polymer Flip Chip Corp. | Flip chip mounting technique |
| CN101789379A (en) * | 2009-01-22 | 2010-07-28 | 日月光半导体制造股份有限公司 | Manufacturing method for package structure |
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