CN102841360B - Weak signal quick capture method on basis of part correlation - Google Patents
Weak signal quick capture method on basis of part correlation Download PDFInfo
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Abstract
The invention provides a weak signal quick capture method on basis of part correlation, which can meet the requirement of long coherent accumulation of a weak signal, and meanwhile, is suitable for the effect of wide-range Doppler change. The method comprises the following steps: generating 8-path data sequences, obtaining a duplication code, and allowing each path of the data sequence to be subjected to exclusive or operation together with the duplication code so as to obtain 8-path data auxiliary duplication codes; and allowing in-phase base band data and orthogonal base band data to be subjected to coherent accumulation operation through the auxiliary duplication codes and the duplication code, allowing the accumulation result of each path of data sequence to be subjected to FFT (Fast Fourier Transform), and then calculating the quadratic sums of the transformation results so as to judge whether the capture succeeds or not according to the maximal quadratic sum. According to the invention, the 8-path data sequences with different phase positions are adopted, a multi-path parallel coherent processing is adopted according to the processing results of the data sequences, and the coherent integration time in the signal capture process is prolonged as far as possible to an extent that the coherent integration can span several modulation data widths so as to improve the signal-to-noise ratio.
Description
Technical field
The present invention relates to a kind of feeble signal quick capturing method relevant based on part, belong to the telemetry communication technical field.
Background technology
In actual spread spectrum communication system engineering, the direct sequence spread spectrum mode is that what to use at present is at most, also most typical a kind of, and typical example has: the Galileo in the GPS of the U.S., Muscovite GLONASS, Europe and the Compass of China.
The fast Capture Technique of signal is one of gordian technique of receiver baseband signal processing, because transmitting, transmitting terminal comprises carrier wave, pseudo-code and required data, for the Obtaining Accurate desired data, fast Capture Technique eliminates carrier wave and the pseudo-code received in signal.
The principle of catching of signal is: on satellite, the observing and controlling receiver produces local pseudo-code sequence, then must move the phase place of this local code, until occur relevant to the pseudo-code of receiving spread frequency signal.Because, while only having the local copy codes that produces when receiver with the coupling of the pseudo-code phase on spread-spectrum signal, maximum being correlated with now arranged.Receiver also must detect in the carrier frequency territory carrier frequency of upward signal (ground-launched signal) simultaneously, the method detected is produce the local replica carrier frequency and consider Doppler effect, utilize the similarity of correlation detection local replica carrier wave and up-link carrier, realize carrier synchronization.Therefore, receiver is a two dimension (pseudo-code and carrier frequency or be called the time and frequency) signal replication process to the acquisition procedure of signal.
Except the uncertainty of code phase and carrier wave frequency deviation, modulating data can change chip polarity, can affect the coherent length of capture systems related operation, and modulation data rate is higher, and coherent length is less, and then causes the spread spectrum system processing gain to descend.
In the base band signal process of spread spectrum communication system, acquisition algorithm is also more complicated, miscellaneous.From the search strategy aspect, mainly be divided into: linear search, parallel frequency search and parallel code phase search.
Linear search algorithm is the most basic a kind of signal search catching method, and it utilizes digital correlator Doppler shift and this bidimensional of code phase to specified satellite-signal in time domain to carry out the scan-type search.The search order of two-dimensional linear code acquisition algorithm sets out for frequency band between at first therefrom, and by code phase, ascending order has been searched for all unit on this frequency band successively, then continues all unit on the next frequency band of search.The shortcoming of this kind of method is that acquisition procedure is very consuming time in pseudo-code and the larger situation of carrier doppler uncertainty.
The parallel frequency search algorithm utilizes Fourier transform to realize the parallel search to frequency, thereby accelerates acquisition speed.The parallel frequency search algorithm does not need the signal frequency one dimension is carried out to the scan-type search, the search of each code phase is carried out to a FFT and calculate, and can complete the search in large Doppler's variation range, and frequency search resolution is higher.But realize that modulation data rate is higher, the parallel frequency search algorithm in the large situation of feeble signal, Doppler's variation range is the work of a rich challenge and difficulty.
Parallel code phase search can complete code phase by Fourier transform is disposable, this correlation technique based on fft algorithm is equivalent to parallel correlator, has farthest reduced the search unit number, therefore has the shortest capture time.But when each frequency band of search, need to complete twice Fourier transform and a Fourier inversion, required calculated amount is larger.Simultaneously, the impact that parallel code phase search acquisition algorithm is subject to the saltus step of modulating data bit, therefore, realize that modulation data rate is higher, and there is certain difficulty in the parallel code phase search algorithm in the feeble signal situation.
Be directed to relay satellite, its modulation signal form is PCM-DSSS-BPSK, and the requirement of modulation data rate, carrier-to-noise ratio, Doppler shift scope three aspects: is respectively:
1) the known modulation data rate is 2000bps, sends " 101010 ... " idle sequence when there is no information, to keep synchronous;
2) capture ability that requirement has feeble signal, acquisition sensitivity is better than carrier-to-noise ratio 48dB/Hz;
3) require the Doppler shift acquisition scope for-90kHz ~+90kHz.
Above several the requirements of relaying observing and controlling are compared with the GPS civil signal, relaying observing and controlling modulation data rate is 40 times of gps navigation message speed, the Doppler shift acquisition scope of relaying TT&C requirement is 18 times of GPS receiver, the carrier-to-noise ratio of relaying TT&C requirement and gps satellite near zenith during position intensity 46dBHz compare and belong to quite equally feeble signal.
Above several requirements condition each other, and the problem caused is: the first, when the signal received when receiving end is feeble signal, catch need to be long as far as possible the coherent integration time, but modulation data rate is higher, limited again the coherent integration time.The second, when the Doppler's variation range between receiving end and transmitting terminal is large, due to the variation of the pseudo-bit rate that exists Doppler effect to cause, therefore affect catching of pseudo-code phase.Therefore overcome the impact of modulating data upset, and consider that Doppler affects in situation, reach optimum capture time performance and meet the sensitivity requirement, be the current problem solved that needs.
Summary of the invention
The purpose of this invention is to provide a kind of feeble signal quick capturing method relevant based on part, the method can meet the coherent accumulation to the long period of feeble signal, the impact that simultaneously applicable Doppler on a large scale changes.
Realize that technical scheme of the present invention is as follows:
A kind of feeble signal quick capturing method relevant based on part, concrete step is as follows:
Step 1, generate 8 circuit-switched data sequences, the bit period of described 8 circuit-switched data sequences is 0.5ms, since the 1st circuit-switched data sequence to the 8 circuit-switched data sequences, its start-phase according to the step-length of 22.5 ° for increasing progressively;
Step 2, utilize the pseudo-code digital controlled oscillator to produce the pseudo-code clock of 3.069MHz, pseudo-code generator generates replica code under the driving of pseudo-code clock, and the speed of the replica code generated is 3.069Mcps;
Step 3, described 8 circuit-switched data sequences are carried out to XOR with replica code respectively, obtain 8 circuit-switched data auxiliary duplication codes;
Step 4, the method for utilizing the digital quadrature down coversion are processed the intermediate-freuqncy signal of input, produce sinusoidal, cosine two paths of signals, and by this just, cosine two paths of signals and described intermediate-freuqncy signal multiply each other, and obtains respectively homophase, quadrature two-way base band data;
Step 5, make described 8 circuit-switched data auxiliary duplication codes and described replica code do relevant accumulation computing to homophase, quadrature two-way base band data respectively, obtain 18 tunnel integral operation results, it is 2ms that integration period wherein is set, in the time range of 2ms, number of samples on signal is divided into to 512 parts, each increment is counted and accumulated, obtain 512 sample value;
Step 6, the accumulation results of the homophase of same data auxiliary duplication code correspondence, quadrature two-way base band data is merged, obtain 8 road accumulation results, to replica code, corresponding homophase, the accumulation results of quadrature two-way base band data are merged, obtain 1 road accumulation result, altogether obtain 9 road accumulation results;
Step 7, for each road accumulation result, to its rear end zero padding to 2048 point, then the real part converted its homophase accumulated value as FFT, the imaginary part of conversion using its quadrature accumulated value as FFT, 9 road signals are carried out respectively to the FFT conversion, then calculate the quadratic sum of FFT transformation results, obtain altogether 9 * 2048=18432 quadratic sum;
Step 8, relatively 9 * 2048=18432 the quadratic sum of passing through, select maximal value and default thresholding wherein to compare, when maximal value surpasses default thresholding, think acquisition success, think that current replica code and input intermediate-freuqncy signal pseudo code correlation sexual satisfaction catch requirement, and the FFT position that the peak value of 18432 quadratic sums is corresponding has represented that carrier doppler catches result, method ends; If maximal value is less than default thresholding, next coherent integration period is come, and controls 0.5 chip of pseudo-code generator slip and generates replica code, returns to step 3.
Beneficial effect
The present invention arranges the different data sequence of 8 tunnel phase place, adopt the multidiameter delay relevant treatment according to the result to the data sequence, lengthen as much as possible the coherent integration time in the signal capture process, make coherent integration cross over several modulating data width to improve signal to noise ratio (S/N ratio).
The accompanying drawing explanation
The process flow diagram that Fig. 1 is feeble signal quick capturing method of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is further elaborated.
The hardware platform the present invention is based on has A/D transducer, FPGA etc.Fpga chip is selected the product XC2V3000 of U.S. Xilinx company, and its dominant frequency reaches as high as 300MHz, and FPGA (Field Programmable Gate Array) can reach 3,000,000.The A/D transducer is selected the product A D10200 of U.S. Analogic Corp., and its highest sample frequency is 105MHz, and data resolution is 12.Be converted to the sample value data after the bandpass sampling of intermediate-freuqncy signal by A/D transducer (chip), then the catching of settling signal in FPGA.
FPGA adopts the work clock of 38MHz, and 38MHz is also used as the change over clock of A/D simultaneously.Analog if signal, through analog to digital conversion, is exported the sample value intermediate-freuqncy signal of per second 38M, the input through 12 interfaces as FPGA.
As shown in Figure 1, the present invention is based on the feeble signal quick capturing method that part is relevant, concrete steps are as follows:
Step 1, generate 8 circuit-switched data sequences, the bit period of described 8 circuit-switched data sequences is that 0.5ms(0.5ms equals 2000bps according to signaled bit rate to determine), since the 1st circuit-switched data sequence to the 8 circuit-switched data sequences, its start-phase increases progressively according to the step-length of 22.5 °, can obtain the data sequence of the different initial phases in 8 tunnels.
Step 2, produced the pseudo-code clock of 3.069MHz by the pseudo-code digital controlled oscillator, pseudo-code generator generates replica code under the driving of pseudo-code clock, and the speed of the replica code generated is 3.069Mcps.
Step 3, described 8 circuit-switched data sequences are carried out to XOR with replica code respectively, obtain 8 circuit-switched data auxiliary duplication codes.
Step 4, the method for utilizing the digital quadrature down coversion are processed the intermediate-freuqncy signal of input, produce sinusoidal, cosine two paths of signals, and by this just, cosine two paths of signals and described intermediate-freuqncy signal multiply each other, and obtains respectively homophase, quadrature two-way base band data.
Step 5, utilize 18 parallel correlators in 8 circuit-switched data auxiliary duplication codes and step 2, produce 1 road replica code totally 9 road replica codes do relevant accumulation computing to homophase, quadrature two-way base band data respectively, it is 2ms that integration period wherein is set, in the time range of 2ms, number of samples on signal is divided into to 512 parts, each increment is counted and accumulated, obtain 512 sample value, and then obtain 18 tunnel integral operation results.
Step 6, the accumulation results of the homophase of same data auxiliary duplication code correspondence, quadrature two-way base band data is merged, obtain 8 road accumulation results, to replica code, corresponding homophase, the accumulation results of quadrature two-way base band data are merged, obtain 1 road accumulation result, altogether obtain 9 road accumulation results; This 9 road accumulation result is kept in the inside dual port RAM of FPGA simultaneously.Concrete is stored as, and two groups of dual port RAMs (every group of dual port RAM unit that comprises that 9 degree of depth are 512) are set in FPGA, two groups of dual port RAMs is used the read-write mode operation of ping-pong operation simultaneously.
Step 7, read successively storage De Ge road accumulation result in it from the dual port RAM of FPGA inside, for each road accumulation result, to its rear end zero padding to 2048 point, then the real part converted its homophase accumulated value as FFT, the imaginary part of conversion using its quadrature accumulated value as FFT, 9 road signals are completed respectively to the FFT transformation calculations, the FFT computing is used the IP kernel of Xilinx company to realize, the real part that the exportable FFT computing of this IP kernel obtains, imaginary part and exponential part, then calculate the quadratic sum of FFT transformation results, obtain altogether 9 * 2048=18432 quadratic sum, quadratic sum obtained above is delivered to step 8 carries out peak value and detects to realize catching signal.
Step 8, catch processing: by 9 * 2048=18432 quadratic sum relatively, selection maximal value and default thresholding wherein compares, this process implementation first guess the inspection in rear inspection.Utilization occurs that a road of correlation must be the most accurate that the bit upturned position is guessed, weakens the fact on a minimum road to catching signal to noise ratio (S/N ratio).When maximal value surpasses default thresholding, think acquisition success, think that current replica code catches requirement with input intermediate-freuqncy signal pseudo code correlation sexual satisfaction, and FFT position corresponding to the peak value of 18432 quadratic sums represented that carrier doppler catches result; If maximal value is less than default thresholding, next coherent integration period is come, and controls 0.5 chip of pseudo-code generator slip and generates replica code, then returns to step 3.
In a chip, relevant peaks is all arranged by the pseudo code correlation characteristic is known, the slip sum that therefore the each maximum step-length of sliding of local chip and maximum Doppler cause should be not more than 1chip.Therefore, by the step-length of appropriate design chip search, can make code phase search in large Doppler spread can obtain as early as possible correlation peak.
It is to realize the time of composing initial phase by controlling the chip generation unit that the present invention controls 0.5 chip generation control code of chip maker slip, for example coherent integration period of the present invention is 2ms, use the counter cycle count, when reaching 2ms+t1 constantly, the register of pseudo-code generator is composed as first phase value, the value zero clearing of unison counter.Reach the purpose of controlling the slip number of chips according to the large I of controlling t1.
For example, the carrier doppler of known maximum is ± 90kHz, the carrier frequency point that land station transmits and the ratio of pseudo-bit rate are 684.1, and when coherent integration period is 2ms, the pseudo-code relative sliding that Doppler causes in integration period is ± 90000/684.1 * 2=± 0.263(chip).
Considering that Doppler affects in situation, in order to guarantee acquisition success, each actual amount of sliding meet be not more than 1-0.263=0.737(chip).
Known pseudo-bit rate is 3.069Mcps, and the work clock of system is 38.0MHz, and the step-length of each actual replica code slided should meet that to be not more than 9.125(be 0.737/3.069 * 38.0=9.125) the individual work clock cycle.Meet under this condition, can meet the pseudo code correlation characteristic and guarantee to catch to there is peak value.The fastest capture time performance when equaling 9, the step-length of selecting replica code is arranged.
The known pseudo-code cycle is 1023, and the step-length that replica code slides is selected 9 work clock cycles, when-90kHz, 0Hz ,+tri-kinds of carrier doppler situations of 90kHz under, the actual code phase slided is:
The situation of be directed to-90kHz: 0.726-0.263=0.463
Be directed to the situation of 0Hz: 0.726-0=0.726
Be directed to the situation of 90kHz: 0.726+0.263=0.989
The maximum duration that travels through all 1023 chips is-situation of 90kHz carrier doppler, and now the longest traversal search time equals (1023/0.463) * 0.002=4.4 second
If do not consider the relative sliding that Doppler causes, still use the conventional sliding step of 0.5chip/ time.The longest time traversal search time is (1023/(0.5-0.263)) * 0.002=8.6 second.
Visible, use the longest capture time that has shortened 4.2 seconds of this method.
In sum, these are only preferred embodiment of the present invention, be not intended to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (1)
1. a feeble signal quick capturing method relevant based on part, is characterized in that, concrete step is as follows:
Step 1, generate 8 circuit-switched data sequences, the bit period of described 8 circuit-switched data sequences is 0.5ms, and since the 1st circuit-switched data sequence to the 8 circuit-switched data sequences, its start-phase increases progressively according to the step-length of 22.5 °;
Step 2, utilize the pseudo-code digital controlled oscillator to produce the pseudo-code clock of 3.069MHz, pseudo-code generator generates replica code under the driving of pseudo-code clock, and the speed of the replica code generated is 3.069Mcps;
Step 3, described 8 circuit-switched data sequences are carried out to XOR with replica code respectively, obtain 8 circuit-switched data auxiliary duplication codes;
Step 4, the method for utilizing the digital quadrature down coversion are processed the intermediate-freuqncy signal of input, produce sinusoidal, cosine two paths of signals, and by this just, cosine two paths of signals and described intermediate-freuqncy signal multiply each other, and obtains respectively homophase, quadrature two-way base band data;
Step 5, make described 8 circuit-switched data auxiliary duplication codes and described replica code do relevant accumulation computing to homophase, quadrature two-way base band data respectively, obtain 18 tunnel integral operation results, it is 2ms that integration period wherein is set, in the time range of 2ms, number of samples on signal is divided into to 512 parts, each increment is counted and accumulated, obtain 512 sample value;
Step 6, the accumulation results of the homophase of same data auxiliary duplication code correspondence, quadrature two-way base band data is merged, obtain 8 road accumulation results, to replica code, corresponding homophase, the accumulation results of quadrature two-way base band data are merged, obtain 1 road accumulation result, altogether obtain 9 road accumulation results;
Step 7, for each road accumulation result, to its rear end zero padding to 2048 point, then the real part converted its homophase accumulated value as FFT, the imaginary part of conversion using its quadrature accumulated value as FFT, 9 road signals are carried out respectively to the FFT conversion, then calculate the quadratic sum of FFT transformation results, obtain altogether 9 * 2048=18432 quadratic sum;
Step 8, relatively 9 * 2048=18432 the quadratic sum of passing through, select maximal value and default thresholding wherein to compare, when maximal value surpasses default thresholding, think acquisition success, think that current replica code and input intermediate-freuqncy signal pseudo code correlation sexual satisfaction catch requirement, and the FFT position that the peak value of 18432 quadratic sums is corresponding has represented that carrier doppler catches result, method ends; If maximal value is less than default thresholding, next coherent integration period is come, and controls 0.5 chip of pseudo-code generator slip and generates replica code, returns to step 3.
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| CN103078660B (en) * | 2013-01-06 | 2015-04-22 | 中国电子科技集团公司第十研究所 | Method for reducing capturing time of spreading code in large dynamic range |
| CN103873105B (en) * | 2014-01-27 | 2016-07-06 | 中国电子科技集团公司第十研究所 | High dynamic weak DS/FH hybrid spread spectrum signal acquisition system |
| CN105162493B (en) * | 2015-08-04 | 2017-07-14 | 北京理工大学 | Doppler domain and the two-dimentional catching method of delay domain and device |
| CN106772475B (en) * | 2016-12-23 | 2023-12-12 | 天津七六四通信导航技术有限公司 | Circuit and method for capturing weak GPS navigation signals based on FPGA |
| CN107888230B (en) * | 2017-10-17 | 2021-09-14 | 上海航天电子有限公司 | Multiphase coherent integration acquisition method applied to weak signal environment |
| CN107976696B (en) * | 2017-11-13 | 2019-08-20 | 中国人民解放军国防科技大学 | Method for rapidly capturing high-dynamic weak L1CP signal |
| CN108521388B (en) * | 2018-04-10 | 2019-09-06 | 北京邮电大学 | A kind of frequency capture method based on TC-OFDM, device, electronic equipment and storage medium |
| CN115080498B (en) * | 2022-07-27 | 2022-11-08 | 成都奇芯微电子有限公司 | Signal data storage method and storage chip based on satellite navigation application |
| CN115327582B (en) * | 2022-10-13 | 2023-02-14 | 北京凯芯微科技有限公司 | GNSS signal processing circuit, method and receiver |
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