CN102841359A - Two-dimensional capturing method for carrier pseudo codes of direct sequence spread spectrum signals capable of preventing turnover of messages - Google Patents
Two-dimensional capturing method for carrier pseudo codes of direct sequence spread spectrum signals capable of preventing turnover of messages Download PDFInfo
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Abstract
The invention provides a two-dimensional capturing method for carrier pseudo codes of direct sequence spread spectrum signals capable of preventing turnover of messages. The two-dimensional capturing method is characterized in that turnover of messages can be prevented during the capturing progress of the direct sequence spread spectrum signals. The method comprises the specific steps of: obtaining two paths of in-phase and orthorhombic baseband signals; conducting delayed time processing of one time, two times, three times, ..., (N-1) times to the two paths of in-phase and orthorhombic baseband signals respectively, obtaining 2*N paths of parallel baseband signals; generating duplication codes by a pseudo code generator driven by a pseudo code clock, and conducting coherent accumulation operation to the 2*N paths of baseband signals and the duplication codes respectively by using 2*N parallel correlators; and then conducting double angle procession and FFT (Fast Fourier Transform) to a result of the accumulation operation, getting quadratic sums after the FFT; and selecting the maximum value in the quadratic sums and comparing the maximum value with a preset threshold, so as to conduct capturing.
Description
Technical field
The present invention relates to a kind of direct sequence signal carrier wave pseudo-code two dimension catching method of anti-text upset, belong to communication technical field.
Background technology
In actual spread spectrum communication system engineering, directly expansion mode is that what to use at present at most, also is most typical a kind of, and typical example has: the Galileo in GPS of USA, Muscovite GLONASS, Europe and the Compass of China.
The quick capture technique of signal is one of gordian technique of receiver baseband signal processing.The observing and controlling receiver produces local pseudo-code sequence on the satellite, must move the phase place of this local code then, up to the pseudo-code of receiving spread frequency signal take place relevant till.Simultaneously; Receiver also must detect the transmit carrier frequency of (upward signal) of ground in the carrier frequency territory; Method is to produce the local replica carrier frequency to add Doppler, utilizes the similarity of the carrier wave and the up-link carrier of correlation detection local replica, realizes carrier synchronization.Therefore, receiver is a two dimension (pseudo-code and carrier frequency or be called a time and frequency) signal replication process to the acquisition procedure of signal.
In the telemetry communication system of space, the direct sequence signal of the up band remote information that send on space observing and controlling receiver receiving demodulation ground.The up remote information of S frequency range is that low-rate modulated is used, and general the requirement is 2kbps ~ 16kbps.Simultaneously, the receiver two dimension that will accomplish carrier doppler and pseudo-code phase is caught fast.
Up direct sequence signal is being carried out two dimension fast in the acquisition procedure, the problem of modulating data upset influence to space observing and controlling receiver.The saltus step meeting of modulated data symbol is estimated Doppler and pseudo-code phase is estimated to exert an influence: promptly the spectral leakage of signal, frequency produce to squint and cause when utilizing Doppler filter group analysis signal spectrum, detecting less than correct Doppler frequency.
Summary of the invention
The purpose of this invention is to provide a kind of direct sequence signal carrier wave pseudo-code two dimension catching method of anti-text upset, this method can resist the upset of text in the acquisition procedure to direct sequence signal.
Realize that technical scheme of the present invention is following:
Step 1, required intermediate frequency direct sequence signal of catching is carried out the digital quadrature down-converted; Obtain sine, cosine two paths of signals; The sine that will obtain then, cosine two paths of signals multiply each other with said intermediate frequency direct sequence signal respectively, obtain homophase, quadrature two-way baseband signal;
Step 2, homophase, quadrature two-way baseband signal are carried out respectively 1 time, 2 times, 3 times ..., (N-1) inferior delay process obtains the parallel baseband signal in 2N road; Wherein each number of samples K=(f that delays time
s/ f
c) * (L/N), f
sRepresent sampling rate, f
cRepresent pseudo-bit rate, L representes the pseudo-code cycle;
Step 3, make the pseudo-code digital controlled oscillator produce the pseudo-code clock of 3.069MHz, pseudo-code generator generates replica code under the driving of pseudo-code clock, and the speed of the replica code that is generated is 3.069Mcps;
Step 4, utilize 2N parallel correlator that 2N roadbed band signal and replica code are carried out relevant accumulation computing respectively; The cycle that each accumulation computing wherein is set is 2ms; Promptly in the time range of 2ms; Number of samples on the signal is divided into 512 parts, the number of samples on each part is accumulated, and then obtain 2N road accumulation operation result; Homophase with same time-delay, the accumulation operation result of digital orthogonal baseband signal are merged into one the tunnel, obtain the accumulation result of N road after merging;
Step 5, the accumulation result after the N road merged adopt formula (1) and (2) to carry out a times angle processing respectively, obtain N road sets of signals, and wherein each sets of signals comprises I (n) and Q (n),
I(n)＝r
I(n)×r
I(n)-r
Q(n)×r
Q(n)（1）
Q(n)＝r
I(n)×r
Q(n)+r
Q(n)×r
I(n)（2）
R wherein
I(n) be the accumulation result of in-phase base band signal, r
Q(n) be the accumulation result of digital orthogonal baseband signal, * for multiplying, n is all integers of getting all in 1 to 512;
Step 6, to each road in the sets of signals of N road, to I (n) rear end zero padding to 1024 accumulation result, to Q (n) rear end zero padding to 1024 accumulation result; Then with the real part of I (n) as Fourier FFT conversion; With the imaginary part of Q (n) as the FFT conversion; Respectively N road signal is carried out Fast Fourier Transform (FFT); Obtain real part, imaginary part and exponential part after the FFT conversion, calculate real part and the quadratic sum of imaginary part after the FFT conversion then, obtain 1024 * N quadratic sum altogether;
Step 7, relatively 1024 * N the quadratic sum of passing through; Select wherein maximal value and preset thresholding to compare; When comparative result is preset thresholding for surpassing, then think and obtain the maximum pairing retardation of quadratic sum by acquisition success; Utilize this retardation to produce a thick synchronous replica code and be used for accurate pseudo-code tracing, and on behalf of carrier doppler, 1024 * N the corresponding FFT position of quadratic sum maximal value catch the result; When obtaining comparative result for the time less than thresholding, judge then and catch unsuccessfully that then next coherent integration period is come, control pseudo-code generator 0.5 chip that slides generates replica code, returns step 3.
Beneficial effect
The present invention is utilized in the frequency domain FFT acquisition algorithm, before FFT, adopts double angle formula that homophase, quadrature two paths of signals are handled, and eliminates the problem less than correct Doppler frequency that detects when data-modulated causes FFT to carry out doppler frequency spectrum analysis.
Description of drawings
Fig. 1 is the process flow diagram of catching method of the present invention.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment the present invention is elaborated.
This invention be embodied as a measurement and control unit, adopt hardware realizations such as FPGA and A/D converter.Fpga chip is selected U.S. Xilinx Company products XC2V3000 for use, and its dominant frequency reaches as high as 300MHz, and FPGA can reach 3,000,000.A/D conversion chip is selected the product A D10200 of U.S. Analogic Corp. for use, and its highest SF is 105MHz, and data resolution is 12.The analog if signal of input converts the intermediate frequency direct sequence signal into behind the bandpass sampling of A/D chip, in FPGA, accomplish catching of signal.
In FPGA, comprise digital quadrature down conversion module, parallel correlator group, pseudo-code generator, FFT conversion module, mould value computing module, catch processing module etc.The scheme that adopts based on frequency domain FFT parallel-time domain multidiameter delay code acquisition algorithm, the flow process of processing is as shown in Figure 1, below invention is implemented to set forth.
FPGA described in the present embodiment adopts the work clock of 38MHz, and 38MHz also uses as the change over clock of A/D simultaneously.Analog if signal is through analog to digital conversion, and the intermediate frequency direct sequence signal of the sample value of output per second 38M is through the input of 12 interfaces as FPGA.
As shown in Figure 1, concrete acquisition procedure is following:
Step 1, required intermediate frequency direct sequence signal of catching is carried out the digital quadrature down-converted; Obtain sine, cosine two paths of signals; The sine that will obtain then, cosine two paths of signals multiply each other with said intermediate frequency direct sequence signal respectively, obtain homophase, quadrature two-way baseband signal.
Step 2, through the RAM resource with the mode delay input signal of FIFO, adopt through (N-1) group RAM to postpone to handle, homophase, quadrature two-way baseband signal are become 2N road parallel signal; For homophase and digital orthogonal baseband signal, the N road is equivalent to differ in time L/N chip with respect to the N-1 road.The N road walks abreast and can realize searching for simultaneously N pseudo-code phase that is spaced apart the L/N chip like this.Concrete process is: homophase, quadrature two-way baseband signal carried out respectively 1 time, and 2 times, 3 times ..., (N-1) inferior delay process, wherein the number of samples K=(f of each time-delay
s/ f
c) * (L/N), f
sRepresent sampling rate, f
cRepresent pseudo-bit rate, L representes the pseudo-code cycle, and N representes the way that walks abreast, and then obtains the parallel baseband signal in 2N road.The L that makes preferable in this enforcement equals 1023, and the preferable N that makes equals 8, and following steps all make N equal 8 and describe.
Because each road signal has all been carried out 7 kinds of time-delays respectively, add that a road of not time-delay obtains 8 road signals altogether, therefore consider that each road comprises homophase and quadrature again; Obtain 16 road signals altogether, in the signal of resulting 2N road, if only there is 1 time-delay; Then amount of delay is K, if there are 2 time-delays, then amount of delay is 2K; And therefore analogize, obtained 16 road signals.
Differ 8 road signals of L/N code phase on the generation time successively, relevant with the local replica pseudo-code then, when local copy codes slides into certain phase place, N the phase place that be equivalent to parallel detection.
Step 3, make the pseudo-code digital controlled oscillator produce the pseudo-code clock of 3.069MHz, pseudo-code generator generates replica code under the driving of pseudo-code clock, and the speed of the replica code that is generated is 3.069Mcps.
Step 4, utilize 16 parallel correlators that 16 road homophases, digital orthogonal baseband signal are carried out relevant accumulation computing respectively with replica code; The cycle that each accumulation computing wherein is set is 2ms; Promptly in the time range of 2ms; Number of samples on the signal is divided into 512 parts, each increment is counted accumulate, and then obtain 16 tunnel integral operation results.To the homophase with same time-delay, quadrature base band data, homophase, quadrature two-way base band data are merged into one the tunnel with the relevant accumulation results of replica code, obtain 8 tunnel accumulation results after merging.
Step 5, the accumulation result after merging 8 tunnel adopt formula (1) and (2) to carry out times angle respectively and handle, and the influence of elimination data-modulated obtains N road sets of signals, and wherein each sets of signals comprises I (n) and Q (n),
I(n)＝r
I(n)×r
I(n)-r
Q(n)×r
Q(n)（1）
Q(n)＝r
I(n)×r
Q(n)+r
Q(n)×r
I(n)（2）
R wherein
I(n) be the accumulation result of in-phase base band signal, r
Q(n) be the accumulation result of digital orthogonal baseband signal, * for multiplying, n is all integers of getting all in 1 to 512.
The homophase accumulation result I (n) and the quadrature accumulation result Q (n) that computing are obtained, eliminate the influence of data-modulated are kept in the inside dual port RAM of FPGA.Because the result that each 2ms time produces is 8 tunnel 512 values, be kept at by ping-pong operation in the internal RAM of FPGA, therefore 16 storage depths of needs are 512 block RAM.
Step 6, sense data from the inner dual port RAM of FPGA successively are to each road in the sets of signals of N road, to I (n) rear end zero padding to 1024 accumulation result, to Q (n) rear end zero padding to 1024 accumulation result; Then with the real part of I (n) as Fourier FFT conversion; With the imaginary part of Q (n) as the FFT conversion; 8 road signals are accomplished Fast Fourier Transform (FFT) respectively and are calculated, and the FFT computing uses the IP kernel of Xilinx company to realize real part, imaginary part and exponential part that the exportable FFT computing of this IP kernel obtains; The quadratic sum that calculates real part and imaginary part after the FFT conversion is delivered to peak value and is detected, and the quadratic sum that wherein calculates has 1024 * 8=8192.
Step 7, relatively 8192 quadratic sums of passing through; Select wherein maximal value and preset thresholding to compare; When comparative result is preset thresholding for surpassing, then think and obtain the maximum pairing retardation of quadratic sum by acquisition success; Utilize this retardation to produce a thick synchronous replica code and be used for accurate pseudo-code tracing, and the doppler values of catching has been represented in the corresponding FFT position of maximal value; When comparative result is less than thresholding, judge then and catch unsuccessfully that come to next coherent integration period, the slip of a sign indicating number NCO control replica code chip gets into next group code phase search unit.
Use the coherent integration period of 2ms, use the counter cycle count, when reaching 2ms+t
1Constantly, the register of pseudo-code generator is composed and is first phase value, the value zero clearing of unison counter.According to t
1Can calculate the number of chips that each replica code slides, every 2ms once slides.Known integration period is 2ms, t
1Be chosen as 1 ~ 9 work clock cycle.
Use the coherent integration period of 2ms, the frequency resolution of FFT is 1/2ms=500Hz, and 2ms sampling point integration is 512 accumulated values, and corresponding capturing carrier scope is 500Hz * 512/2=128kHz, promptly-and 64kHz ~+63kHz.Adopt 1024 FFT, the corresponding frequency resolution of catching of each FFT sample value is 128kHz/1024=125Hz.
The present invention can overcome the influence that the text upset is caught carrier doppler, has capturing carrier speed and high reliability fast.And combine to realize that with time-domain parallel multichannel pseudo-code searching method carrier wave and pseudo-code two dimension catch fast.
In sum, more than being merely preferred embodiment of the present invention, is not to be used to limit protection scope of the present invention.All within spirit of the present invention and principle, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (1)
1. the direct sequence signal carrier wave pseudo-code two dimension catching method of an anti-text upset is characterized in that,
Step 1, required that catch, intermediate frequency direct sequence signal is carried out the digital quadrature down-converted; Obtain sine, cosine two paths of signals; The sine that will obtain then, cosine two paths of signals multiply each other with said intermediate frequency direct sequence signal respectively, obtain homophase, quadrature two-way baseband signal;
Step 2, homophase, quadrature two-way baseband signal are carried out respectively 1 time, 2 times, 3 times ..., (N-1) inferior delay process obtains the parallel baseband signal in 2N road; Wherein each number of samples K=(f that delays time
s/ f
c) * (L/N), f
sRepresent sampling rate, f
cRepresent pseudo-bit rate, L representes the pseudo-code cycle;
Step 3, make the pseudo-code digital controlled oscillator produce the pseudo-code clock of 3.069MHz, pseudo-code generator generates replica code under the driving of pseudo-code clock, and the speed of the replica code that is generated is 3.069Mcps;
Step 4, utilize 2N parallel correlator that 2N roadbed band signal and replica code are carried out relevant accumulation computing respectively; The cycle that each accumulation computing wherein is set is 2ms; Promptly in the time range of 2ms; Number of samples on the signal is divided into 512 parts, the number of samples on each part is accumulated, and then obtain 2N road accumulation operation result; Homophase with same time-delay, the accumulation operation result of digital orthogonal baseband signal are merged into one the tunnel, obtain the accumulation result of N road after merging;
Step 5, the accumulation result after the N road merged adopt formula (1) and (2) to carry out a times angle processing respectively, obtain N road sets of signals, and wherein each sets of signals comprises I (n) and Q (n),
I(n)＝r
I(n)×r
I(n)-r
Q(n)×r
Q(n)（1）
Q(n)＝r
I(n)×r
Q(n)+r
Q(n)×r
I(n)（2）
R wherein
I(n) be the accumulation result of in-phase base band signal, r
Q(n) be the accumulation result of digital orthogonal baseband signal, * for multiplying, n is all integers of getting all in 1 to 512;
Step 6, to each road in the sets of signals of N road, to I (n) rear end zero padding to 1024 accumulation result, to Q (n) rear end zero padding to 1024 accumulation result; Then with the real part of I (n) as Fourier FFT conversion; With the imaginary part of Q (n) as the FFT conversion; Respectively N road signal is carried out Fast Fourier Transform (FFT); Obtain real part, imaginary part and exponential part after the FFT conversion, calculate real part and the quadratic sum of imaginary part after the FFT conversion then, obtain 1024 * N quadratic sum altogether;
Step 7, relatively 1024 * N the quadratic sum of passing through; Select wherein maximal value and preset thresholding to compare; When comparative result is preset thresholding for surpassing; Then think and obtain the maximum pairing retardation of quadratic sum by acquisition success, utilize this retardation to produce a thick synchronous replica code and be used for accurate pseudo-code tracing; When obtaining comparative result for the time less than thresholding, judge then and catch unsuccessfully that then next coherent integration period is come, control pseudo-code generator 0.5 chip that slides generates replica code, returns step 3.
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| CN111262618B (en) * | 2020-01-17 | 2020-09-29 | 北京理工大学 | Solution method for multi-target measurement and control signal parallel access based on same pseudo code |
| CN115065380A (en) * | 2022-03-31 | 2022-09-16 | 北京全路通信信号研究设计院集团有限公司 | Pseudo code synchronization method and device, electronic equipment and storage medium |
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